MachineInstr.cpp revision e722c3f005ae1e96250ddd3577f9eb56a8ad14cb 
1//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/Target/TargetMachine.h"
17#include "llvm/Target/TargetInstrInfo.h"
18#include "llvm/Target/MRegisterInfo.h"
19#include "llvm/Support/LeakDetector.h"
20#include "llvm/Support/Streams.h"
21#include <ostream>
22using namespace llvm;
23
24/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
25/// TID NULL and no operands.
26MachineInstr::MachineInstr()
27  : TID(0), NumImplicitOps(0), parent(0) {
28  // Make sure that we get added to a machine basicblock
29  LeakDetector::addGarbageObject(this);
30}
31
32void MachineInstr::addImplicitDefUseOperands() {
33  if (TID->ImplicitDefs)
34    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
35      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
36  if (TID->ImplicitUses)
37    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
38      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
39}
40
41/// MachineInstr ctor - This constructor create a MachineInstr and add the
42/// implicit operands. It reserves space for number of operands specified by
43/// TargetInstrDescriptor or the numOperands if it is not zero. (for
44/// instructions with variable number of operands).
45MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
46  : TID(&tid), NumImplicitOps(0), parent(0) {
47  if (!NoImp && TID->ImplicitDefs)
48    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
49      NumImplicitOps++;
50  if (!NoImp && TID->ImplicitUses)
51    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
52      NumImplicitOps++;
53  Operands.reserve(NumImplicitOps + TID->numOperands);
54  if (!NoImp)
55    addImplicitDefUseOperands();
56  // Make sure that we get added to a machine basicblock
57  LeakDetector::addGarbageObject(this);
58}
59
60/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
61/// MachineInstr is created and added to the end of the specified basic block.
62///
63MachineInstr::MachineInstr(MachineBasicBlock *MBB,
64                           const TargetInstrDescriptor &tid)
65  : TID(&tid), NumImplicitOps(0), parent(0) {
66  assert(MBB && "Cannot use inserting ctor with null basic block!");
67  if (TID->ImplicitDefs)
68    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
69      NumImplicitOps++;
70  if (TID->ImplicitUses)
71    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
72      NumImplicitOps++;
73  Operands.reserve(NumImplicitOps + TID->numOperands);
74  addImplicitDefUseOperands();
75  // Make sure that we get added to a machine basicblock
76  LeakDetector::addGarbageObject(this);
77  MBB->push_back(this);  // Add instruction to end of basic block!
78}
79
80/// MachineInstr ctor - Copies MachineInstr arg exactly
81///
82MachineInstr::MachineInstr(const MachineInstr &MI) {
83  TID = MI.getInstrDescriptor();
84  NumImplicitOps = MI.NumImplicitOps;
85  Operands.reserve(MI.getNumOperands());
86
87  // Add operands
88  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
89    Operands.push_back(MI.getOperand(i));
90    Operands.back().ParentMI = this;
91  }
92
93  // Set parent, next, and prev to null
94  parent = 0;
95  prev = 0;
96  next = 0;
97}
98
99
100MachineInstr::~MachineInstr() {
101  LeakDetector::removeGarbageObject(this);
102#ifndef NDEBUG
103  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
104    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
105#endif
106}
107
108/// getOpcode - Returns the opcode of this MachineInstr.
109///
110int MachineInstr::getOpcode() const {
111  return TID->Opcode;
112}
113
114/// removeFromParent - This method unlinks 'this' from the containing basic
115/// block, and returns it, but does not delete it.
116MachineInstr *MachineInstr::removeFromParent() {
117  assert(getParent() && "Not embedded in a basic block!");
118  getParent()->remove(this);
119  return this;
120}
121
122
123/// OperandComplete - Return true if it's illegal to add a new operand
124///
125bool MachineInstr::OperandsComplete() const {
126  unsigned short NumOperands = TID->numOperands;
127  if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
128      getNumOperands()-NumImplicitOps >= NumOperands)
129    return true;  // Broken: we have all the operands of this instruction!
130  return false;
131}
132
133/// getNumExplicitOperands - Returns the number of non-implicit operands.
134///
135unsigned MachineInstr::getNumExplicitOperands() const {
136  unsigned NumOperands = TID->numOperands;
137  if ((TID->Flags & M_VARIABLE_OPS) == 0)
138    return NumOperands;
139
140  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
141    const MachineOperand &MO = getOperand(NumOperands);
142    if (!MO.isRegister() || !MO.isImplicit())
143      NumOperands++;
144  }
145  return NumOperands;
146}
147
148/// isIdenticalTo - Return true if this operand is identical to the specified
149/// operand.
150bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
151  if (getType() != Other.getType()) return false;
152
153  switch (getType()) {
154  default: assert(0 && "Unrecognized operand type");
155  case MachineOperand::MO_Register:
156    return getReg() == Other.getReg() && isDef() == Other.isDef();
157  case MachineOperand::MO_Immediate:
158    return getImm() == Other.getImm();
159  case MachineOperand::MO_MachineBasicBlock:
160    return getMBB() == Other.getMBB();
161  case MachineOperand::MO_FrameIndex:
162    return getFrameIndex() == Other.getFrameIndex();
163  case MachineOperand::MO_ConstantPoolIndex:
164    return getConstantPoolIndex() == Other.getConstantPoolIndex() &&
165           getOffset() == Other.getOffset();
166  case MachineOperand::MO_JumpTableIndex:
167    return getJumpTableIndex() == Other.getJumpTableIndex();
168  case MachineOperand::MO_GlobalAddress:
169    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
170  case MachineOperand::MO_ExternalSymbol:
171    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
172           getOffset() == Other.getOffset();
173  }
174}
175
176/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
177/// the specific register or -1 if it is not found. It further tightening
178/// the search criteria to a use that kills the register if isKill is true.
179int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
180  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
181    const MachineOperand &MO = getOperand(i);
182    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
183      if (!isKill || MO.isKill())
184        return i;
185  }
186  return -1;
187}
188
189/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
190/// the specific register or NULL if it is not found.
191MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
192  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
193    MachineOperand &MO = getOperand(i);
194    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
195      return &MO;
196  }
197  return NULL;
198}
199
200/// findFirstPredOperandIdx() - Find the index of the first operand in the
201/// operand list that is used to represent the predicate. It returns -1 if
202/// none is found.
203int MachineInstr::findFirstPredOperandIdx() const {
204  const TargetInstrDescriptor *TID = getInstrDescriptor();
205  if (TID->Flags & M_PREDICABLE) {
206    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
207      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND))
208        return i;
209  }
210
211  return -1;
212}
213
214/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
215/// to two addr elimination.
216bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
217  const TargetInstrDescriptor *TID = getInstrDescriptor();
218  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
219    const MachineOperand &MO1 = getOperand(i);
220    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
221      for (unsigned j = i+1; j < e; ++j) {
222        const MachineOperand &MO2 = getOperand(j);
223        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
224            TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
225          return true;
226      }
227    }
228  }
229  return false;
230}
231
232/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
233///
234void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
235  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
236    const MachineOperand &MO = MI->getOperand(i);
237    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
238      continue;
239    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
240      MachineOperand &MOp = getOperand(j);
241      if (!MOp.isIdenticalTo(MO))
242        continue;
243      if (MO.isKill())
244        MOp.setIsKill();
245      else
246        MOp.setIsDead();
247      break;
248    }
249  }
250}
251
252/// copyPredicates - Copies predicate operand(s) from MI.
253void MachineInstr::copyPredicates(const MachineInstr *MI) {
254  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
255  if (TID->Flags & M_PREDICABLE) {
256    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
257      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
258        // Predicated operands must be last operands.
259        addOperand(MI->getOperand(i));
260      }
261    }
262  }
263}
264
265void MachineInstr::dump() const {
266  cerr << "  " << *this;
267}
268
269static inline void OutputReg(std::ostream &os, unsigned RegNo,
270                             const MRegisterInfo *MRI = 0) {
271  if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
272    if (MRI)
273      os << "%" << MRI->get(RegNo).Name;
274    else
275      os << "%mreg(" << RegNo << ")";
276  } else
277    os << "%reg" << RegNo;
278}
279
280static void print(const MachineOperand &MO, std::ostream &OS,
281                  const TargetMachine *TM) {
282  const MRegisterInfo *MRI = 0;
283
284  if (TM) MRI = TM->getRegisterInfo();
285
286  switch (MO.getType()) {
287  case MachineOperand::MO_Register:
288    OutputReg(OS, MO.getReg(), MRI);
289    break;
290  case MachineOperand::MO_Immediate:
291    OS << MO.getImmedValue();
292    break;
293  case MachineOperand::MO_MachineBasicBlock:
294    OS << "mbb<"
295       << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
296       << "," << (void*)MO.getMachineBasicBlock() << ">";
297    break;
298  case MachineOperand::MO_FrameIndex:
299    OS << "<fi#" << MO.getFrameIndex() << ">";
300    break;
301  case MachineOperand::MO_ConstantPoolIndex:
302    OS << "<cp#" << MO.getConstantPoolIndex() << ">";
303    break;
304  case MachineOperand::MO_JumpTableIndex:
305    OS << "<jt#" << MO.getJumpTableIndex() << ">";
306    break;
307  case MachineOperand::MO_GlobalAddress:
308    OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
309    if (MO.getOffset()) OS << "+" << MO.getOffset();
310    OS << ">";
311    break;
312  case MachineOperand::MO_ExternalSymbol:
313    OS << "<es:" << MO.getSymbolName();
314    if (MO.getOffset()) OS << "+" << MO.getOffset();
315    OS << ">";
316    break;
317  default:
318    assert(0 && "Unrecognized operand type");
319  }
320}
321
322void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
323  unsigned StartOp = 0;
324
325   // Specialize printing if op#0 is definition
326  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
327    ::print(getOperand(0), OS, TM);
328    if (getOperand(0).isDead())
329      OS << "<dead>";
330    OS << " = ";
331    ++StartOp;   // Don't print this operand again!
332  }
333
334  if (TID)
335    OS << TID->Name;
336
337  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
338    const MachineOperand& mop = getOperand(i);
339    if (i != StartOp)
340      OS << ",";
341    OS << " ";
342    ::print(mop, OS, TM);
343
344    if (mop.isRegister()) {
345      if (mop.isDef() || mop.isKill() || mop.isDead() || mop.isImplicit()) {
346        OS << "<";
347        bool NeedComma = false;
348        if (mop.isImplicit()) {
349          OS << (mop.isDef() ? "imp-def" : "imp-use");
350          NeedComma = true;
351        } else if (mop.isDef()) {
352          OS << "def";
353          NeedComma = true;
354        }
355        if (mop.isKill() || mop.isDead()) {
356          if (NeedComma)
357            OS << ",";
358          if (mop.isKill())
359            OS << "kill";
360          if (mop.isDead())
361            OS << "dead";
362        }
363        OS << ">";
364      }
365    }
366  }
367
368  OS << "\n";
369}
370
371void MachineInstr::print(std::ostream &os) const {
372  // If the instruction is embedded into a basic block, we can find the target
373  // info for the instruction.
374  if (const MachineBasicBlock *MBB = getParent()) {
375    const MachineFunction *MF = MBB->getParent();
376    if (MF)
377      print(os, &MF->getTarget());
378    else
379      print(os, 0);
380  }
381
382  // Otherwise, print it out in the "raw" format without symbolic register names
383  // and such.
384  os << getInstrDescriptor()->Name;
385
386  for (unsigned i = 0, N = getNumOperands(); i < N; i++) {
387    os << "\t" << getOperand(i);
388    if (getOperand(i).isRegister() && getOperand(i).isDef())
389      os << "<d>";
390  }
391
392  os << "\n";
393}
394
395void MachineOperand::print(std::ostream &OS) const {
396  switch (getType()) {
397  case MO_Register:
398    OutputReg(OS, getReg());
399    break;
400  case MO_Immediate:
401    OS << (long)getImmedValue();
402    break;
403  case MO_MachineBasicBlock:
404    OS << "<mbb:"
405       << ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
406       << "@" << (void*)getMachineBasicBlock() << ">";
407    break;
408  case MO_FrameIndex:
409    OS << "<fi#" << getFrameIndex() << ">";
410    break;
411  case MO_ConstantPoolIndex:
412    OS << "<cp#" << getConstantPoolIndex() << ">";
413    break;
414  case MO_JumpTableIndex:
415    OS << "<jt#" << getJumpTableIndex() << ">";
416    break;
417  case MO_GlobalAddress:
418    OS << "<ga:" << ((Value*)getGlobal())->getName() << ">";
419    break;
420  case MO_ExternalSymbol:
421    OS << "<es:" << getSymbolName() << ">";
422    break;
423  default:
424    assert(0 && "Unrecognized operand type");
425    break;
426  }
427}
428
429