MachineLICM.cpp revision 4038f9c21b17378617c25f3092fe615326f8b874
1//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass performs loop invariant code motion on machine instructions. We 11// attempt to remove as much code from the body of a loop as possible. 12// 13// This pass does not attempt to throttle itself to limit register pressure. 14// The register allocation phases are expected to perform rematerialization 15// to recover when register pressure is high. 16// 17// This pass is not intended to be a replacement or a complete alternative 18// for the LLVM-IR-level LICM pass. It is only designed to hoist simple 19// constructs that are not exposed before lowering and instruction selection. 20// 21//===----------------------------------------------------------------------===// 22 23#define DEBUG_TYPE "machine-licm" 24#include "llvm/CodeGen/Passes.h" 25#include "llvm/CodeGen/MachineDominators.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineLoopInfo.h" 28#include "llvm/CodeGen/MachineMemOperand.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/PseudoSourceValue.h" 31#include "llvm/Target/TargetRegisterInfo.h" 32#include "llvm/Target/TargetInstrInfo.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Analysis/AliasAnalysis.h" 35#include "llvm/ADT/DenseMap.h" 36#include "llvm/ADT/SmallSet.h" 37#include "llvm/ADT/Statistic.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Support/raw_ostream.h" 40 41using namespace llvm; 42 43STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops"); 44STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed"); 45STATISTIC(NumPostRAHoisted, 46 "Number of machine instructions hoisted out of loops post regalloc"); 47 48namespace { 49 class MachineLICM : public MachineFunctionPass { 50 bool PreRegAlloc; 51 52 const TargetMachine *TM; 53 const TargetInstrInfo *TII; 54 const TargetRegisterInfo *TRI; 55 const MachineFrameInfo *MFI; 56 MachineRegisterInfo *RegInfo; 57 58 // Various analyses that we use... 59 AliasAnalysis *AA; // Alias analysis info. 60 MachineLoopInfo *MLI; // Current MachineLoopInfo 61 MachineDominatorTree *DT; // Machine dominator tree for the cur loop 62 63 // State that is updated as we process loops 64 bool Changed; // True if a loop is changed. 65 MachineLoop *CurLoop; // The current loop we are working on. 66 MachineBasicBlock *CurPreheader; // The preheader for CurLoop. 67 68 BitVector AllocatableSet; 69 70 // For each opcode, keep a list of potentail CSE instructions. 71 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap; 72 73 public: 74 static char ID; // Pass identification, replacement for typeid 75 MachineLICM() : 76 MachineFunctionPass(&ID), PreRegAlloc(true) {} 77 78 explicit MachineLICM(bool PreRA) : 79 MachineFunctionPass(&ID), PreRegAlloc(PreRA) {} 80 81 virtual bool runOnMachineFunction(MachineFunction &MF); 82 83 const char *getPassName() const { return "Machine Instruction LICM"; } 84 85 // FIXME: Loop preheaders? 86 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 87 AU.setPreservesCFG(); 88 AU.addRequired<MachineLoopInfo>(); 89 AU.addRequired<MachineDominatorTree>(); 90 AU.addRequired<AliasAnalysis>(); 91 AU.addPreserved<MachineLoopInfo>(); 92 AU.addPreserved<MachineDominatorTree>(); 93 MachineFunctionPass::getAnalysisUsage(AU); 94 } 95 96 virtual void releaseMemory() { 97 CSEMap.clear(); 98 } 99 100 private: 101 /// CandidateInfo - Keep track of information about hoisting candidates. 102 struct CandidateInfo { 103 MachineInstr *MI; 104 int FI; 105 unsigned Def; 106 CandidateInfo(MachineInstr *mi, int fi, unsigned def) 107 : MI(mi), FI(fi), Def(def) {} 108 }; 109 110 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop 111 /// invariants out to the preheader. 112 void HoistRegionPostRA(MachineDomTreeNode *N); 113 114 /// HoistPostRA - When an instruction is found to only use loop invariant 115 /// operands that is safe to hoist, this instruction is called to do the 116 /// dirty work. 117 void HoistPostRA(MachineInstr *MI, unsigned Def); 118 119 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also 120 /// gather register def and frame object update information. 121 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs, 122 SmallSet<int, 32> &StoredFIs, 123 SmallVector<CandidateInfo, 32> &Candidates); 124 125 /// AddToLiveIns - Add 'Reg' to the livein sets of BBs in the backedge path 126 /// from MBB to LoopHeader (inclusive). 127 void AddToLiveIns(unsigned Reg, 128 MachineBasicBlock *MBB, MachineBasicBlock *LoopHeader); 129 130 /// IsLoopInvariantInst - Returns true if the instruction is loop 131 /// invariant. I.e., all virtual register operands are defined outside of 132 /// the loop, physical registers aren't accessed (explicitly or implicitly), 133 /// and the instruction is hoistable. 134 /// 135 bool IsLoopInvariantInst(MachineInstr &I); 136 137 /// IsProfitableToHoist - Return true if it is potentially profitable to 138 /// hoist the given loop invariant. 139 bool IsProfitableToHoist(MachineInstr &MI); 140 141 /// HoistRegion - Walk the specified region of the CFG (defined by all 142 /// blocks dominated by the specified block, and that are in the current 143 /// loop) in depth first order w.r.t the DominatorTree. This allows us to 144 /// visit definitions before uses, allowing us to hoist a loop body in one 145 /// pass without iteration. 146 /// 147 void HoistRegion(MachineDomTreeNode *N); 148 149 /// isLoadFromConstantMemory - Return true if the given instruction is a 150 /// load from constant memory. 151 bool isLoadFromConstantMemory(MachineInstr *MI); 152 153 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if 154 /// the load itself could be hoisted. Return the unfolded and hoistable 155 /// load, or null if the load couldn't be unfolded or if it wouldn't 156 /// be hoistable. 157 MachineInstr *ExtractHoistableLoad(MachineInstr *MI); 158 159 /// LookForDuplicate - Find an instruction amount PrevMIs that is a 160 /// duplicate of MI. Return this instruction if it's found. 161 const MachineInstr *LookForDuplicate(const MachineInstr *MI, 162 std::vector<const MachineInstr*> &PrevMIs); 163 164 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on 165 /// the preheader that compute the same value. If it's found, do a RAU on 166 /// with the definition of the existing instruction rather than hoisting 167 /// the instruction to the preheader. 168 bool EliminateCSE(MachineInstr *MI, 169 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI); 170 171 /// Hoist - When an instruction is found to only use loop invariant operands 172 /// that is safe to hoist, this instruction is called to do the dirty work. 173 /// 174 void Hoist(MachineInstr *MI); 175 176 /// InitCSEMap - Initialize the CSE map with instructions that are in the 177 /// current loop preheader that may become duplicates of instructions that 178 /// are hoisted out of the loop. 179 void InitCSEMap(MachineBasicBlock *BB); 180 }; 181} // end anonymous namespace 182 183char MachineLICM::ID = 0; 184static RegisterPass<MachineLICM> 185X("machinelicm", "Machine Loop Invariant Code Motion"); 186 187FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) { 188 return new MachineLICM(PreRegAlloc); 189} 190 191/// LoopIsOuterMostWithPreheader - Test if the given loop is the outer-most 192/// loop that has a preheader. 193static bool LoopIsOuterMostWithPreheader(MachineLoop *CurLoop) { 194 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop()) 195 if (L->getLoopPreheader()) 196 return false; 197 return true; 198} 199 200/// Hoist expressions out of the specified loop. Note, alias info for inner loop 201/// is not preserved so it is not a good idea to run LICM multiple times on one 202/// loop. 203/// 204bool MachineLICM::runOnMachineFunction(MachineFunction &MF) { 205 if (PreRegAlloc) 206 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n"); 207 else 208 DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n"); 209 210 Changed = false; 211 TM = &MF.getTarget(); 212 TII = TM->getInstrInfo(); 213 TRI = TM->getRegisterInfo(); 214 MFI = MF.getFrameInfo(); 215 RegInfo = &MF.getRegInfo(); 216 AllocatableSet = TRI->getAllocatableSet(MF); 217 218 // Get our Loop information... 219 MLI = &getAnalysis<MachineLoopInfo>(); 220 DT = &getAnalysis<MachineDominatorTree>(); 221 AA = &getAnalysis<AliasAnalysis>(); 222 223 for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I){ 224 CurLoop = *I; 225 226 // If this is done before regalloc, only visit outer-most preheader-sporting 227 // loops. 228 if (PreRegAlloc && !LoopIsOuterMostWithPreheader(CurLoop)) 229 continue; 230 231 // Determine the block to which to hoist instructions. If we can't find a 232 // suitable loop preheader, we can't do any hoisting. 233 // 234 // FIXME: We are only hoisting if the basic block coming into this loop 235 // has only one successor. This isn't the case in general because we haven't 236 // broken critical edges or added preheaders. 237 CurPreheader = CurLoop->getLoopPreheader(); 238 if (!CurPreheader) 239 continue; 240 241 // CSEMap is initialized for loop header when the first instruction is 242 // being hoisted. 243 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader()); 244 if (!PreRegAlloc) 245 HoistRegionPostRA(N); 246 else { 247 HoistRegion(N); 248 CSEMap.clear(); 249 } 250 } 251 252 return Changed; 253} 254 255/// InstructionStoresToFI - Return true if instruction stores to the 256/// specified frame. 257static bool InstructionStoresToFI(const MachineInstr *MI, int FI) { 258 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 259 oe = MI->memoperands_end(); o != oe; ++o) { 260 if (!(*o)->isStore() || !(*o)->getValue()) 261 continue; 262 if (const FixedStackPseudoSourceValue *Value = 263 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 264 if (Value->getFrameIndex() == FI) 265 return true; 266 } 267 } 268 return false; 269} 270 271/// ProcessMI - Examine the instruction for potentai LICM candidate. Also 272/// gather register def and frame object update information. 273void MachineLICM::ProcessMI(MachineInstr *MI, 274 unsigned *PhysRegDefs, 275 SmallSet<int, 32> &StoredFIs, 276 SmallVector<CandidateInfo, 32> &Candidates) { 277 bool RuledOut = false; 278 unsigned Def = 0; 279 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 280 const MachineOperand &MO = MI->getOperand(i); 281 if (MO.isFI()) { 282 // Remember if the instruction stores to the frame index. 283 int FI = MO.getIndex(); 284 if (!StoredFIs.count(FI) && 285 MFI->isSpillSlotObjectIndex(FI) && 286 InstructionStoresToFI(MI, FI)) 287 StoredFIs.insert(FI); 288 continue; 289 } 290 291 if (!MO.isReg()) 292 continue; 293 unsigned Reg = MO.getReg(); 294 if (!Reg) 295 continue; 296 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 297 "Not expecting virtual register!"); 298 299 if (!MO.isDef()) 300 continue; 301 302 if (MO.isImplicit()) { 303 ++PhysRegDefs[Reg]; 304 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 305 ++PhysRegDefs[*AS]; 306 if (!MO.isDead()) 307 // Non-dead implicit def? This cannot be hoisted. 308 RuledOut = true; 309 // No need to check if a dead implicit def is also defined by 310 // another instruction. 311 continue; 312 } 313 314 // FIXME: For now, avoid instructions with multiple defs, unless 315 // it's a dead implicit def. 316 if (Def) 317 RuledOut = true; 318 else 319 Def = Reg; 320 321 // If we have already seen another instruction that defines the same 322 // register, then this is not safe. 323 if (++PhysRegDefs[Reg] > 1) 324 // MI defined register is seen defined by another instruction in 325 // the loop, it cannot be a LICM candidate. 326 RuledOut = true; 327 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 328 if (++PhysRegDefs[*AS] > 1) 329 RuledOut = true; 330 } 331 332 // FIXME: Only consider reloads for now. We should be able to handle 333 // remats which does not have register operands. 334 if (Def && !RuledOut) { 335 int FI; 336 if (TII->isLoadFromStackSlot(MI, FI) && 337 MFI->isSpillSlotObjectIndex(FI)) 338 Candidates.push_back(CandidateInfo(MI, FI, Def)); 339 } 340} 341 342/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop 343/// invariants out to the preheader. 344void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) { 345 assert(N != 0 && "Null dominator tree node?"); 346 347 unsigned NumRegs = TRI->getNumRegs(); 348 unsigned *PhysRegDefs = new unsigned[NumRegs]; 349 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0); 350 351 SmallVector<CandidateInfo, 32> Candidates; 352 SmallSet<int, 32> StoredFIs; 353 354 // Walk the entire region, count number of defs for each register, and 355 // return potential LICM candidates. 356 SmallVector<MachineDomTreeNode*, 8> WorkList; 357 WorkList.push_back(N); 358 do { 359 N = WorkList.pop_back_val(); 360 MachineBasicBlock *BB = N->getBlock(); 361 362 if (!CurLoop->contains(MLI->getLoopFor(BB))) 363 continue; 364 // Conservatively treat live-in's as an external def. 365 // FIXME: That means a reload that're reused in successor block(s) will not 366 // be LICM'ed. 367 for (MachineBasicBlock::const_livein_iterator I = BB->livein_begin(), 368 E = BB->livein_end(); I != E; ++I) { 369 unsigned Reg = *I; 370 ++PhysRegDefs[Reg]; 371 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 372 ++PhysRegDefs[*AS]; 373 } 374 375 for (MachineBasicBlock::iterator 376 MII = BB->begin(), E = BB->end(); MII != E; ++MII) { 377 MachineInstr *MI = &*MII; 378 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates); 379 } 380 381 const std::vector<MachineDomTreeNode*> &Children = N->getChildren(); 382 for (unsigned I = 0, E = Children.size(); I != E; ++I) 383 WorkList.push_back(Children[I]); 384 } while (!WorkList.empty()); 385 386 // Now evaluate whether the potential candidates qualify. 387 // 1. Check if the candidate defined register is defined by another 388 // instruction in the loop. 389 // 2. If the candidate is a load from stack slot (always true for now), 390 // check if the slot is stored anywhere in the loop. 391 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) { 392 if (StoredFIs.count(Candidates[i].FI)) 393 continue; 394 395 if (PhysRegDefs[Candidates[i].Def] == 1) 396 HoistPostRA(Candidates[i].MI, Candidates[i].Def); 397 } 398} 399 400/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the 401/// backedge path from MBB to LoopHeader. 402void MachineLICM::AddToLiveIns(unsigned Reg, MachineBasicBlock *MBB, 403 MachineBasicBlock *LoopHeader) { 404 SmallPtrSet<MachineBasicBlock*, 4> Visited; 405 SmallVector<MachineBasicBlock*, 4> WorkList; 406 WorkList.push_back(MBB); 407 do { 408 MBB = WorkList.pop_back_val(); 409 if (!Visited.insert(MBB)) 410 continue; 411 MBB->addLiveIn(Reg); 412 if (MBB == LoopHeader) 413 continue; 414 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), 415 E = MBB->pred_end(); PI != E; ++PI) 416 WorkList.push_back(*PI); 417 } while (!WorkList.empty()); 418} 419 420/// HoistPostRA - When an instruction is found to only use loop invariant 421/// operands that is safe to hoist, this instruction is called to do the 422/// dirty work. 423void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) { 424 // Now move the instructions to the predecessor, inserting it before any 425 // terminator instructions. 426 DEBUG({ 427 dbgs() << "Hoisting " << *MI; 428 if (CurPreheader->getBasicBlock()) 429 dbgs() << " to MachineBasicBlock " 430 << CurPreheader->getName(); 431 if (MI->getParent()->getBasicBlock()) 432 dbgs() << " from MachineBasicBlock " 433 << MI->getParent()->getName(); 434 dbgs() << "\n"; 435 }); 436 437 // Splice the instruction to the preheader. 438 MachineBasicBlock *MBB = MI->getParent(); 439 CurPreheader->splice(CurPreheader->getFirstTerminator(), MBB, MI); 440 441 // Add register to livein list to BBs in the path from loop header to original 442 // BB. Note, currently it's not necessary to worry about adding it to all BB's 443 // with uses. Reload that're reused in successor block(s) are not being 444 // hoisted. 445 AddToLiveIns(Def, MBB, CurLoop->getHeader()); 446 447 ++NumPostRAHoisted; 448 Changed = true; 449} 450 451/// HoistRegion - Walk the specified region of the CFG (defined by all blocks 452/// dominated by the specified block, and that are in the current loop) in depth 453/// first order w.r.t the DominatorTree. This allows us to visit definitions 454/// before uses, allowing us to hoist a loop body in one pass without iteration. 455/// 456void MachineLICM::HoistRegion(MachineDomTreeNode *N) { 457 assert(N != 0 && "Null dominator tree node?"); 458 MachineBasicBlock *BB = N->getBlock(); 459 460 // If this subregion is not in the top level loop at all, exit. 461 if (!CurLoop->contains(BB)) return; 462 463 for (MachineBasicBlock::iterator 464 MII = BB->begin(), E = BB->end(); MII != E; ) { 465 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 466 Hoist(&*MII); 467 MII = NextMII; 468 } 469 470 const std::vector<MachineDomTreeNode*> &Children = N->getChildren(); 471 for (unsigned I = 0, E = Children.size(); I != E; ++I) 472 HoistRegion(Children[I]); 473} 474 475/// IsLoopInvariantInst - Returns true if the instruction is loop 476/// invariant. I.e., all virtual register operands are defined outside of the 477/// loop, physical registers aren't accessed explicitly, and there are no side 478/// effects that aren't captured by the operands or other flags. 479/// 480bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) { 481 const TargetInstrDesc &TID = I.getDesc(); 482 483 // Ignore stuff that we obviously can't hoist. 484 if (TID.mayStore() || TID.isCall() || TID.isTerminator() || 485 TID.hasUnmodeledSideEffects()) 486 return false; 487 488 if (TID.mayLoad()) { 489 // Okay, this instruction does a load. As a refinement, we allow the target 490 // to decide whether the loaded value is actually a constant. If so, we can 491 // actually use it as a load. 492 if (!I.isInvariantLoad(AA)) 493 // FIXME: we should be able to hoist loads with no other side effects if 494 // there are no other instructions which can change memory in this loop. 495 // This is a trivial form of alias analysis. 496 return false; 497 } 498 499 // The instruction is loop invariant if all of its operands are. 500 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 501 const MachineOperand &MO = I.getOperand(i); 502 503 if (!MO.isReg()) 504 continue; 505 506 unsigned Reg = MO.getReg(); 507 if (Reg == 0) continue; 508 509 // Don't hoist an instruction that uses or defines a physical register. 510 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 511 if (MO.isUse()) { 512 // If the physreg has no defs anywhere, it's just an ambient register 513 // and we can freely move its uses. Alternatively, if it's allocatable, 514 // it could get allocated to something with a def during allocation. 515 if (!RegInfo->def_empty(Reg)) 516 return false; 517 if (AllocatableSet.test(Reg)) 518 return false; 519 // Check for a def among the register's aliases too. 520 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 521 unsigned AliasReg = *Alias; 522 if (!RegInfo->def_empty(AliasReg)) 523 return false; 524 if (AllocatableSet.test(AliasReg)) 525 return false; 526 } 527 // Otherwise it's safe to move. 528 continue; 529 } else if (!MO.isDead()) { 530 // A def that isn't dead. We can't move it. 531 return false; 532 } else if (CurLoop->getHeader()->isLiveIn(Reg)) { 533 // If the reg is live into the loop, we can't hoist an instruction 534 // which would clobber it. 535 return false; 536 } 537 } 538 539 if (!MO.isUse()) 540 continue; 541 542 assert(RegInfo->getVRegDef(Reg) && 543 "Machine instr not mapped for this vreg?!"); 544 545 // If the loop contains the definition of an operand, then the instruction 546 // isn't loop invariant. 547 if (CurLoop->contains(RegInfo->getVRegDef(Reg))) 548 return false; 549 } 550 551 // If we got this far, the instruction is loop invariant! 552 return true; 553} 554 555 556/// HasPHIUses - Return true if the specified register has any PHI use. 557static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) { 558 for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg), 559 UE = RegInfo->use_end(); UI != UE; ++UI) { 560 MachineInstr *UseMI = &*UI; 561 if (UseMI->isPHI()) 562 return true; 563 } 564 return false; 565} 566 567/// isLoadFromConstantMemory - Return true if the given instruction is a 568/// load from constant memory. Machine LICM will hoist these even if they are 569/// not re-materializable. 570bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) { 571 if (!MI->getDesc().mayLoad()) return false; 572 if (!MI->hasOneMemOperand()) return false; 573 MachineMemOperand *MMO = *MI->memoperands_begin(); 574 if (MMO->isVolatile()) return false; 575 if (!MMO->getValue()) return false; 576 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue()); 577 if (PSV) { 578 MachineFunction &MF = *MI->getParent()->getParent(); 579 return PSV->isConstant(MF.getFrameInfo()); 580 } else { 581 return AA->pointsToConstantMemory(MMO->getValue()); 582 } 583} 584 585/// IsProfitableToHoist - Return true if it is potentially profitable to hoist 586/// the given loop invariant. 587bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) { 588 if (MI.isImplicitDef()) 589 return false; 590 591 // FIXME: For now, only hoist re-materilizable instructions. LICM will 592 // increase register pressure. We want to make sure it doesn't increase 593 // spilling. 594 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting 595 // these tend to help performance in low register pressure situation. The 596 // trade off is it may cause spill in high pressure situation. It will end up 597 // adding a store in the loop preheader. But the reload is no more expensive. 598 // The side benefit is these loads are frequently CSE'ed. 599 if (!TII->isTriviallyReMaterializable(&MI, AA)) { 600 if (!isLoadFromConstantMemory(&MI)) 601 return false; 602 } 603 604 // If result(s) of this instruction is used by PHIs, then don't hoist it. 605 // The presence of joins makes it difficult for current register allocator 606 // implementation to perform remat. 607 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 608 const MachineOperand &MO = MI.getOperand(i); 609 if (!MO.isReg() || !MO.isDef()) 610 continue; 611 if (HasPHIUses(MO.getReg(), RegInfo)) 612 return false; 613 } 614 615 return true; 616} 617 618MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) { 619 // If not, we may be able to unfold a load and hoist that. 620 // First test whether the instruction is loading from an amenable 621 // memory location. 622 if (!isLoadFromConstantMemory(MI)) 623 return 0; 624 625 // Next determine the register class for a temporary register. 626 unsigned LoadRegIndex; 627 unsigned NewOpc = 628 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(), 629 /*UnfoldLoad=*/true, 630 /*UnfoldStore=*/false, 631 &LoadRegIndex); 632 if (NewOpc == 0) return 0; 633 const TargetInstrDesc &TID = TII->get(NewOpc); 634 if (TID.getNumDefs() != 1) return 0; 635 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI); 636 // Ok, we're unfolding. Create a temporary register and do the unfold. 637 unsigned Reg = RegInfo->createVirtualRegister(RC); 638 639 MachineFunction &MF = *MI->getParent()->getParent(); 640 SmallVector<MachineInstr *, 2> NewMIs; 641 bool Success = 642 TII->unfoldMemoryOperand(MF, MI, Reg, 643 /*UnfoldLoad=*/true, /*UnfoldStore=*/false, 644 NewMIs); 645 (void)Success; 646 assert(Success && 647 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold " 648 "succeeded!"); 649 assert(NewMIs.size() == 2 && 650 "Unfolded a load into multiple instructions!"); 651 MachineBasicBlock *MBB = MI->getParent(); 652 MBB->insert(MI, NewMIs[0]); 653 MBB->insert(MI, NewMIs[1]); 654 // If unfolding produced a load that wasn't loop-invariant or profitable to 655 // hoist, discard the new instructions and bail. 656 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { 657 NewMIs[0]->eraseFromParent(); 658 NewMIs[1]->eraseFromParent(); 659 return 0; 660 } 661 // Otherwise we successfully unfolded a load that we can hoist. 662 MI->eraseFromParent(); 663 return NewMIs[0]; 664} 665 666void MachineLICM::InitCSEMap(MachineBasicBlock *BB) { 667 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) { 668 const MachineInstr *MI = &*I; 669 // FIXME: For now, only hoist re-materilizable instructions. LICM will 670 // increase register pressure. We want to make sure it doesn't increase 671 // spilling. 672 if (TII->isTriviallyReMaterializable(MI, AA)) { 673 unsigned Opcode = MI->getOpcode(); 674 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator 675 CI = CSEMap.find(Opcode); 676 if (CI != CSEMap.end()) 677 CI->second.push_back(MI); 678 else { 679 std::vector<const MachineInstr*> CSEMIs; 680 CSEMIs.push_back(MI); 681 CSEMap.insert(std::make_pair(Opcode, CSEMIs)); 682 } 683 } 684 } 685} 686 687const MachineInstr* 688MachineLICM::LookForDuplicate(const MachineInstr *MI, 689 std::vector<const MachineInstr*> &PrevMIs) { 690 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) { 691 const MachineInstr *PrevMI = PrevMIs[i]; 692 if (TII->produceSameValue(MI, PrevMI)) 693 return PrevMI; 694 } 695 return 0; 696} 697 698bool MachineLICM::EliminateCSE(MachineInstr *MI, 699 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) { 700 if (CI == CSEMap.end()) 701 return false; 702 703 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) { 704 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup); 705 706 // Replace virtual registers defined by MI by their counterparts defined 707 // by Dup. 708 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 709 const MachineOperand &MO = MI->getOperand(i); 710 711 // Physical registers may not differ here. 712 assert((!MO.isReg() || MO.getReg() == 0 || 713 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 714 MO.getReg() == Dup->getOperand(i).getReg()) && 715 "Instructions with different phys regs are not identical!"); 716 717 if (MO.isReg() && MO.isDef() && 718 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) 719 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg()); 720 } 721 MI->eraseFromParent(); 722 ++NumCSEed; 723 return true; 724 } 725 return false; 726} 727 728/// Hoist - When an instruction is found to use only loop invariant operands 729/// that are safe to hoist, this instruction is called to do the dirty work. 730/// 731void MachineLICM::Hoist(MachineInstr *MI) { 732 // First check whether we should hoist this instruction. 733 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) { 734 // If not, try unfolding a hoistable load. 735 MI = ExtractHoistableLoad(MI); 736 if (!MI) return; 737 } 738 739 // Now move the instructions to the predecessor, inserting it before any 740 // terminator instructions. 741 DEBUG({ 742 dbgs() << "Hoisting " << *MI; 743 if (CurPreheader->getBasicBlock()) 744 dbgs() << " to MachineBasicBlock " 745 << CurPreheader->getName(); 746 if (MI->getParent()->getBasicBlock()) 747 dbgs() << " from MachineBasicBlock " 748 << MI->getParent()->getName(); 749 dbgs() << "\n"; 750 }); 751 752 // If this is the first instruction being hoisted to the preheader, 753 // initialize the CSE map with potential common expressions. 754 InitCSEMap(CurPreheader); 755 756 // Look for opportunity to CSE the hoisted instruction. 757 unsigned Opcode = MI->getOpcode(); 758 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator 759 CI = CSEMap.find(Opcode); 760 if (!EliminateCSE(MI, CI)) { 761 // Otherwise, splice the instruction to the preheader. 762 CurPreheader->splice(CurPreheader->getFirstTerminator(),MI->getParent(),MI); 763 764 // Add to the CSE map. 765 if (CI != CSEMap.end()) 766 CI->second.push_back(MI); 767 else { 768 std::vector<const MachineInstr*> CSEMIs; 769 CSEMIs.push_back(MI); 770 CSEMap.insert(std::make_pair(Opcode, CSEMIs)); 771 } 772 } 773 774 ++NumHoisted; 775 Changed = true; 776} 777