MachineLICM.cpp revision 9571e5b43b0cd3370fe480bb6ffd766bcfde46ae
1//===-- MachineLICM.cpp - Machine Loop Invariant Code Motion Pass ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass performs loop invariant code motion on machine instructions. We 11// attempt to remove as much code from the body of a loop as possible. 12// 13// This pass does not attempt to throttle itself to limit register pressure. 14// The register allocation phases are expected to perform rematerialization 15// to recover when register pressure is high. 16// 17// This pass is not intended to be a replacement or a complete alternative 18// for the LLVM-IR-level LICM pass. It is only designed to hoist simple 19// constructs that are not exposed before lowering and instruction selection. 20// 21//===----------------------------------------------------------------------===// 22 23#define DEBUG_TYPE "machine-licm" 24#include "llvm/CodeGen/Passes.h" 25#include "llvm/CodeGen/MachineDominators.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineLoopInfo.h" 28#include "llvm/CodeGen/MachineMemOperand.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/PseudoSourceValue.h" 31#include "llvm/Target/TargetRegisterInfo.h" 32#include "llvm/Target/TargetInstrInfo.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Analysis/AliasAnalysis.h" 35#include "llvm/ADT/DenseMap.h" 36#include "llvm/ADT/SmallSet.h" 37#include "llvm/ADT/Statistic.h" 38#include "llvm/Support/Debug.h" 39#include "llvm/Support/raw_ostream.h" 40 41using namespace llvm; 42 43STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops"); 44STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed"); 45STATISTIC(NumPostRAHoisted, 46 "Number of machine instructions hoisted out of loops post regalloc"); 47 48namespace { 49 class MachineLICM : public MachineFunctionPass { 50 bool PreRegAlloc; 51 52 const TargetMachine *TM; 53 const TargetInstrInfo *TII; 54 const TargetRegisterInfo *TRI; 55 const MachineFrameInfo *MFI; 56 MachineRegisterInfo *RegInfo; 57 58 // Various analyses that we use... 59 AliasAnalysis *AA; // Alias analysis info. 60 MachineLoopInfo *MLI; // Current MachineLoopInfo 61 MachineDominatorTree *DT; // Machine dominator tree for the cur loop 62 63 // State that is updated as we process loops 64 bool Changed; // True if a loop is changed. 65 bool FirstInLoop; // True if it's the first LICM in the loop. 66 MachineLoop *CurLoop; // The current loop we are working on. 67 MachineBasicBlock *CurPreheader; // The preheader for CurLoop. 68 69 BitVector AllocatableSet; 70 71 // For each opcode, keep a list of potentail CSE instructions. 72 DenseMap<unsigned, std::vector<const MachineInstr*> > CSEMap; 73 74 public: 75 static char ID; // Pass identification, replacement for typeid 76 MachineLICM() : 77 MachineFunctionPass(&ID), PreRegAlloc(true) {} 78 79 explicit MachineLICM(bool PreRA) : 80 MachineFunctionPass(&ID), PreRegAlloc(PreRA) {} 81 82 virtual bool runOnMachineFunction(MachineFunction &MF); 83 84 const char *getPassName() const { return "Machine Instruction LICM"; } 85 86 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 87 AU.setPreservesCFG(); 88 AU.addRequired<MachineLoopInfo>(); 89 AU.addRequired<MachineDominatorTree>(); 90 AU.addRequired<AliasAnalysis>(); 91 AU.addPreserved<MachineLoopInfo>(); 92 AU.addPreserved<MachineDominatorTree>(); 93 MachineFunctionPass::getAnalysisUsage(AU); 94 } 95 96 virtual void releaseMemory() { 97 CSEMap.clear(); 98 } 99 100 private: 101 /// CandidateInfo - Keep track of information about hoisting candidates. 102 struct CandidateInfo { 103 MachineInstr *MI; 104 unsigned Def; 105 int FI; 106 CandidateInfo(MachineInstr *mi, unsigned def, int fi) 107 : MI(mi), Def(def), FI(fi) {} 108 }; 109 110 /// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop 111 /// invariants out to the preheader. 112 void HoistRegionPostRA(); 113 114 /// HoistPostRA - When an instruction is found to only use loop invariant 115 /// operands that is safe to hoist, this instruction is called to do the 116 /// dirty work. 117 void HoistPostRA(MachineInstr *MI, unsigned Def); 118 119 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also 120 /// gather register def and frame object update information. 121 void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs, 122 SmallSet<int, 32> &StoredFIs, 123 SmallVector<CandidateInfo, 32> &Candidates); 124 125 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the 126 /// current loop. 127 void AddToLiveIns(unsigned Reg); 128 129 /// IsLICMCandidate - Returns true if the instruction may be a suitable 130 /// candidate for LICM. e.g. If the instruction is a call, then it's obviously 131 /// not safe to hoist it. 132 bool IsLICMCandidate(MachineInstr &I); 133 134 /// IsLoopInvariantInst - Returns true if the instruction is loop 135 /// invariant. I.e., all virtual register operands are defined outside of 136 /// the loop, physical registers aren't accessed (explicitly or implicitly), 137 /// and the instruction is hoistable. 138 /// 139 bool IsLoopInvariantInst(MachineInstr &I); 140 141 /// IsProfitableToHoist - Return true if it is potentially profitable to 142 /// hoist the given loop invariant. 143 bool IsProfitableToHoist(MachineInstr &MI); 144 145 /// HoistRegion - Walk the specified region of the CFG (defined by all 146 /// blocks dominated by the specified block, and that are in the current 147 /// loop) in depth first order w.r.t the DominatorTree. This allows us to 148 /// visit definitions before uses, allowing us to hoist a loop body in one 149 /// pass without iteration. 150 /// 151 void HoistRegion(MachineDomTreeNode *N); 152 153 /// isLoadFromConstantMemory - Return true if the given instruction is a 154 /// load from constant memory. 155 bool isLoadFromConstantMemory(MachineInstr *MI); 156 157 /// ExtractHoistableLoad - Unfold a load from the given machineinstr if 158 /// the load itself could be hoisted. Return the unfolded and hoistable 159 /// load, or null if the load couldn't be unfolded or if it wouldn't 160 /// be hoistable. 161 MachineInstr *ExtractHoistableLoad(MachineInstr *MI); 162 163 /// LookForDuplicate - Find an instruction amount PrevMIs that is a 164 /// duplicate of MI. Return this instruction if it's found. 165 const MachineInstr *LookForDuplicate(const MachineInstr *MI, 166 std::vector<const MachineInstr*> &PrevMIs); 167 168 /// EliminateCSE - Given a LICM'ed instruction, look for an instruction on 169 /// the preheader that compute the same value. If it's found, do a RAU on 170 /// with the definition of the existing instruction rather than hoisting 171 /// the instruction to the preheader. 172 bool EliminateCSE(MachineInstr *MI, 173 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI); 174 175 /// Hoist - When an instruction is found to only use loop invariant operands 176 /// that is safe to hoist, this instruction is called to do the dirty work. 177 /// 178 void Hoist(MachineInstr *MI); 179 180 /// InitCSEMap - Initialize the CSE map with instructions that are in the 181 /// current loop preheader that may become duplicates of instructions that 182 /// are hoisted out of the loop. 183 void InitCSEMap(MachineBasicBlock *BB); 184 185 /// getCurPreheader - Get the preheader for the current loop, splitting 186 /// a critical edge if needed. 187 MachineBasicBlock *getCurPreheader(); 188 }; 189} // end anonymous namespace 190 191char MachineLICM::ID = 0; 192static RegisterPass<MachineLICM> 193X("machinelicm", "Machine Loop Invariant Code Motion"); 194 195FunctionPass *llvm::createMachineLICMPass(bool PreRegAlloc) { 196 return new MachineLICM(PreRegAlloc); 197} 198 199/// LoopIsOuterMostWithPredecessor - Test if the given loop is the outer-most 200/// loop that has a unique predecessor. 201static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) { 202 // Check whether this loop even has a unique predecessor. 203 if (!CurLoop->getLoopPredecessor()) 204 return false; 205 // Ok, now check to see if any of its outer loops do. 206 for (MachineLoop *L = CurLoop->getParentLoop(); L; L = L->getParentLoop()) 207 if (L->getLoopPredecessor()) 208 return false; 209 // None of them did, so this is the outermost with a unique predecessor. 210 return true; 211} 212 213bool MachineLICM::runOnMachineFunction(MachineFunction &MF) { 214 if (PreRegAlloc) 215 DEBUG(dbgs() << "******** Pre-regalloc Machine LICM ********\n"); 216 else 217 DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n"); 218 219 Changed = FirstInLoop = false; 220 TM = &MF.getTarget(); 221 TII = TM->getInstrInfo(); 222 TRI = TM->getRegisterInfo(); 223 MFI = MF.getFrameInfo(); 224 RegInfo = &MF.getRegInfo(); 225 AllocatableSet = TRI->getAllocatableSet(MF); 226 227 // Get our Loop information... 228 MLI = &getAnalysis<MachineLoopInfo>(); 229 DT = &getAnalysis<MachineDominatorTree>(); 230 AA = &getAnalysis<AliasAnalysis>(); 231 232 SmallVector<MachineLoop *, 8> Worklist(MLI->begin(), MLI->end()); 233 while (!Worklist.empty()) { 234 CurLoop = Worklist.pop_back_val(); 235 CurPreheader = 0; 236 237 // If this is done before regalloc, only visit outer-most preheader-sporting 238 // loops. 239 if (PreRegAlloc && !LoopIsOuterMostWithPredecessor(CurLoop)) { 240 Worklist.append(CurLoop->begin(), CurLoop->end()); 241 continue; 242 } 243 244 if (!PreRegAlloc) 245 HoistRegionPostRA(); 246 else { 247 // CSEMap is initialized for loop header when the first instruction is 248 // being hoisted. 249 MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader()); 250 FirstInLoop = true; 251 HoistRegion(N); 252 CSEMap.clear(); 253 } 254 } 255 256 return Changed; 257} 258 259/// InstructionStoresToFI - Return true if instruction stores to the 260/// specified frame. 261static bool InstructionStoresToFI(const MachineInstr *MI, int FI) { 262 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 263 oe = MI->memoperands_end(); o != oe; ++o) { 264 if (!(*o)->isStore() || !(*o)->getValue()) 265 continue; 266 if (const FixedStackPseudoSourceValue *Value = 267 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 268 if (Value->getFrameIndex() == FI) 269 return true; 270 } 271 } 272 return false; 273} 274 275/// ProcessMI - Examine the instruction for potentai LICM candidate. Also 276/// gather register def and frame object update information. 277void MachineLICM::ProcessMI(MachineInstr *MI, 278 unsigned *PhysRegDefs, 279 SmallSet<int, 32> &StoredFIs, 280 SmallVector<CandidateInfo, 32> &Candidates) { 281 bool RuledOut = false; 282 bool HasNonInvariantUse = false; 283 unsigned Def = 0; 284 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 285 const MachineOperand &MO = MI->getOperand(i); 286 if (MO.isFI()) { 287 // Remember if the instruction stores to the frame index. 288 int FI = MO.getIndex(); 289 if (!StoredFIs.count(FI) && 290 MFI->isSpillSlotObjectIndex(FI) && 291 InstructionStoresToFI(MI, FI)) 292 StoredFIs.insert(FI); 293 HasNonInvariantUse = true; 294 continue; 295 } 296 297 if (!MO.isReg()) 298 continue; 299 unsigned Reg = MO.getReg(); 300 if (!Reg) 301 continue; 302 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 303 "Not expecting virtual register!"); 304 305 if (!MO.isDef()) { 306 if (Reg && PhysRegDefs[Reg]) 307 // If it's using a non-loop-invariant register, then it's obviously not 308 // safe to hoist. 309 HasNonInvariantUse = true; 310 continue; 311 } 312 313 if (MO.isImplicit()) { 314 ++PhysRegDefs[Reg]; 315 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 316 ++PhysRegDefs[*AS]; 317 if (!MO.isDead()) 318 // Non-dead implicit def? This cannot be hoisted. 319 RuledOut = true; 320 // No need to check if a dead implicit def is also defined by 321 // another instruction. 322 continue; 323 } 324 325 // FIXME: For now, avoid instructions with multiple defs, unless 326 // it's a dead implicit def. 327 if (Def) 328 RuledOut = true; 329 else 330 Def = Reg; 331 332 // If we have already seen another instruction that defines the same 333 // register, then this is not safe. 334 if (++PhysRegDefs[Reg] > 1) 335 // MI defined register is seen defined by another instruction in 336 // the loop, it cannot be a LICM candidate. 337 RuledOut = true; 338 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 339 if (++PhysRegDefs[*AS] > 1) 340 RuledOut = true; 341 } 342 343 // Only consider reloads for now and remats which do not have register 344 // operands. FIXME: Consider unfold load folding instructions. 345 if (Def && !RuledOut) { 346 int FI = INT_MIN; 347 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) || 348 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI))) 349 Candidates.push_back(CandidateInfo(MI, Def, FI)); 350 } 351} 352 353/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop 354/// invariants out to the preheader. 355void MachineLICM::HoistRegionPostRA() { 356 unsigned NumRegs = TRI->getNumRegs(); 357 unsigned *PhysRegDefs = new unsigned[NumRegs]; 358 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0); 359 360 SmallVector<CandidateInfo, 32> Candidates; 361 SmallSet<int, 32> StoredFIs; 362 363 // Walk the entire region, count number of defs for each register, and 364 // collect potential LICM candidates. 365 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks(); 366 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { 367 MachineBasicBlock *BB = Blocks[i]; 368 // Conservatively treat live-in's as an external def. 369 // FIXME: That means a reload that're reused in successor block(s) will not 370 // be LICM'ed. 371 for (MachineBasicBlock::livein_iterator I = BB->livein_begin(), 372 E = BB->livein_end(); I != E; ++I) { 373 unsigned Reg = *I; 374 ++PhysRegDefs[Reg]; 375 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 376 ++PhysRegDefs[*AS]; 377 } 378 379 for (MachineBasicBlock::iterator 380 MII = BB->begin(), E = BB->end(); MII != E; ++MII) { 381 MachineInstr *MI = &*MII; 382 ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates); 383 } 384 } 385 386 // Now evaluate whether the potential candidates qualify. 387 // 1. Check if the candidate defined register is defined by another 388 // instruction in the loop. 389 // 2. If the candidate is a load from stack slot (always true for now), 390 // check if the slot is stored anywhere in the loop. 391 for (unsigned i = 0, e = Candidates.size(); i != e; ++i) { 392 if (Candidates[i].FI != INT_MIN && 393 StoredFIs.count(Candidates[i].FI)) 394 continue; 395 396 if (PhysRegDefs[Candidates[i].Def] == 1) { 397 bool Safe = true; 398 MachineInstr *MI = Candidates[i].MI; 399 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) { 400 const MachineOperand &MO = MI->getOperand(j); 401 if (!MO.isReg() || MO.isDef() || !MO.getReg()) 402 continue; 403 if (PhysRegDefs[MO.getReg()]) { 404 // If it's using a non-loop-invariant register, then it's obviously 405 // not safe to hoist. 406 Safe = false; 407 break; 408 } 409 } 410 if (Safe) 411 HoistPostRA(MI, Candidates[i].Def); 412 } 413 } 414 415 delete[] PhysRegDefs; 416} 417 418/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the current 419/// loop, and make sure it is not killed by any instructions in the loop. 420void MachineLICM::AddToLiveIns(unsigned Reg) { 421 const std::vector<MachineBasicBlock*> Blocks = CurLoop->getBlocks(); 422 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { 423 MachineBasicBlock *BB = Blocks[i]; 424 if (!BB->isLiveIn(Reg)) 425 BB->addLiveIn(Reg); 426 for (MachineBasicBlock::iterator 427 MII = BB->begin(), E = BB->end(); MII != E; ++MII) { 428 MachineInstr *MI = &*MII; 429 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 430 MachineOperand &MO = MI->getOperand(i); 431 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; 432 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg())) 433 MO.setIsKill(false); 434 } 435 } 436 } 437} 438 439/// HoistPostRA - When an instruction is found to only use loop invariant 440/// operands that is safe to hoist, this instruction is called to do the 441/// dirty work. 442void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) { 443 MachineBasicBlock *Preheader = getCurPreheader(); 444 if (!Preheader) return; 445 446 // Now move the instructions to the predecessor, inserting it before any 447 // terminator instructions. 448 DEBUG({ 449 dbgs() << "Hoisting " << *MI; 450 if (Preheader->getBasicBlock()) 451 dbgs() << " to MachineBasicBlock " 452 << Preheader->getName(); 453 if (MI->getParent()->getBasicBlock()) 454 dbgs() << " from MachineBasicBlock " 455 << MI->getParent()->getName(); 456 dbgs() << "\n"; 457 }); 458 459 // Splice the instruction to the preheader. 460 MachineBasicBlock *MBB = MI->getParent(); 461 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI); 462 463 // Add register to livein list to all the BBs in the current loop since a 464 // loop invariant must be kept live throughout the whole loop. This is 465 // important to ensure later passes do not scavenge the def register. 466 AddToLiveIns(Def); 467 468 ++NumPostRAHoisted; 469 Changed = true; 470} 471 472/// HoistRegion - Walk the specified region of the CFG (defined by all blocks 473/// dominated by the specified block, and that are in the current loop) in depth 474/// first order w.r.t the DominatorTree. This allows us to visit definitions 475/// before uses, allowing us to hoist a loop body in one pass without iteration. 476/// 477void MachineLICM::HoistRegion(MachineDomTreeNode *N) { 478 assert(N != 0 && "Null dominator tree node?"); 479 MachineBasicBlock *BB = N->getBlock(); 480 481 // If this subregion is not in the top level loop at all, exit. 482 if (!CurLoop->contains(BB)) return; 483 484 for (MachineBasicBlock::iterator 485 MII = BB->begin(), E = BB->end(); MII != E; ) { 486 MachineBasicBlock::iterator NextMII = MII; ++NextMII; 487 Hoist(&*MII); 488 MII = NextMII; 489 } 490 491 const std::vector<MachineDomTreeNode*> &Children = N->getChildren(); 492 for (unsigned I = 0, E = Children.size(); I != E; ++I) 493 HoistRegion(Children[I]); 494} 495 496/// IsLICMCandidate - Returns true if the instruction may be a suitable 497/// candidate for LICM. e.g. If the instruction is a call, then it's obviously 498/// not safe to hoist it. 499bool MachineLICM::IsLICMCandidate(MachineInstr &I) { 500 if (I.isImplicitDef()) 501 return false; 502 503 const TargetInstrDesc &TID = I.getDesc(); 504 505 // Ignore stuff that we obviously can't hoist. 506 if (TID.mayStore() || TID.isCall() || TID.isTerminator() || 507 TID.hasUnmodeledSideEffects()) 508 return false; 509 510 if (TID.mayLoad()) { 511 // Okay, this instruction does a load. As a refinement, we allow the target 512 // to decide whether the loaded value is actually a constant. If so, we can 513 // actually use it as a load. 514 if (!I.isInvariantLoad(AA)) 515 // FIXME: we should be able to hoist loads with no other side effects if 516 // there are no other instructions which can change memory in this loop. 517 // This is a trivial form of alias analysis. 518 return false; 519 } 520 return true; 521} 522 523/// IsLoopInvariantInst - Returns true if the instruction is loop 524/// invariant. I.e., all virtual register operands are defined outside of the 525/// loop, physical registers aren't accessed explicitly, and there are no side 526/// effects that aren't captured by the operands or other flags. 527/// 528bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) { 529 if (!IsLICMCandidate(I)) 530 return false; 531 532 // The instruction is loop invariant if all of its operands are. 533 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { 534 const MachineOperand &MO = I.getOperand(i); 535 536 if (!MO.isReg()) 537 continue; 538 539 unsigned Reg = MO.getReg(); 540 if (Reg == 0) continue; 541 542 // Don't hoist an instruction that uses or defines a physical register. 543 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 544 if (MO.isUse()) { 545 // If the physreg has no defs anywhere, it's just an ambient register 546 // and we can freely move its uses. Alternatively, if it's allocatable, 547 // it could get allocated to something with a def during allocation. 548 if (!RegInfo->def_empty(Reg)) 549 return false; 550 if (AllocatableSet.test(Reg)) 551 return false; 552 // Check for a def among the register's aliases too. 553 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 554 unsigned AliasReg = *Alias; 555 if (!RegInfo->def_empty(AliasReg)) 556 return false; 557 if (AllocatableSet.test(AliasReg)) 558 return false; 559 } 560 // Otherwise it's safe to move. 561 continue; 562 } else if (!MO.isDead()) { 563 // A def that isn't dead. We can't move it. 564 return false; 565 } else if (CurLoop->getHeader()->isLiveIn(Reg)) { 566 // If the reg is live into the loop, we can't hoist an instruction 567 // which would clobber it. 568 return false; 569 } 570 } 571 572 if (!MO.isUse()) 573 continue; 574 575 assert(RegInfo->getVRegDef(Reg) && 576 "Machine instr not mapped for this vreg?!"); 577 578 // If the loop contains the definition of an operand, then the instruction 579 // isn't loop invariant. 580 if (CurLoop->contains(RegInfo->getVRegDef(Reg))) 581 return false; 582 } 583 584 // If we got this far, the instruction is loop invariant! 585 return true; 586} 587 588 589/// HasPHIUses - Return true if the specified register has any PHI use. 590static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) { 591 for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg), 592 UE = RegInfo->use_end(); UI != UE; ++UI) { 593 MachineInstr *UseMI = &*UI; 594 if (UseMI->isPHI()) 595 return true; 596 } 597 return false; 598} 599 600/// isLoadFromConstantMemory - Return true if the given instruction is a 601/// load from constant memory. Machine LICM will hoist these even if they are 602/// not re-materializable. 603bool MachineLICM::isLoadFromConstantMemory(MachineInstr *MI) { 604 if (!MI->getDesc().mayLoad()) return false; 605 if (!MI->hasOneMemOperand()) return false; 606 MachineMemOperand *MMO = *MI->memoperands_begin(); 607 if (MMO->isVolatile()) return false; 608 if (!MMO->getValue()) return false; 609 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(MMO->getValue()); 610 if (PSV) { 611 MachineFunction &MF = *MI->getParent()->getParent(); 612 return PSV->isConstant(MF.getFrameInfo()); 613 } else { 614 return AA->pointsToConstantMemory(MMO->getValue()); 615 } 616} 617 618/// IsProfitableToHoist - Return true if it is potentially profitable to hoist 619/// the given loop invariant. 620bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) { 621 // FIXME: For now, only hoist re-materilizable instructions. LICM will 622 // increase register pressure. We want to make sure it doesn't increase 623 // spilling. 624 // Also hoist loads from constant memory, e.g. load from stubs, GOT. Hoisting 625 // these tend to help performance in low register pressure situation. The 626 // trade off is it may cause spill in high pressure situation. It will end up 627 // adding a store in the loop preheader. But the reload is no more expensive. 628 // The side benefit is these loads are frequently CSE'ed. 629 if (!TII->isTriviallyReMaterializable(&MI, AA)) { 630 if (!isLoadFromConstantMemory(&MI)) 631 return false; 632 } 633 634 // If result(s) of this instruction is used by PHIs, then don't hoist it. 635 // The presence of joins makes it difficult for current register allocator 636 // implementation to perform remat. 637 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 638 const MachineOperand &MO = MI.getOperand(i); 639 if (!MO.isReg() || !MO.isDef()) 640 continue; 641 if (HasPHIUses(MO.getReg(), RegInfo)) 642 return false; 643 } 644 645 return true; 646} 647 648MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) { 649 // If not, we may be able to unfold a load and hoist that. 650 // First test whether the instruction is loading from an amenable 651 // memory location. 652 if (!isLoadFromConstantMemory(MI)) 653 return 0; 654 655 // Next determine the register class for a temporary register. 656 unsigned LoadRegIndex; 657 unsigned NewOpc = 658 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(), 659 /*UnfoldLoad=*/true, 660 /*UnfoldStore=*/false, 661 &LoadRegIndex); 662 if (NewOpc == 0) return 0; 663 const TargetInstrDesc &TID = TII->get(NewOpc); 664 if (TID.getNumDefs() != 1) return 0; 665 const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI); 666 // Ok, we're unfolding. Create a temporary register and do the unfold. 667 unsigned Reg = RegInfo->createVirtualRegister(RC); 668 669 MachineFunction &MF = *MI->getParent()->getParent(); 670 SmallVector<MachineInstr *, 2> NewMIs; 671 bool Success = 672 TII->unfoldMemoryOperand(MF, MI, Reg, 673 /*UnfoldLoad=*/true, /*UnfoldStore=*/false, 674 NewMIs); 675 (void)Success; 676 assert(Success && 677 "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold " 678 "succeeded!"); 679 assert(NewMIs.size() == 2 && 680 "Unfolded a load into multiple instructions!"); 681 MachineBasicBlock *MBB = MI->getParent(); 682 MBB->insert(MI, NewMIs[0]); 683 MBB->insert(MI, NewMIs[1]); 684 // If unfolding produced a load that wasn't loop-invariant or profitable to 685 // hoist, discard the new instructions and bail. 686 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { 687 NewMIs[0]->eraseFromParent(); 688 NewMIs[1]->eraseFromParent(); 689 return 0; 690 } 691 // Otherwise we successfully unfolded a load that we can hoist. 692 MI->eraseFromParent(); 693 return NewMIs[0]; 694} 695 696void MachineLICM::InitCSEMap(MachineBasicBlock *BB) { 697 for (MachineBasicBlock::iterator I = BB->begin(),E = BB->end(); I != E; ++I) { 698 const MachineInstr *MI = &*I; 699 // FIXME: For now, only hoist re-materilizable instructions. LICM will 700 // increase register pressure. We want to make sure it doesn't increase 701 // spilling. 702 if (TII->isTriviallyReMaterializable(MI, AA)) { 703 unsigned Opcode = MI->getOpcode(); 704 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator 705 CI = CSEMap.find(Opcode); 706 if (CI != CSEMap.end()) 707 CI->second.push_back(MI); 708 else { 709 std::vector<const MachineInstr*> CSEMIs; 710 CSEMIs.push_back(MI); 711 CSEMap.insert(std::make_pair(Opcode, CSEMIs)); 712 } 713 } 714 } 715} 716 717const MachineInstr* 718MachineLICM::LookForDuplicate(const MachineInstr *MI, 719 std::vector<const MachineInstr*> &PrevMIs) { 720 for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) { 721 const MachineInstr *PrevMI = PrevMIs[i]; 722 if (TII->produceSameValue(MI, PrevMI)) 723 return PrevMI; 724 } 725 return 0; 726} 727 728bool MachineLICM::EliminateCSE(MachineInstr *MI, 729 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator &CI) { 730 if (CI == CSEMap.end()) 731 return false; 732 733 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) { 734 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup); 735 736 // Replace virtual registers defined by MI by their counterparts defined 737 // by Dup. 738 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 739 const MachineOperand &MO = MI->getOperand(i); 740 741 // Physical registers may not differ here. 742 assert((!MO.isReg() || MO.getReg() == 0 || 743 !TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 744 MO.getReg() == Dup->getOperand(i).getReg()) && 745 "Instructions with different phys regs are not identical!"); 746 747 if (MO.isReg() && MO.isDef() && 748 !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { 749 RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg()); 750 RegInfo->clearKillFlags(Dup->getOperand(i).getReg()); 751 } 752 } 753 MI->eraseFromParent(); 754 ++NumCSEed; 755 return true; 756 } 757 return false; 758} 759 760/// Hoist - When an instruction is found to use only loop invariant operands 761/// that are safe to hoist, this instruction is called to do the dirty work. 762/// 763void MachineLICM::Hoist(MachineInstr *MI) { 764 MachineBasicBlock *Preheader = getCurPreheader(); 765 if (!Preheader) return; 766 767 // First check whether we should hoist this instruction. 768 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) { 769 // If not, try unfolding a hoistable load. 770 MI = ExtractHoistableLoad(MI); 771 if (!MI) return; 772 } 773 774 // Now move the instructions to the predecessor, inserting it before any 775 // terminator instructions. 776 DEBUG({ 777 dbgs() << "Hoisting " << *MI; 778 if (Preheader->getBasicBlock()) 779 dbgs() << " to MachineBasicBlock " 780 << Preheader->getName(); 781 if (MI->getParent()->getBasicBlock()) 782 dbgs() << " from MachineBasicBlock " 783 << MI->getParent()->getName(); 784 dbgs() << "\n"; 785 }); 786 787 // If this is the first instruction being hoisted to the preheader, 788 // initialize the CSE map with potential common expressions. 789 if (FirstInLoop) { 790 InitCSEMap(Preheader); 791 FirstInLoop = false; 792 } 793 794 // Look for opportunity to CSE the hoisted instruction. 795 unsigned Opcode = MI->getOpcode(); 796 DenseMap<unsigned, std::vector<const MachineInstr*> >::iterator 797 CI = CSEMap.find(Opcode); 798 if (!EliminateCSE(MI, CI)) { 799 // Otherwise, splice the instruction to the preheader. 800 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI); 801 802 // Clear the kill flags of any register this instruction defines, 803 // since they may need to be live throughout the entire loop 804 // rather than just live for part of it. 805 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 806 MachineOperand &MO = MI->getOperand(i); 807 if (MO.isReg() && MO.isDef() && !MO.isDead()) 808 RegInfo->clearKillFlags(MO.getReg()); 809 } 810 811 // Add to the CSE map. 812 if (CI != CSEMap.end()) 813 CI->second.push_back(MI); 814 else { 815 std::vector<const MachineInstr*> CSEMIs; 816 CSEMIs.push_back(MI); 817 CSEMap.insert(std::make_pair(Opcode, CSEMIs)); 818 } 819 } 820 821 ++NumHoisted; 822 Changed = true; 823} 824 825MachineBasicBlock *MachineLICM::getCurPreheader() { 826 // Determine the block to which to hoist instructions. If we can't find a 827 // suitable loop predecessor, we can't do any hoisting. 828 829 // If we've tried to get a preheader and failed, don't try again. 830 if (CurPreheader == reinterpret_cast<MachineBasicBlock *>(-1)) 831 return 0; 832 833 if (!CurPreheader) { 834 CurPreheader = CurLoop->getLoopPreheader(); 835 if (!CurPreheader) { 836 MachineBasicBlock *Pred = CurLoop->getLoopPredecessor(); 837 if (!Pred) { 838 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1); 839 return 0; 840 } 841 842 CurPreheader = Pred->SplitCriticalEdge(CurLoop->getHeader(), this); 843 if (!CurPreheader) { 844 CurPreheader = reinterpret_cast<MachineBasicBlock *>(-1); 845 return 0; 846 } 847 } 848 } 849 return CurPreheader; 850} 851