MachineRegisterInfo.cpp revision 03bafaf802579d0c659af6f2bc1ca539ac0704ca
162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//
384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//                     The LLVM Compiler Infrastructure
484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//
584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source
684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details.
784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//
884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===//
984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//
1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// Implementation of the MachineRegisterInfo class.
1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//
1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===//
1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner
1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h"
1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerusing namespace llvm;
1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner
176f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanMachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner  VRegInfo.reserve(256);
196f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman  UsedPhysRegs.resize(TRI.getNumRegs());
2062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner
2162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner  // Create the physreg use/def lists.
226f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman  PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
236f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman  memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
2462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner}
2562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner
2662ed6b9ade63bf01717ce5274fa11e93e873d245Chris LattnerMachineRegisterInfo::~MachineRegisterInfo() {
2762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#ifndef NDEBUG
2862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner    assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
3003bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman  for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
3103bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman    assert(!PhysRegUseDefLists[i] &&
3203bafaf802579d0c659af6f2bc1ca539ac0704caDan Gohman           "PhysRegUseDefLists has entries after all instructions are deleted");
3362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner#endif
3462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner  delete [] PhysRegUseDefLists;
3562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner}
3662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner
3762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// HandleVRegListReallocation - We just added a virtual register to the
3862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// VRegInfo info list and it reallocated.  Update the use/def lists info
3962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner/// pointers.
4062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnervoid MachineRegisterInfo::HandleVRegListReallocation() {
4162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner  // The back pointers for the vreg lists point into the previous vector.
4262ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner  // Update them to point to their correct slots.
4362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
4462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner    MachineOperand *List = VRegInfo[i].second;
4562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner    if (!List) continue;
4662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner    // Update the back-pointer to be accurate once more.
4762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner    List->Contents.Reg.Prev = &VRegInfo[i].second;
4862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner  }
4984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}
50a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner
51e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// replaceRegWith - Replace all instances of FromReg with ToReg in the
52e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
53e138b3dd1ff02d826233482831318708a166ed93Chris Lattner/// except that it also changes any definitions of the register as well.
54e138b3dd1ff02d826233482831318708a166ed93Chris Lattnervoid MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
55e138b3dd1ff02d826233482831318708a166ed93Chris Lattner  assert(FromReg != ToReg && "Cannot replace a reg with itself");
56e138b3dd1ff02d826233482831318708a166ed93Chris Lattner
57e138b3dd1ff02d826233482831318708a166ed93Chris Lattner  // TODO: This could be more efficient by bulk changing the operands.
58e138b3dd1ff02d826233482831318708a166ed93Chris Lattner  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
59e138b3dd1ff02d826233482831318708a166ed93Chris Lattner    MachineOperand &O = I.getOperand();
60e138b3dd1ff02d826233482831318708a166ed93Chris Lattner    ++I;
61e138b3dd1ff02d826233482831318708a166ed93Chris Lattner    O.setReg(ToReg);
62e138b3dd1ff02d826233482831318708a166ed93Chris Lattner  }
63e138b3dd1ff02d826233482831318708a166ed93Chris Lattner}
64e138b3dd1ff02d826233482831318708a166ed93Chris Lattner
65a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner
66a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// getVRegDef - Return the machine instr that defines the specified virtual
67a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// register or null if none is found.  This assumes that the code is in SSA
68a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner/// form, so there should only be one definition.
69a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris LattnerMachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
706f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman  assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
71a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner         "Invalid vreg!");
72a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner  for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
73a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner    // Since we are in SSA form, we can stop at the first definition.
74e138b3dd1ff02d826233482831318708a166ed93Chris Lattner    if (I.getOperand().isDef())
75e138b3dd1ff02d826233482831318708a166ed93Chris Lattner      return &*I;
76a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner  }
77a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner  return 0;
78a91a7d594ff1e1503731ca92f72e627bdfd18f3fChris Lattner}
791eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng
801eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng
811eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG
821eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Chengvoid MachineRegisterInfo::dumpUses(unsigned Reg) const {
831eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng  for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
841eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng    I.getOperand().getParent()->dump();
851eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng}
861eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif
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