MachineRegisterInfo.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
15d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 25d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner// 35d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner// The LLVM Compiler Infrastructure 45d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner// 55d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner// This file is distributed under the University of Illinois Open Source 65d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner// License. See LICENSE.TXT for details. 75d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner// 85d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner//===----------------------------------------------------------------------===// 95d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner// 1034c48ff1e3ad5cd2084ca40188754d45f423750bDavid 'Digit' Turner// Implementation of the MachineRegisterInfo class. 11e1e03df288d5a44bfbffbd86588395c7cbbc27dfDavid 'Digit' Turner// 125d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner//===----------------------------------------------------------------------===// 135d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 145d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#include "llvm/CodeGen/MachineRegisterInfo.h" 15aa8236dc1b1ea300ab18716db5b8fab42aca3ca7David 'Digit' Turner#include "llvm/CodeGen/MachineInstrBuilder.h" 165d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#include "llvm/Support/raw_os_ostream.h" 175d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#include "llvm/Target/TargetInstrInfo.h" 185d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#include "llvm/Target/TargetMachine.h" 195d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 205d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnerusing namespace llvm; 21bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turner 22bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turner// Pin the vtable to this file. 235d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnervoid MachineRegisterInfo::Delegate::anchor() {} 245d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 255d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' TurnerMachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM) 26aa8236dc1b1ea300ab18716db5b8fab42aca3ca7David 'Digit' Turner : TM(TM), TheDelegate(0), IsSSA(true), TracksLiveness(true) { 275d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner VRegInfo.reserve(256); 285d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner RegAllocHints.reserve(256); 295d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits()); 305d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs()); 315d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 325d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Create the physreg use/def lists. 335d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner PhysRegUseDefLists = 345d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner new MachineOperand*[getTargetRegisterInfo()->getNumRegs()]; 355d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner memset(PhysRegUseDefLists, 0, 36aa8236dc1b1ea300ab18716db5b8fab42aca3ca7David 'Digit' Turner sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs()); 375d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 385d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 395d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' TurnerMachineRegisterInfo::~MachineRegisterInfo() { 405d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner delete [] PhysRegUseDefLists; 415d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 425d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 435d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner/// setRegClass - Set the register class of the specified virtual register. 445d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner/// 455d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnervoid 465d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' TurnerMachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 47bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turner assert(RC && RC->isAllocatable() && "Invalid RC for virtual register"); 485d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner VRegInfo[Reg].first = RC; 495d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 505d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 515d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnerconst TargetRegisterClass * 525d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' TurnerMachineRegisterInfo::constrainRegClass(unsigned Reg, 535d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner const TargetRegisterClass *RC, 545d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner unsigned MinNumRegs) { 555d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner const TargetRegisterClass *OldRC = getRegClass(Reg); 565d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (OldRC == RC) 575d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return RC; 585d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner const TargetRegisterClass *NewRC = 595d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); 605d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (!NewRC || NewRC == OldRC) 615d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return NewRC; 625d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (NewRC->getNumRegs() < MinNumRegs) 635d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return 0; 645d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner setRegClass(Reg, NewRC); 655d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return NewRC; 665d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 675d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 685d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnerbool 695d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' TurnerMachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 705d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner const TargetInstrInfo *TII = TM.getInstrInfo(); 715d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner const TargetRegisterClass *OldRC = getRegClass(Reg); 725d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner const TargetRegisterClass *NewRC = 735d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC); 745d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 755d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Stop early if there is no room to grow. 765d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (NewRC == OldRC) 775d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return false; 785d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 795d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Accumulate constraints from all uses. 805d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner for (MachineOperand &MO : reg_nodbg_operands(Reg)) { 815d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Apply the effect of the given operand to NewRC. 825d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner MachineInstr *MI = MO.getParent(); 835d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner unsigned OpNo = &MO - &MI->getOperand(0); 845d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII, 85bcde1092aca184dbd7860078af020de7d1e4e22fDavid 'Digit' Turner getTargetRegisterInfo()); 865d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (!NewRC || NewRC == OldRC) 875d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return false; 885d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner } 895d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner setRegClass(Reg, NewRC); 905d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return true; 915d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 925d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 935d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner/// createVirtualRegister - Create and return a new virtual register in the 945d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner/// function with the specified register class. 955d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner/// 965d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnerunsigned 975d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' TurnerMachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 985d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner assert(RegClass && "Cannot create register without RegClass!"); 995d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner assert(RegClass->isAllocatable() && 1005d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner "Virtual register RegClass must be allocatable."); 1015d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 1025d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // New virtual register number. 1035d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 1045d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner VRegInfo.grow(Reg); 1055d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner VRegInfo[Reg].first = RegClass; 1065d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner RegAllocHints.grow(Reg); 1075d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (TheDelegate) 1085d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner TheDelegate->MRI_NoteNewVirtualRegister(Reg); 1095d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner return Reg; 1105d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 1115d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 1125d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 1135d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnervoid MachineRegisterInfo::clearVirtRegs() { 1145d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#ifndef NDEBUG 1155d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 1165d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 1175d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (!VRegInfo[Reg].second) 1185d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner continue; 1195d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner verifyUseList(Reg); 1205d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner llvm_unreachable("Remaining virtual register operands"); 1215d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner } 1225d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#endif 1235d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner VRegInfo.clear(); 1245d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 1255d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 1265d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnervoid MachineRegisterInfo::verifyUseList(unsigned Reg) const { 1275d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#ifndef NDEBUG 1285d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner bool Valid = true; 1295d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner for (MachineOperand &M : reg_operands(Reg)) { 1305d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner MachineOperand *MO = &M; 1315d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner MachineInstr *MI = MO->getParent(); 1325d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (!MI) { 1335d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner errs() << PrintReg(Reg, getTargetRegisterInfo()) 1345d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << " use list MachineOperand " << MO 1355d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << " has no parent instruction.\n"; 1365d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner Valid = false; 1375d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner } 1385d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner MachineOperand *MO0 = &MI->getOperand(0); 1395d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner unsigned NumOps = MI->getNumOperands(); 1405d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (!(MO >= MO0 && MO < MO0+NumOps)) { 1415d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner errs() << PrintReg(Reg, getTargetRegisterInfo()) 1425d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << " use list MachineOperand " << MO 1435d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << " doesn't belong to parent MI: " << *MI; 1445d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner Valid = false; 1455d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner } 1465d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (!MO->isReg()) { 1475d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner errs() << PrintReg(Reg, getTargetRegisterInfo()) 1485d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << " MachineOperand " << MO << ": " << *MO 1495d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << " is not a register\n"; 1505d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner Valid = false; 1515d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner } 1525d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (MO->getReg() != Reg) { 1535d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner errs() << PrintReg(Reg, getTargetRegisterInfo()) 1545d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << " use-list MachineOperand " << MO << ": " 1555d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner << *MO << " is the wrong register\n"; 1565d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner Valid = false; 1575d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner } 1585d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner } 1595d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner assert(Valid && "Invalid use list"); 1605d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#endif 1615d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 1625d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 1635d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnervoid MachineRegisterInfo::verifyUseLists() const { 1645d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#ifndef NDEBUG 1655d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 1665d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner verifyUseList(TargetRegisterInfo::index2VirtReg(i)); 1675d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i) 1685d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner verifyUseList(i); 1695d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner#endif 1705d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner} 1715d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 1725d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner/// Add MO to the linked list of operands for its register. 1735d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turnervoid MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 1745d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner assert(!MO->isOnRegUseList() && "Already on list"); 1755d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 1765d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner MachineOperand *const Head = HeadRef; 1775d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 1785d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Head points to the first list element. 1795d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Next is NULL on the last list element. 1805d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Prev pointers are circular, so Head->Prev == Last. 1815d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner 1825d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner // Head is NULL for an empty list. 1835d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner if (!Head) { 1845d8f37ad78fc66901af50c762029a501561f3b23David 'Digit' Turner MO->Contents.Reg.Prev = MO; 185 MO->Contents.Reg.Next = 0; 186 HeadRef = MO; 187 return; 188 } 189 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 190 191 // Insert MO between Last and Head in the circular Prev chain. 192 MachineOperand *Last = Head->Contents.Reg.Prev; 193 assert(Last && "Inconsistent use list"); 194 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 195 Head->Contents.Reg.Prev = MO; 196 MO->Contents.Reg.Prev = Last; 197 198 // Def operands always precede uses. This allows def_iterator to stop early. 199 // Insert def operands at the front, and use operands at the back. 200 if (MO->isDef()) { 201 // Insert def at the front. 202 MO->Contents.Reg.Next = Head; 203 HeadRef = MO; 204 } else { 205 // Insert use at the end. 206 MO->Contents.Reg.Next = 0; 207 Last->Contents.Reg.Next = MO; 208 } 209} 210 211/// Remove MO from its use-def list. 212void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 213 assert(MO->isOnRegUseList() && "Operand not on use list"); 214 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 215 MachineOperand *const Head = HeadRef; 216 assert(Head && "List already empty"); 217 218 // Unlink this from the doubly linked list of operands. 219 MachineOperand *Next = MO->Contents.Reg.Next; 220 MachineOperand *Prev = MO->Contents.Reg.Prev; 221 222 // Prev links are circular, next link is NULL instead of looping back to Head. 223 if (MO == Head) 224 HeadRef = Next; 225 else 226 Prev->Contents.Reg.Next = Next; 227 228 (Next ? Next : Head)->Contents.Reg.Prev = Prev; 229 230 MO->Contents.Reg.Prev = 0; 231 MO->Contents.Reg.Next = 0; 232} 233 234/// Move NumOps operands from Src to Dst, updating use-def lists as needed. 235/// 236/// The Dst range is assumed to be uninitialized memory. (Or it may contain 237/// operands that won't be destroyed, which is OK because the MO destructor is 238/// trivial anyway). 239/// 240/// The Src and Dst ranges may overlap. 241void MachineRegisterInfo::moveOperands(MachineOperand *Dst, 242 MachineOperand *Src, 243 unsigned NumOps) { 244 assert(Src != Dst && NumOps && "Noop moveOperands"); 245 246 // Copy backwards if Dst is within the Src range. 247 int Stride = 1; 248 if (Dst >= Src && Dst < Src + NumOps) { 249 Stride = -1; 250 Dst += NumOps - 1; 251 Src += NumOps - 1; 252 } 253 254 // Copy one operand at a time. 255 do { 256 new (Dst) MachineOperand(*Src); 257 258 // Dst takes Src's place in the use-def chain. 259 if (Src->isReg()) { 260 MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 261 MachineOperand *Prev = Src->Contents.Reg.Prev; 262 MachineOperand *Next = Src->Contents.Reg.Next; 263 assert(Head && "List empty, but operand is chained"); 264 assert(Prev && "Operand was not on use-def list"); 265 266 // Prev links are circular, next link is NULL instead of looping back to 267 // Head. 268 if (Src == Head) 269 Head = Dst; 270 else 271 Prev->Contents.Reg.Next = Dst; 272 273 // Update Prev pointer. This also works when Src was pointing to itself 274 // in a 1-element list. In that case Head == Dst. 275 (Next ? Next : Head)->Contents.Reg.Prev = Dst; 276 } 277 278 Dst += Stride; 279 Src += Stride; 280 } while (--NumOps); 281} 282 283/// replaceRegWith - Replace all instances of FromReg with ToReg in the 284/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 285/// except that it also changes any definitions of the register as well. 286void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 287 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 288 289 // TODO: This could be more efficient by bulk changing the operands. 290 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 291 MachineOperand &O = *I; 292 ++I; 293 O.setReg(ToReg); 294 } 295} 296 297 298/// getVRegDef - Return the machine instr that defines the specified virtual 299/// register or null if none is found. This assumes that the code is in SSA 300/// form, so there should only be one definition. 301MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 302 // Since we are in SSA form, we can use the first definition. 303 def_instr_iterator I = def_instr_begin(Reg); 304 assert((I.atEnd() || std::next(I) == def_instr_end()) && 305 "getVRegDef assumes a single definition or no definition"); 306 return !I.atEnd() ? &*I : 0; 307} 308 309/// getUniqueVRegDef - Return the unique machine instr that defines the 310/// specified virtual register or null if none is found. If there are 311/// multiple definitions or no definition, return null. 312MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 313 if (def_empty(Reg)) return 0; 314 def_instr_iterator I = def_instr_begin(Reg); 315 if (std::next(I) != def_instr_end()) 316 return 0; 317 return &*I; 318} 319 320bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 321 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 322 if (UI == use_nodbg_end()) 323 return false; 324 return ++UI == use_nodbg_end(); 325} 326 327/// clearKillFlags - Iterate over all the uses of the given register and 328/// clear the kill flag from the MachineOperand. This function is used by 329/// optimization passes which extend register lifetimes and need only 330/// preserve conservative kill flag information. 331void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 332 for (MachineOperand &MO : use_operands(Reg)) 333 MO.setIsKill(false); 334} 335 336bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 337 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 338 if (I->first == Reg || I->second == Reg) 339 return true; 340 return false; 341} 342 343/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 344/// corresponding live-in physical register. 345unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 346 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 347 if (I->second == VReg) 348 return I->first; 349 return 0; 350} 351 352/// getLiveInVirtReg - If PReg is a live-in physical register, return the 353/// corresponding live-in physical register. 354unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 355 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 356 if (I->first == PReg) 357 return I->second; 358 return 0; 359} 360 361/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 362/// into the given entry block. 363void 364MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 365 const TargetRegisterInfo &TRI, 366 const TargetInstrInfo &TII) { 367 // Emit the copies into the top of the block. 368 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 369 if (LiveIns[i].second) { 370 if (use_empty(LiveIns[i].second)) { 371 // The livein has no uses. Drop it. 372 // 373 // It would be preferable to have isel avoid creating live-in 374 // records for unused arguments in the first place, but it's 375 // complicated by the debug info code for arguments. 376 LiveIns.erase(LiveIns.begin() + i); 377 --i; --e; 378 } else { 379 // Emit a copy. 380 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 381 TII.get(TargetOpcode::COPY), LiveIns[i].second) 382 .addReg(LiveIns[i].first); 383 384 // Add the register to the entry block live-in set. 385 EntryMBB->addLiveIn(LiveIns[i].first); 386 } 387 } else { 388 // Add the register to the entry block live-in set. 389 EntryMBB->addLiveIn(LiveIns[i].first); 390 } 391} 392 393#ifndef NDEBUG 394void MachineRegisterInfo::dumpUses(unsigned Reg) const { 395 for (MachineInstr &I : use_instructions(Reg)) 396 I.dump(); 397} 398#endif 399 400void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 401 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); 402 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && 403 "Invalid ReservedRegs vector from target"); 404} 405 406bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 407 const MachineFunction &MF) const { 408 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 409 410 // Check if any overlapping register is modified, or allocatable so it may be 411 // used later. 412 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true); 413 AI.isValid(); ++AI) 414 if (!def_empty(*AI) || isAllocatable(*AI)) 415 return false; 416 return true; 417} 418 419/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the 420/// specified register as undefined which causes the DBG_VALUE to be 421/// deleted during LiveDebugVariables analysis. 422void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const { 423 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.) 424 MachineRegisterInfo::use_instr_iterator nextI; 425 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end(); 426 I != E; I = nextI) { 427 nextI = std::next(I); // I is invalidated by the setReg 428 MachineInstr *UseMI = &*I; 429 if (UseMI->isDebugValue()) 430 UseMI->getOperand(0).setReg(0U); 431 } 432} 433