MachineRegisterInfo.cpp revision 6d1fd0b979cb88809ebb77a24f4da69e1d67606b
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implementation of the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/CodeGen/MachineInstrBuilder.h" 16#include "llvm/Target/TargetInstrInfo.h" 17#include "llvm/Target/TargetMachine.h" 18using namespace llvm; 19 20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21 : IsSSA(true) { 22 VRegInfo.reserve(256); 23 RegAllocHints.reserve(256); 24 UsedPhysRegs.resize(TRI.getNumRegs()); 25 26 // Create the physreg use/def lists. 27 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 28 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 29} 30 31MachineRegisterInfo::~MachineRegisterInfo() { 32#ifndef NDEBUG 33 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 34 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 35 "Vreg use list non-empty still?"); 36 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 37 assert(!PhysRegUseDefLists[i] && 38 "PhysRegUseDefLists has entries after all instructions are deleted"); 39#endif 40 delete [] PhysRegUseDefLists; 41} 42 43/// setRegClass - Set the register class of the specified virtual register. 44/// 45void 46MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 47 VRegInfo[Reg].first = RC; 48} 49 50const TargetRegisterClass * 51MachineRegisterInfo::constrainRegClass(unsigned Reg, 52 const TargetRegisterClass *RC) { 53 const TargetRegisterClass *OldRC = getRegClass(Reg); 54 if (OldRC == RC) 55 return RC; 56 const TargetRegisterClass *NewRC = getCommonSubClass(OldRC, RC); 57 if (!NewRC) 58 return 0; 59 if (NewRC != OldRC) 60 setRegClass(Reg, NewRC); 61 return NewRC; 62} 63 64bool 65MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 66 const TargetInstrInfo *TII = TM.getInstrInfo(); 67 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 68 const TargetRegisterClass *OldRC = getRegClass(Reg); 69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 70 71 // Stop early if there is no room to grow. 72 if (NewRC == OldRC) 73 return false; 74 75 // Accumulate constraints from all uses. 76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 77 ++I) { 78 // TRI doesn't have accurate enough information to model this yet. 79 if (I.getOperand().getSubReg()) 80 return false; 81 // Inline asm instuctions don't remember their constraints. 82 if (I->isInlineAsm()) 83 return false; 84 const TargetRegisterClass *OpRC = 85 TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI); 86 if (OpRC) 87 NewRC = getCommonSubClass(NewRC, OpRC); 88 if (!NewRC || NewRC == OldRC) 89 return false; 90 } 91 setRegClass(Reg, NewRC); 92 return true; 93} 94 95/// createVirtualRegister - Create and return a new virtual register in the 96/// function with the specified register class. 97/// 98unsigned 99MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 100 assert(RegClass && "Cannot create register without RegClass!"); 101 assert(RegClass->isAllocatable() && 102 "Virtual register RegClass must be allocatable."); 103 104 // New virtual register number. 105 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 106 107 // Add a reg, but keep track of whether the vector reallocated or not. 108 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); 109 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; 110 VRegInfo.grow(Reg); 111 VRegInfo[Reg].first = RegClass; 112 RegAllocHints.grow(Reg); 113 114 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) 115 // The vector reallocated, handle this now. 116 HandleVRegListReallocation(); 117 return Reg; 118} 119 120/// HandleVRegListReallocation - We just added a virtual register to the 121/// VRegInfo info list and it reallocated. Update the use/def lists info 122/// pointers. 123void MachineRegisterInfo::HandleVRegListReallocation() { 124 // The back pointers for the vreg lists point into the previous vector. 125 // Update them to point to their correct slots. 126 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 127 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 128 MachineOperand *List = VRegInfo[Reg].second; 129 if (!List) continue; 130 // Update the back-pointer to be accurate once more. 131 List->Contents.Reg.Prev = &VRegInfo[Reg].second; 132 } 133} 134 135/// replaceRegWith - Replace all instances of FromReg with ToReg in the 136/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 137/// except that it also changes any definitions of the register as well. 138void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 139 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 140 141 // TODO: This could be more efficient by bulk changing the operands. 142 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 143 MachineOperand &O = I.getOperand(); 144 ++I; 145 O.setReg(ToReg); 146 } 147} 148 149 150/// getVRegDef - Return the machine instr that defines the specified virtual 151/// register or null if none is found. This assumes that the code is in SSA 152/// form, so there should only be one definition. 153MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 154 // Since we are in SSA form, we can use the first definition. 155 if (!def_empty(Reg)) 156 return &*def_begin(Reg); 157 return 0; 158} 159 160bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 161 use_iterator UI = use_begin(RegNo); 162 if (UI == use_end()) 163 return false; 164 return ++UI == use_end(); 165} 166 167bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 168 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 169 if (UI == use_nodbg_end()) 170 return false; 171 return ++UI == use_nodbg_end(); 172} 173 174/// clearKillFlags - Iterate over all the uses of the given register and 175/// clear the kill flag from the MachineOperand. This function is used by 176/// optimization passes which extend register lifetimes and need only 177/// preserve conservative kill flag information. 178void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 179 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 180 UI.getOperand().setIsKill(false); 181} 182 183bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 184 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 185 if (I->first == Reg || I->second == Reg) 186 return true; 187 return false; 188} 189 190bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 191 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 192 if (*I == Reg) 193 return true; 194 return false; 195} 196 197/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 198/// corresponding live-in physical register. 199unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 200 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 201 if (I->second == VReg) 202 return I->first; 203 return 0; 204} 205 206/// getLiveInVirtReg - If PReg is a live-in physical register, return the 207/// corresponding live-in physical register. 208unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 209 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 210 if (I->first == PReg) 211 return I->second; 212 return 0; 213} 214 215/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 216/// into the given entry block. 217void 218MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 219 const TargetRegisterInfo &TRI, 220 const TargetInstrInfo &TII) { 221 // Emit the copies into the top of the block. 222 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 223 if (LiveIns[i].second) { 224 if (use_empty(LiveIns[i].second)) { 225 // The livein has no uses. Drop it. 226 // 227 // It would be preferable to have isel avoid creating live-in 228 // records for unused arguments in the first place, but it's 229 // complicated by the debug info code for arguments. 230 LiveIns.erase(LiveIns.begin() + i); 231 --i; --e; 232 } else { 233 // Emit a copy. 234 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 235 TII.get(TargetOpcode::COPY), LiveIns[i].second) 236 .addReg(LiveIns[i].first); 237 238 // Add the register to the entry block live-in set. 239 EntryMBB->addLiveIn(LiveIns[i].first); 240 } 241 } else { 242 // Add the register to the entry block live-in set. 243 EntryMBB->addLiveIn(LiveIns[i].first); 244 } 245} 246 247void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { 248 for (int i = UsedPhysRegs.find_first(); i >= 0; 249 i = UsedPhysRegs.find_next(i)) 250 for (const unsigned *SS = TRI.getSubRegisters(i); 251 unsigned SubReg = *SS; ++SS) 252 if (SubReg > unsigned(i)) 253 UsedPhysRegs.set(SubReg); 254} 255 256#ifndef NDEBUG 257void MachineRegisterInfo::dumpUses(unsigned Reg) const { 258 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 259 I.getOperand().getParent()->dump(); 260} 261#endif 262