MachineRegisterInfo.cpp revision 7a7b809327b3905a1b035c1b7e061822ec627f3f 
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implementation of the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15using namespace llvm;
16
17MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
18  VRegInfo.reserve(256);
19  RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
20  UsedPhysRegs.resize(TRI.getNumRegs());
21
22  // Create the physreg use/def lists.
23  PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
24  memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
25}
26
27MachineRegisterInfo::~MachineRegisterInfo() {
28#ifndef NDEBUG
29  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
30    assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
31  for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
32    assert(!PhysRegUseDefLists[i] &&
33           "PhysRegUseDefLists has entries after all instructions are deleted");
34#endif
35  delete [] PhysRegUseDefLists;
36}
37
38/// createVirtualRegister - Create and return a new virtual register in the
39/// function with the specified register class.
40///
41unsigned
42MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
43  assert(RegClass && "Cannot create register without RegClass!");
44  // Add a reg, but keep track of whether the vector reallocated or not.
45  void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
46  VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
47
48  if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
49    // The vector reallocated, handle this now.
50    HandleVRegListReallocation();
51  unsigned VR = getLastVirtReg();
52  RegClass2VRegMap[RegClass->getID()].push_back(VR);
53  return VR;
54}
55
56/// HandleVRegListReallocation - We just added a virtual register to the
57/// VRegInfo info list and it reallocated.  Update the use/def lists info
58/// pointers.
59void MachineRegisterInfo::HandleVRegListReallocation() {
60  // The back pointers for the vreg lists point into the previous vector.
61  // Update them to point to their correct slots.
62  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
63    MachineOperand *List = VRegInfo[i].second;
64    if (!List) continue;
65    // Update the back-pointer to be accurate once more.
66    List->Contents.Reg.Prev = &VRegInfo[i].second;
67  }
68}
69
70/// replaceRegWith - Replace all instances of FromReg with ToReg in the
71/// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
72/// except that it also changes any definitions of the register as well.
73void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
74  assert(FromReg != ToReg && "Cannot replace a reg with itself");
75
76  // TODO: This could be more efficient by bulk changing the operands.
77  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
78    MachineOperand &O = I.getOperand();
79    ++I;
80    O.setReg(ToReg);
81  }
82}
83
84
85/// getVRegDef - Return the machine instr that defines the specified virtual
86/// register or null if none is found.  This assumes that the code is in SSA
87/// form, so there should only be one definition.
88MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
89  assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
90         "Invalid vreg!");
91  for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
92    // Since we are in SSA form, we can stop at the first definition.
93    if (I.getOperand().isDef())
94      return &*I;
95  }
96  return 0;
97}
98
99
100#ifndef NDEBUG
101void MachineRegisterInfo::dumpUses(unsigned Reg) const {
102  for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
103    I.getOperand().getParent()->dump();
104}
105#endif
106