MachineRegisterInfo.cpp revision 82b07dc4995d48065bd95affff4d8513a5cad4f2
1521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// 3521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// The LLVM Compiler Infrastructure 4521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// 5521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// License. See LICENSE.TXT for details. 7521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// 8521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)//===----------------------------------------------------------------------===// 9521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// 10521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// Implementation of the MachineRegisterInfo class. 11521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)// 12521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)//===----------------------------------------------------------------------===// 13521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 14521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)#include "llvm/CodeGen/MachineRegisterInfo.h" 15521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)#include "llvm/CodeGen/MachineInstrBuilder.h" 16521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)#include "llvm/Target/TargetInstrInfo.h" 17521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)#include "llvm/Support/CommandLine.h" 18521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)using namespace llvm; 19521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 20521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 21521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) VRegInfo.reserve(256); 22521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) RegAllocHints.reserve(256); 23521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. 24521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) UsedPhysRegs.resize(TRI.getNumRegs()); 25521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 26521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // Create the physreg use/def lists. 27521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 28521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 29521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)} 30521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 31521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)MachineRegisterInfo::~MachineRegisterInfo() { 32521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)#ifndef NDEBUG 33521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 34197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 35197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 367757ec2eadfa2dd8ac2aeed0a4399e9b07ec38cbBen Murdoch assert(!PhysRegUseDefLists[i] && 371e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles) "PhysRegUseDefLists has entries after all instructions are deleted"); 38197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch#endif 3906f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles) delete [] PhysRegUseDefLists; 4006f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles)} 41521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 42197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch/// setRegClass - Set the register class of the specified virtual register. 43521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)/// 441e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles)void 451e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles)MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 4651b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) unsigned VR = Reg; 47521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) Reg -= TargetRegisterInfo::FirstVirtualRegister; 48521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) assert(Reg < VRegInfo.size() && "Invalid vreg!"); 493c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 503c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch VRegInfo[Reg].first = RC; 513c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch 52521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // Remove from old register class's vregs list. This may be slow but 5351b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) // fortunately this operation is rarely needed. 5451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 55c1847b1379d12d0e05df27436bf19a9b1bf12deaTorne (Richard Coles) std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 56521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) VRegs.erase(I); 57d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 58d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) // Add to new register class's vregs list. 59d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) RegClass2VRegMap[RC->getID()].push_back(VR); 60d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)} 61d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 62d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)/// createVirtualRegister - Create and return a new virtual register in the 63d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)/// function with the specified register class. 64d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)/// 65d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)unsigned 66d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 67d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) assert(RegClass && "Cannot create register without RegClass!"); 68d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) // Add a reg, but keep track of whether the vector reallocated or not. 69d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 70d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 71d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) RegAllocHints.push_back(std::make_pair(0, 0)); 72d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 73d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 7409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) // The vector reallocated, handle this now. 75197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch HandleVRegListReallocation(); 76521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) unsigned VR = getLastVirtReg(); 77197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch RegClass2VRegMap[RegClass->getID()].push_back(VR); 78521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) return VR; 79197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch} 80521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 81521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)/// HandleVRegListReallocation - We just added a virtual register to the 8251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)/// VRegInfo info list and it reallocated. Update the use/def lists info 831e202183a5dc46166763171984b285173f8585e5Torne (Richard Coles)/// pointers. 8451b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)void MachineRegisterInfo::HandleVRegListReallocation() { 85521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // The back pointers for the vreg lists point into the previous vector. 86521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // Update them to point to their correct slots. 8709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 88521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) MachineOperand *List = VRegInfo[i].second; 89521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) if (!List) continue; 903c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // Update the back-pointer to be accurate once more. 913c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch List->Contents.Reg.Prev = &VRegInfo[i].second; 927242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci } 93323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles)} 94f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) 9523e46e0f045bc1935a09565578b448d36cfc5b8cBen Murdoch/// replaceRegWith - Replace all instances of FromReg with ToReg in the 9623e46e0f045bc1935a09565578b448d36cfc5b8cBen Murdoch/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 97f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles)/// except that it also changes any definitions of the register as well. 9806f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles)void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 9906f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles) assert(FromReg != ToReg && "Cannot replace a reg with itself"); 100f79f16f17ddc4f842d7b7a38603e280e94be826aTorne (Richard Coles) 101521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // TODO: This could be more efficient by bulk changing the operands. 10251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 103521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) MachineOperand &O = I.getOperand(); 1047242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci ++I; 105521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) O.setReg(ToReg); 106521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) } 107521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)} 108521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 109197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch 110197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch/// getVRegDef - Return the machine instr that defines the specified virtual 111197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch/// register or null if none is found. This assumes that the code is in SSA 112197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch/// form, so there should only be one definition. 113521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 11406f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles) assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 11506f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles) "Invalid vreg!"); 1167242dc3dbeb210b5e876a3c42d1ec1a667fc621aPrimiano Tucci // Since we are in SSA form, we can use the first definition. 117197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch if (!def_empty(Reg)) 118521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) return &*def_begin(Reg); 119521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) return 0; 12009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)} 12109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 12209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 12309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) use_iterator UI = use_begin(RegNo); 12409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) if (UI == use_end()) 12509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return false; 12609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return ++UI == use_end(); 12709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)} 12809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 12909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 13009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) use_nodbg_iterator UI = use_nodbg_begin(RegNo); 13109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) if (UI == use_nodbg_end()) 13209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return false; 13309380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return ++UI == use_nodbg_end(); 13409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)} 13509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 136323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles)bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 13709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 138323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) if (I->first == Reg || I->second == Reg) 139d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) return true; 14009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return false; 14109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)} 142323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) 143323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles)bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 144323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 14509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) if (*I == Reg) 14609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return true; 147323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) return false; 148323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles)} 14909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 15009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 15109380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)/// corresponding live-in physical register. 15209380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 153d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 15409380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) if (I->second == VReg) 15509380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return I->first; 15609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) return 0; 157323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles)} 15809380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) 15909380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)static cl::opt<bool> 16009380295ba73501a205346becac22c6978e4671dTorne (Richard Coles)SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 161197021e6b966cfb06891637935ef33fff06433d1Ben Murdoch cl::desc("Schedule copies of livein registers"), 162521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) cl::init(false)); 163521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 164521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 165e69819bd8e388ea4ad1636a19aa6b2eed4952191Ben Murdoch/// physical register has only a single copy use, then coalesced the copy 166521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)/// if possible. 167d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles)static void EmitLiveInCopy(MachineBasicBlock *MBB, 168d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) MachineBasicBlock::iterator &InsertPos, 169521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) unsigned VirtReg, unsigned PhysReg, 170521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) const TargetRegisterClass *RC, 171521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) DenseMap<MachineInstr*, unsigned> &CopyRegMap, 17251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) const MachineRegisterInfo &MRI, 173521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) const TargetRegisterInfo &TRI, 174521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) const TargetInstrInfo &TII) { 175521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) unsigned NumUses = 0; 176521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) MachineInstr *UseMI = NULL; 177521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 178521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) UE = MRI.use_end(); UI != UE; ++UI) { 179521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) UseMI = &*UI; 18051b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) if (++NumUses > 1) 181521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) break; 182521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) } 183323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) 18423e46e0f045bc1935a09565578b448d36cfc5b8cBen Murdoch // If the number of uses is not one, or the use is not a move instruction, 18523e46e0f045bc1935a09565578b448d36cfc5b8cBen Murdoch // don't coalesce. Also, only coalesce away a virtual register to virtual 186e69819bd8e388ea4ad1636a19aa6b2eed4952191Ben Murdoch // register copy. 18723e46e0f045bc1935a09565578b448d36cfc5b8cBen Murdoch bool Coalesced = false; 188d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 1891fad5ca6c42d689812b66fc493992aa6d747a6fbBen Murdoch if (NumUses == 1 && 1901fad5ca6c42d689812b66fc493992aa6d747a6fbBen Murdoch TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 191521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) TargetRegisterInfo::isVirtualRegister(DstReg)) { 192521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) VirtReg = DstReg; 193521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) Coalesced = true; 194521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) } 195521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 19609380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) // Now find an ideal location to insert the copy. 19709380295ba73501a205346becac22c6978e4671dTorne (Richard Coles) MachineBasicBlock::iterator Pos = InsertPos; 19851b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) while (Pos != MBB->begin()) { 199d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) MachineInstr *PrevMI = prior(Pos); 200521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 201521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // copyRegToReg might emit multiple instructions to do a copy. 202521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 20323e46e0f045bc1935a09565578b448d36cfc5b8cBen Murdoch if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 204521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // This is what the BB looks like right now: 205521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // r1024 = mov r0 206521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) // ... 2073c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // r1 = mov r1024 2083c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // 2093c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // We want to insert "r1025 = mov r1". Inserting this copy below the 2103c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // move to r1024 makes it impossible for that move to be coalesced. 2113c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // 21251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) // r1025 = mov r1 2133c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // r1024 = mov r0 2143c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // ... 215323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) // r1 = mov 1024 2163c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // r2 = mov 1025 2173c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch break; // Woot! Found a good location. 2183c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch --Pos; 219d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) } 2203c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch 2213c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC, 2223c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch DebugLoc()); 2233c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 2243c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch (void) Emitted; 225d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) 2263c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 2273c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch if (Coalesced) { 2283c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch if (&*InsertPos == UseMI) ++InsertPos; 22951b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) MBB->erase(UseMI); 2303c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch } 2313c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch} 2323c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch 2333c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 2343c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch/// into the given entry block. 2353c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdochvoid 2363c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben MurdochMachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 2373c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch const TargetRegisterInfo &TRI, 2383c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch const TargetInstrInfo &TII) { 2393c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch if (SchedLiveInCopies) { 24051b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) // Emit the copies at a heuristically-determined location in the block. 2413c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch DenseMap<MachineInstr*, unsigned> CopyRegMap; 2423c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 243323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 2443c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch E = livein_end(); LI != E; ++LI) 2453c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch if (LI->second) { 2463c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch const TargetRegisterClass *RC = getRegClass(LI->second); 247d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 2483c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch RC, CopyRegMap, *this, TRI, TII); 2493c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch } 2503c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch } else { 251d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) // Emit the copies into the top of the block. 252d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 253d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) E = livein_end(); LI != E; ++LI) 254d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) if (LI->second) { 255323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) const TargetRegisterClass *RC = getRegClass(LI->second); 256323480423219ecd77329f8326dc5e0e3b50926d4Torne (Richard Coles) bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 257d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) LI->second, LI->first, RC, RC, 258f6b7aed3f7ce69aca0d7a032d144cbd088b04393Torne (Richard Coles) DebugLoc()); 2593c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 2603c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch (void) Emitted; 2613c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch } 26251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) } 2633c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch 2643c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch // Add function live-ins to entry block live-in set. 2653c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch for (MachineRegisterInfo::livein_iterator I = livein_begin(), 2663c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch E = livein_end(); I != E; ++I) 2673c9e4aeaee9f9b0a9a814da07bcb33319c7ea363Ben Murdoch EntryMBB->addLiveIn(I->first); 26851b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)} 269521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 270521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { 271521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) for (int i = UsedPhysRegs.find_first(); i >= 0; 27251b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) i = UsedPhysRegs.find_next(i)) 273521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) for (const unsigned *SS = TRI.getSubRegisters(i); 274521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) unsigned SubReg = *SS; ++SS) 27551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles) if (SubReg > i) 276521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) UsedPhysRegs.set(SubReg); 277521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles)} 278521d96ec04ace82590870fb04353ec4f82bb150fTorne (Richard Coles) 27951b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)#ifndef NDEBUG 28006f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles)void MachineRegisterInfo::dumpUses(unsigned Reg) const { 28106f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles) for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 282d5428f32f5d1719f774f62e19147104ca245a3abTorne (Richard Coles) I.getOperand().getParent()->dump(); 28306f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles)} 28406f816c7c76bc45a15e452ade8a34e8af077693eTorne (Richard Coles)#endif 28551b2906e11752df6c18351cf520e30522d3b53a1Torne (Richard Coles)