MachineRegisterInfo.cpp revision a91a7d594ff1e1503731ca92f72e627bdfd18f3f 
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implementation of the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15using namespace llvm;
16
17MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) {
18  VRegInfo.reserve(256);
19  UsedPhysRegs.resize(MRI.getNumRegs());
20
21  // Create the physreg use/def lists.
22  PhysRegUseDefLists = new MachineOperand*[MRI.getNumRegs()];
23  memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*MRI.getNumRegs());
24}
25
26MachineRegisterInfo::~MachineRegisterInfo() {
27#ifndef NDEBUG
28  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
29    assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
30#endif
31  delete [] PhysRegUseDefLists;
32}
33
34/// HandleVRegListReallocation - We just added a virtual register to the
35/// VRegInfo info list and it reallocated.  Update the use/def lists info
36/// pointers.
37void MachineRegisterInfo::HandleVRegListReallocation() {
38  // The back pointers for the vreg lists point into the previous vector.
39  // Update them to point to their correct slots.
40  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
41    MachineOperand *List = VRegInfo[i].second;
42    if (!List) continue;
43    // Update the back-pointer to be accurate once more.
44    List->Contents.Reg.Prev = &VRegInfo[i].second;
45  }
46}
47
48
49/// getVRegDef - Return the machine instr that defines the specified virtual
50/// register or null if none is found.  This assumes that the code is in SSA
51/// form, so there should only be one definition.
52MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
53  assert(Reg-MRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
54         "Invalid vreg!");
55  for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) {
56    // Since we are in SSA form, we can stop at the first definition.
57    if (I->isDef())
58      return I->getParent();
59  }
60  return 0;
61}
62