MachineRegisterInfo.cpp revision bced5cd924e47818d67e33b3ae1550ab96fc239a
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implementation of the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/CodeGen/MachineInstrBuilder.h" 16#include "llvm/Target/TargetInstrInfo.h" 17#include "llvm/Target/TargetMachine.h" 18using namespace llvm; 19 20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21 : TRI(&TRI), IsSSA(true), TracksLiveness(true) { 22 VRegInfo.reserve(256); 23 RegAllocHints.reserve(256); 24 UsedRegUnits.resize(TRI.getNumRegUnits()); 25 UsedPhysRegMask.resize(TRI.getNumRegs()); 26 27 // Create the physreg use/def lists. 28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 30} 31 32MachineRegisterInfo::~MachineRegisterInfo() { 33#ifndef NDEBUG 34 clearVirtRegs(); 35 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) 36 assert(!PhysRegUseDefLists[i] && 37 "PhysRegUseDefLists has entries after all instructions are deleted"); 38#endif 39 delete [] PhysRegUseDefLists; 40} 41 42/// setRegClass - Set the register class of the specified virtual register. 43/// 44void 45MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 46 VRegInfo[Reg].first = RC; 47} 48 49const TargetRegisterClass * 50MachineRegisterInfo::constrainRegClass(unsigned Reg, 51 const TargetRegisterClass *RC, 52 unsigned MinNumRegs) { 53 const TargetRegisterClass *OldRC = getRegClass(Reg); 54 if (OldRC == RC) 55 return RC; 56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 57 if (!NewRC || NewRC == OldRC) 58 return NewRC; 59 if (NewRC->getNumRegs() < MinNumRegs) 60 return 0; 61 setRegClass(Reg, NewRC); 62 return NewRC; 63} 64 65bool 66MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 67 const TargetInstrInfo *TII = TM.getInstrInfo(); 68 const TargetRegisterClass *OldRC = getRegClass(Reg); 69 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 70 71 // Stop early if there is no room to grow. 72 if (NewRC == OldRC) 73 return false; 74 75 // Accumulate constraints from all uses. 76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 77 ++I) { 78 const TargetRegisterClass *OpRC = 79 I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 80 if (unsigned SubIdx = I.getOperand().getSubReg()) { 81 if (OpRC) 82 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 83 else 84 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 85 } else if (OpRC) 86 NewRC = TRI->getCommonSubClass(NewRC, OpRC); 87 if (!NewRC || NewRC == OldRC) 88 return false; 89 } 90 setRegClass(Reg, NewRC); 91 return true; 92} 93 94/// createVirtualRegister - Create and return a new virtual register in the 95/// function with the specified register class. 96/// 97unsigned 98MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 99 assert(RegClass && "Cannot create register without RegClass!"); 100 assert(RegClass->isAllocatable() && 101 "Virtual register RegClass must be allocatable."); 102 103 // New virtual register number. 104 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 105 VRegInfo.grow(Reg); 106 VRegInfo[Reg].first = RegClass; 107 RegAllocHints.grow(Reg); 108 return Reg; 109} 110 111/// clearVirtRegs - Remove all virtual registers (after physreg assignment). 112void MachineRegisterInfo::clearVirtRegs() { 113#ifndef NDEBUG 114 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 115 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 116 "Vreg use list non-empty still?"); 117#endif 118 VRegInfo.clear(); 119} 120 121/// Add MO to the linked list of operands for its register. 122void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) { 123 assert(!MO->isOnRegUseList() && "Already on list"); 124 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 125 MachineOperand *const Head = HeadRef; 126 127 // Head points to the first list element. 128 // Next is NULL on the last list element. 129 // Prev pointers are circular, so Head->Prev == Last. 130 131 // Head is NULL for an empty list. 132 if (!Head) { 133 MO->Contents.Reg.Prev = MO; 134 MO->Contents.Reg.Next = 0; 135 HeadRef = MO; 136 return; 137 } 138 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!"); 139 140 // Insert MO between Last and Head in the circular Prev chain. 141 MachineOperand *Last = Head->Contents.Reg.Prev; 142 assert(Last && "Inconsistent use list"); 143 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!"); 144 Head->Contents.Reg.Prev = MO; 145 MO->Contents.Reg.Prev = Last; 146 147 // Def operands always precede uses. This allows def_iterator to stop early. 148 // Insert def operands at the front, and use operands at the back. 149 if (MO->isDef()) { 150 // Insert def at the front. 151 MO->Contents.Reg.Next = Head; 152 HeadRef = MO; 153 } else { 154 // Insert use at the end. 155 MO->Contents.Reg.Next = 0; 156 Last->Contents.Reg.Next = MO; 157 } 158} 159 160/// Remove MO from its use-def list. 161void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) { 162 assert(MO->isOnRegUseList() && "Operand not on use list"); 163 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg()); 164 MachineOperand *const Head = HeadRef; 165 assert(Head && "List already empty"); 166 167 // Unlink this from the doubly linked list of operands. 168 MachineOperand *Next = MO->Contents.Reg.Next; 169 MachineOperand *Prev = MO->Contents.Reg.Prev; 170 171 // Prev links are circular, next link is NULL instead of looping back to Head. 172 if (MO == Head) 173 HeadRef = Next; 174 else 175 Prev->Contents.Reg.Next = Next; 176 177 (Next ? Next : Head)->Contents.Reg.Prev = Prev; 178 179 MO->Contents.Reg.Prev = 0; 180 MO->Contents.Reg.Next = 0; 181} 182 183/// Move NumOps operands from Src to Dst, updating use-def lists as needed. 184/// 185/// The Dst range is assumed to be uninitialized memory. (Or it may contain 186/// operands that won't be destroyed, which is OK because the MO destructor is 187/// trivial anyway). 188/// 189/// The Src and Dst ranges may overlap. 190void MachineRegisterInfo::moveOperands(MachineOperand *Dst, 191 MachineOperand *Src, 192 unsigned NumOps) { 193 assert(Src != Dst && NumOps && "Noop moveOperands"); 194 195 // Copy backwards if Dst is within the Src range. 196 int Stride = 1; 197 if (Dst >= Src && Dst < Src + NumOps) { 198 Stride = -1; 199 Dst += NumOps - 1; 200 Src += NumOps - 1; 201 } 202 203 // Copy one operand at a time. 204 do { 205 new (Dst) MachineOperand(*Src); 206 207 // Dst takes Src's place in the use-def chain. 208 if (Src->isReg()) { 209 MachineOperand *&Head = getRegUseDefListHead(Src->getReg()); 210 MachineOperand *Prev = Src->Contents.Reg.Prev; 211 MachineOperand *Next = Src->Contents.Reg.Next; 212 assert(Head && "List empty, but operand is chained"); 213 assert(Prev && "Operand was not on use-def list"); 214 215 // Prev links are circular, next link is NULL instead of looping back to 216 // Head. 217 if (Src == Head) 218 Head = Dst; 219 else 220 Prev->Contents.Reg.Next = Dst; 221 222 // Update Prev pointer. This also works when Src was pointing to itself 223 // in a 1-element list. In that case Head == Dst. 224 (Next ? Next : Head)->Contents.Reg.Prev = Dst; 225 } 226 227 Dst += Stride; 228 Src += Stride; 229 } while (--NumOps); 230} 231 232/// replaceRegWith - Replace all instances of FromReg with ToReg in the 233/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 234/// except that it also changes any definitions of the register as well. 235void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 236 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 237 238 // TODO: This could be more efficient by bulk changing the operands. 239 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 240 MachineOperand &O = I.getOperand(); 241 ++I; 242 O.setReg(ToReg); 243 } 244} 245 246 247/// getVRegDef - Return the machine instr that defines the specified virtual 248/// register or null if none is found. This assumes that the code is in SSA 249/// form, so there should only be one definition. 250MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 251 // Since we are in SSA form, we can use the first definition. 252 def_iterator I = def_begin(Reg); 253 assert((I.atEnd() || llvm::next(I) == def_end()) && 254 "getVRegDef assumes a single definition or no definition"); 255 return !I.atEnd() ? &*I : 0; 256} 257 258/// getUniqueVRegDef - Return the unique machine instr that defines the 259/// specified virtual register or null if none is found. If there are 260/// multiple definitions or no definition, return null. 261MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const { 262 if (def_empty(Reg)) return 0; 263 def_iterator I = def_begin(Reg); 264 if (llvm::next(I) != def_end()) 265 return 0; 266 return &*I; 267} 268 269bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 270 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 271 if (UI == use_nodbg_end()) 272 return false; 273 return ++UI == use_nodbg_end(); 274} 275 276/// clearKillFlags - Iterate over all the uses of the given register and 277/// clear the kill flag from the MachineOperand. This function is used by 278/// optimization passes which extend register lifetimes and need only 279/// preserve conservative kill flag information. 280void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 281 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 282 UI.getOperand().setIsKill(false); 283} 284 285bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 286 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 287 if (I->first == Reg || I->second == Reg) 288 return true; 289 return false; 290} 291 292bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 293 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 294 if (*I == Reg) 295 return true; 296 return false; 297} 298 299/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 300/// corresponding live-in physical register. 301unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 302 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 303 if (I->second == VReg) 304 return I->first; 305 return 0; 306} 307 308/// getLiveInVirtReg - If PReg is a live-in physical register, return the 309/// corresponding live-in physical register. 310unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 311 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 312 if (I->first == PReg) 313 return I->second; 314 return 0; 315} 316 317/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 318/// into the given entry block. 319void 320MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 321 const TargetRegisterInfo &TRI, 322 const TargetInstrInfo &TII) { 323 // Emit the copies into the top of the block. 324 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 325 if (LiveIns[i].second) { 326 if (use_empty(LiveIns[i].second)) { 327 // The livein has no uses. Drop it. 328 // 329 // It would be preferable to have isel avoid creating live-in 330 // records for unused arguments in the first place, but it's 331 // complicated by the debug info code for arguments. 332 LiveIns.erase(LiveIns.begin() + i); 333 --i; --e; 334 } else { 335 // Emit a copy. 336 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 337 TII.get(TargetOpcode::COPY), LiveIns[i].second) 338 .addReg(LiveIns[i].first); 339 340 // Add the register to the entry block live-in set. 341 EntryMBB->addLiveIn(LiveIns[i].first); 342 } 343 } else { 344 // Add the register to the entry block live-in set. 345 EntryMBB->addLiveIn(LiveIns[i].first); 346 } 347} 348 349#ifndef NDEBUG 350void MachineRegisterInfo::dumpUses(unsigned Reg) const { 351 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 352 I.getOperand().getParent()->dump(); 353} 354#endif 355 356void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 357 ReservedRegs = TRI->getReservedRegs(MF); 358 assert(ReservedRegs.size() == TRI->getNumRegs() && 359 "Invalid ReservedRegs vector from target"); 360} 361 362bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 363 const MachineFunction &MF) const { 364 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 365 366 // Check if any overlapping register is modified, or allocatable so it may be 367 // used later. 368 for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) 369 if (!def_empty(*AI) || isAllocatable(*AI)) 370 return false; 371 return true; 372} 373