MachineRegisterInfo.cpp revision d9f0ff56a1878347fe5a0f162ef8c2ef2b63aeb5
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implementation of the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/CodeGen/MachineInstrBuilder.h" 16#include "llvm/Target/TargetInstrInfo.h" 17#include "llvm/Target/TargetMachine.h" 18using namespace llvm; 19 20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) 21 : TRI(&TRI), IsSSA(true) { 22 VRegInfo.reserve(256); 23 RegAllocHints.reserve(256); 24 UsedPhysRegs.resize(TRI.getNumRegs()); 25 UsedPhysRegMask.resize(TRI.getNumRegs()); 26 27 // Create the physreg use/def lists. 28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 30} 31 32MachineRegisterInfo::~MachineRegisterInfo() { 33#ifndef NDEBUG 34 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) 35 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && 36 "Vreg use list non-empty still?"); 37 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 38 assert(!PhysRegUseDefLists[i] && 39 "PhysRegUseDefLists has entries after all instructions are deleted"); 40#endif 41 delete [] PhysRegUseDefLists; 42} 43 44/// setRegClass - Set the register class of the specified virtual register. 45/// 46void 47MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 48 VRegInfo[Reg].first = RC; 49} 50 51const TargetRegisterClass * 52MachineRegisterInfo::constrainRegClass(unsigned Reg, 53 const TargetRegisterClass *RC, 54 unsigned MinNumRegs) { 55 const TargetRegisterClass *OldRC = getRegClass(Reg); 56 if (OldRC == RC) 57 return RC; 58 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 59 if (!NewRC || NewRC == OldRC) 60 return NewRC; 61 if (NewRC->getNumRegs() < MinNumRegs) 62 return 0; 63 setRegClass(Reg, NewRC); 64 return NewRC; 65} 66 67bool 68MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { 69 const TargetInstrInfo *TII = TM.getInstrInfo(); 70 const TargetRegisterClass *OldRC = getRegClass(Reg); 71 const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); 72 73 // Stop early if there is no room to grow. 74 if (NewRC == OldRC) 75 return false; 76 77 // Accumulate constraints from all uses. 78 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 79 ++I) { 80 const TargetRegisterClass *OpRC = 81 I->getRegClassConstraint(I.getOperandNo(), TII, TRI); 82 if (unsigned SubIdx = I.getOperand().getSubReg()) { 83 if (OpRC) 84 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx); 85 else 86 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx); 87 } else if (OpRC) 88 NewRC = TRI->getCommonSubClass(NewRC, OpRC); 89 if (!NewRC || NewRC == OldRC) 90 return false; 91 } 92 setRegClass(Reg, NewRC); 93 return true; 94} 95 96/// createVirtualRegister - Create and return a new virtual register in the 97/// function with the specified register class. 98/// 99unsigned 100MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 101 assert(RegClass && "Cannot create register without RegClass!"); 102 assert(RegClass->isAllocatable() && 103 "Virtual register RegClass must be allocatable."); 104 105 // New virtual register number. 106 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); 107 108 // Add a reg, but keep track of whether the vector reallocated or not. 109 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); 110 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; 111 VRegInfo.grow(Reg); 112 VRegInfo[Reg].first = RegClass; 113 RegAllocHints.grow(Reg); 114 115 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) 116 // The vector reallocated, handle this now. 117 HandleVRegListReallocation(); 118 return Reg; 119} 120 121/// HandleVRegListReallocation - We just added a virtual register to the 122/// VRegInfo info list and it reallocated. Update the use/def lists info 123/// pointers. 124void MachineRegisterInfo::HandleVRegListReallocation() { 125 // The back pointers for the vreg lists point into the previous vector. 126 // Update them to point to their correct slots. 127 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { 128 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 129 MachineOperand *List = VRegInfo[Reg].second; 130 if (!List) continue; 131 // Update the back-pointer to be accurate once more. 132 List->Contents.Reg.Prev = &VRegInfo[Reg].second; 133 } 134} 135 136/// replaceRegWith - Replace all instances of FromReg with ToReg in the 137/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 138/// except that it also changes any definitions of the register as well. 139void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 140 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 141 142 // TODO: This could be more efficient by bulk changing the operands. 143 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 144 MachineOperand &O = I.getOperand(); 145 ++I; 146 O.setReg(ToReg); 147 } 148} 149 150 151/// getVRegDef - Return the machine instr that defines the specified virtual 152/// register or null if none is found. This assumes that the code is in SSA 153/// form, so there should only be one definition. 154MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 155 // Since we are in SSA form, we can use the first definition. 156 if (!def_empty(Reg)) 157 return &*def_begin(Reg); 158 return 0; 159} 160 161bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 162 use_iterator UI = use_begin(RegNo); 163 if (UI == use_end()) 164 return false; 165 return ++UI == use_end(); 166} 167 168bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 169 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 170 if (UI == use_nodbg_end()) 171 return false; 172 return ++UI == use_nodbg_end(); 173} 174 175/// clearKillFlags - Iterate over all the uses of the given register and 176/// clear the kill flag from the MachineOperand. This function is used by 177/// optimization passes which extend register lifetimes and need only 178/// preserve conservative kill flag information. 179void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { 180 for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) 181 UI.getOperand().setIsKill(false); 182} 183 184bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 185 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 186 if (I->first == Reg || I->second == Reg) 187 return true; 188 return false; 189} 190 191bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 192 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 193 if (*I == Reg) 194 return true; 195 return false; 196} 197 198/// getLiveInPhysReg - If VReg is a live-in virtual register, return the 199/// corresponding live-in physical register. 200unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { 201 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 202 if (I->second == VReg) 203 return I->first; 204 return 0; 205} 206 207/// getLiveInVirtReg - If PReg is a live-in physical register, return the 208/// corresponding live-in physical register. 209unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { 210 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 211 if (I->first == PReg) 212 return I->second; 213 return 0; 214} 215 216/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 217/// into the given entry block. 218void 219MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 220 const TargetRegisterInfo &TRI, 221 const TargetInstrInfo &TII) { 222 // Emit the copies into the top of the block. 223 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) 224 if (LiveIns[i].second) { 225 if (use_empty(LiveIns[i].second)) { 226 // The livein has no uses. Drop it. 227 // 228 // It would be preferable to have isel avoid creating live-in 229 // records for unused arguments in the first place, but it's 230 // complicated by the debug info code for arguments. 231 LiveIns.erase(LiveIns.begin() + i); 232 --i; --e; 233 } else { 234 // Emit a copy. 235 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), 236 TII.get(TargetOpcode::COPY), LiveIns[i].second) 237 .addReg(LiveIns[i].first); 238 239 // Add the register to the entry block live-in set. 240 EntryMBB->addLiveIn(LiveIns[i].first); 241 } 242 } else { 243 // Add the register to the entry block live-in set. 244 EntryMBB->addLiveIn(LiveIns[i].first); 245 } 246} 247 248#ifndef NDEBUG 249void MachineRegisterInfo::dumpUses(unsigned Reg) const { 250 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 251 I.getOperand().getParent()->dump(); 252} 253#endif 254 255void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { 256 ReservedRegs = TRI->getReservedRegs(MF); 257} 258 259bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg, 260 const MachineFunction &MF) const { 261 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); 262 263 // Check if any overlapping register is modified. 264 for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R) 265 if (!def_empty(*R)) 266 return false; 267 268 // Check if any overlapping register is allocatable so it may be used later. 269 if (AllocatableRegs.empty()) 270 AllocatableRegs = TRI->getAllocatableSet(MF); 271 for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R) 272 if (AllocatableRegs.test(*R)) 273 return false; 274 return true; 275} 276