MachineRegisterInfo.cpp revision df317fed1e01f90c280562e38c1c7cc9401e9585
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implementation of the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineRegisterInfo.h" 15#include "llvm/Support/CommandLine.h" 16#include "llvm/Target/TargetInstrInfo.h" 17using namespace llvm; 18 19MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { 20 VRegInfo.reserve(256); 21 RegAllocHints.reserve(256); 22 RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. 23 UsedPhysRegs.resize(TRI.getNumRegs()); 24 25 // Create the physreg use/def lists. 26 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; 27 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); 28} 29 30MachineRegisterInfo::~MachineRegisterInfo() { 31#ifndef NDEBUG 32 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) 33 assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?"); 34 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) 35 assert(!PhysRegUseDefLists[i] && 36 "PhysRegUseDefLists has entries after all instructions are deleted"); 37#endif 38 delete [] PhysRegUseDefLists; 39} 40 41/// setRegClass - Set the register class of the specified virtual register. 42/// 43void 44MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { 45 unsigned VR = Reg; 46 Reg -= TargetRegisterInfo::FirstVirtualRegister; 47 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 48 const TargetRegisterClass *OldRC = VRegInfo[Reg].first; 49 VRegInfo[Reg].first = RC; 50 51 // Remove from old register class's vregs list. This may be slow but 52 // fortunately this operation is rarely needed. 53 std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()]; 54 std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); 55 VRegs.erase(I); 56 57 // Add to new register class's vregs list. 58 RegClass2VRegMap[RC->getID()].push_back(VR); 59} 60 61/// createVirtualRegister - Create and return a new virtual register in the 62/// function with the specified register class. 63/// 64unsigned 65MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ 66 assert(RegClass && "Cannot create register without RegClass!"); 67 // Add a reg, but keep track of whether the vector reallocated or not. 68 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0]; 69 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0)); 70 RegAllocHints.push_back(std::make_pair(0, 0)); 71 72 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1))) 73 // The vector reallocated, handle this now. 74 HandleVRegListReallocation(); 75 unsigned VR = getLastVirtReg(); 76 RegClass2VRegMap[RegClass->getID()].push_back(VR); 77 return VR; 78} 79 80/// HandleVRegListReallocation - We just added a virtual register to the 81/// VRegInfo info list and it reallocated. Update the use/def lists info 82/// pointers. 83void MachineRegisterInfo::HandleVRegListReallocation() { 84 // The back pointers for the vreg lists point into the previous vector. 85 // Update them to point to their correct slots. 86 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) { 87 MachineOperand *List = VRegInfo[i].second; 88 if (!List) continue; 89 // Update the back-pointer to be accurate once more. 90 List->Contents.Reg.Prev = &VRegInfo[i].second; 91 } 92} 93 94/// replaceRegWith - Replace all instances of FromReg with ToReg in the 95/// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 96/// except that it also changes any definitions of the register as well. 97void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { 98 assert(FromReg != ToReg && "Cannot replace a reg with itself"); 99 100 // TODO: This could be more efficient by bulk changing the operands. 101 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { 102 MachineOperand &O = I.getOperand(); 103 ++I; 104 O.setReg(ToReg); 105 } 106} 107 108 109/// getVRegDef - Return the machine instr that defines the specified virtual 110/// register or null if none is found. This assumes that the code is in SSA 111/// form, so there should only be one definition. 112MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { 113 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && 114 "Invalid vreg!"); 115 // Since we are in SSA form, we can use the first definition. 116 if (!def_empty(Reg)) 117 return &*def_begin(Reg); 118 return 0; 119} 120 121bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { 122 use_iterator UI = use_begin(RegNo); 123 if (UI == use_end()) 124 return false; 125 return ++UI == use_end(); 126} 127 128bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { 129 use_nodbg_iterator UI = use_nodbg_begin(RegNo); 130 if (UI == use_nodbg_end()) 131 return false; 132 return ++UI == use_nodbg_end(); 133} 134 135bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { 136 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) 137 if (I->first == Reg || I->second == Reg) 138 return true; 139 return false; 140} 141 142bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { 143 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) 144 if (*I == Reg) 145 return true; 146 return false; 147} 148 149static cl::opt<bool> 150SchedLiveInCopies("schedule-livein-copies", cl::Hidden, 151 cl::desc("Schedule copies of livein registers"), 152 cl::init(false)); 153 154/// EmitLiveInCopy - Emit a copy for a live in physical register. If the 155/// physical register has only a single copy use, then coalesced the copy 156/// if possible. 157static void EmitLiveInCopy(MachineBasicBlock *MBB, 158 MachineBasicBlock::iterator &InsertPos, 159 unsigned VirtReg, unsigned PhysReg, 160 const TargetRegisterClass *RC, 161 DenseMap<MachineInstr*, unsigned> &CopyRegMap, 162 const MachineRegisterInfo &MRI, 163 const TargetRegisterInfo &TRI, 164 const TargetInstrInfo &TII) { 165 unsigned NumUses = 0; 166 MachineInstr *UseMI = NULL; 167 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg), 168 UE = MRI.use_end(); UI != UE; ++UI) { 169 UseMI = &*UI; 170 if (++NumUses > 1) 171 break; 172 } 173 174 // If the number of uses is not one, or the use is not a move instruction, 175 // don't coalesce. Also, only coalesce away a virtual register to virtual 176 // register copy. 177 bool Coalesced = false; 178 unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; 179 if (NumUses == 1 && 180 TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && 181 TargetRegisterInfo::isVirtualRegister(DstReg)) { 182 VirtReg = DstReg; 183 Coalesced = true; 184 } 185 186 // Now find an ideal location to insert the copy. 187 MachineBasicBlock::iterator Pos = InsertPos; 188 while (Pos != MBB->begin()) { 189 MachineInstr *PrevMI = prior(Pos); 190 DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI); 191 // copyRegToReg might emit multiple instructions to do a copy. 192 unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second; 193 if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg)) 194 // This is what the BB looks like right now: 195 // r1024 = mov r0 196 // ... 197 // r1 = mov r1024 198 // 199 // We want to insert "r1025 = mov r1". Inserting this copy below the 200 // move to r1024 makes it impossible for that move to be coalesced. 201 // 202 // r1025 = mov r1 203 // r1024 = mov r0 204 // ... 205 // r1 = mov 1024 206 // r2 = mov 1025 207 break; // Woot! Found a good location. 208 --Pos; 209 } 210 211 bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC); 212 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 213 (void) Emitted; 214 215 CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg)); 216 if (Coalesced) { 217 if (&*InsertPos == UseMI) ++InsertPos; 218 MBB->erase(UseMI); 219 } 220} 221 222/// EmitLiveInCopies - Emit copies to initialize livein virtual registers 223/// into the given entry block. 224void 225MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, 226 const TargetRegisterInfo &TRI, 227 const TargetInstrInfo &TII) { 228 if (SchedLiveInCopies) { 229 // Emit the copies at a heuristically-determined location in the block. 230 DenseMap<MachineInstr*, unsigned> CopyRegMap; 231 MachineBasicBlock::iterator InsertPos = EntryMBB->begin(); 232 for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 233 E = livein_end(); LI != E; ++LI) 234 if (LI->second) { 235 const TargetRegisterClass *RC = getRegClass(LI->second); 236 EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first, 237 RC, CopyRegMap, *this, TRI, TII); 238 } 239 } else { 240 // Emit the copies into the top of the block. 241 for (MachineRegisterInfo::livein_iterator LI = livein_begin(), 242 E = livein_end(); LI != E; ++LI) 243 if (LI->second) { 244 const TargetRegisterClass *RC = getRegClass(LI->second); 245 bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(), 246 LI->second, LI->first, RC, RC); 247 assert(Emitted && "Unable to issue a live-in copy instruction!\n"); 248 (void) Emitted; 249 } 250 } 251 252 // Add function live-ins to entry block live-in set. 253 for (MachineRegisterInfo::livein_iterator I = livein_begin(), 254 E = livein_end(); I != E; ++I) 255 EntryMBB->addLiveIn(I->first); 256} 257 258#ifndef NDEBUG 259void MachineRegisterInfo::dumpUses(unsigned Reg) const { 260 for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) 261 I.getOperand().getParent()->dump(); 262} 263#endif 264