MachineRegisterInfo.cpp revision f734f3770ccecf3696a51bef51941cee318e8986 
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implementation of the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15#include "llvm/CodeGen/MachineInstrBuilder.h"
16#include "llvm/Target/TargetInstrInfo.h"
17#include "llvm/Support/CommandLine.h"
18using namespace llvm;
19
20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
21  VRegInfo.reserve(256);
22  RegAllocHints.reserve(256);
23  RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1.
24  UsedPhysRegs.resize(TRI.getNumRegs());
25
26  // Create the physreg use/def lists.
27  PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28  memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
29}
30
31MachineRegisterInfo::~MachineRegisterInfo() {
32#ifndef NDEBUG
33  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
34    assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
35  for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36    assert(!PhysRegUseDefLists[i] &&
37           "PhysRegUseDefLists has entries after all instructions are deleted");
38#endif
39  delete [] PhysRegUseDefLists;
40}
41
42/// setRegClass - Set the register class of the specified virtual register.
43///
44void
45MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46  unsigned VR = Reg;
47  Reg -= TargetRegisterInfo::FirstVirtualRegister;
48  assert(Reg < VRegInfo.size() && "Invalid vreg!");
49  const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
50  VRegInfo[Reg].first = RC;
51
52  // Remove from old register class's vregs list. This may be slow but
53  // fortunately this operation is rarely needed.
54  std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
55  std::vector<unsigned>::iterator I=std::find(VRegs.begin(), VRegs.end(), VR);
56  VRegs.erase(I);
57
58  // Add to new register class's vregs list.
59  RegClass2VRegMap[RC->getID()].push_back(VR);
60}
61
62/// createVirtualRegister - Create and return a new virtual register in the
63/// function with the specified register class.
64///
65unsigned
66MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
67  assert(RegClass && "Cannot create register without RegClass!");
68  // Add a reg, but keep track of whether the vector reallocated or not.
69  void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
70  VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
71  RegAllocHints.push_back(std::make_pair(0, 0));
72
73  if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
74    // The vector reallocated, handle this now.
75    HandleVRegListReallocation();
76  unsigned VR = getLastVirtReg();
77  RegClass2VRegMap[RegClass->getID()].push_back(VR);
78  return VR;
79}
80
81/// HandleVRegListReallocation - We just added a virtual register to the
82/// VRegInfo info list and it reallocated.  Update the use/def lists info
83/// pointers.
84void MachineRegisterInfo::HandleVRegListReallocation() {
85  // The back pointers for the vreg lists point into the previous vector.
86  // Update them to point to their correct slots.
87  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
88    MachineOperand *List = VRegInfo[i].second;
89    if (!List) continue;
90    // Update the back-pointer to be accurate once more.
91    List->Contents.Reg.Prev = &VRegInfo[i].second;
92  }
93}
94
95/// replaceRegWith - Replace all instances of FromReg with ToReg in the
96/// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
97/// except that it also changes any definitions of the register as well.
98void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
99  assert(FromReg != ToReg && "Cannot replace a reg with itself");
100
101  // TODO: This could be more efficient by bulk changing the operands.
102  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
103    MachineOperand &O = I.getOperand();
104    ++I;
105    O.setReg(ToReg);
106  }
107}
108
109
110/// getVRegDef - Return the machine instr that defines the specified virtual
111/// register or null if none is found.  This assumes that the code is in SSA
112/// form, so there should only be one definition.
113MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
114  assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
115         "Invalid vreg!");
116  // Since we are in SSA form, we can use the first definition.
117  if (!def_empty(Reg))
118    return &*def_begin(Reg);
119  return 0;
120}
121
122bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
123  use_iterator UI = use_begin(RegNo);
124  if (UI == use_end())
125    return false;
126  return ++UI == use_end();
127}
128
129bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
130  use_nodbg_iterator UI = use_nodbg_begin(RegNo);
131  if (UI == use_nodbg_end())
132    return false;
133  return ++UI == use_nodbg_end();
134}
135
136bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
137  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
138    if (I->first == Reg || I->second == Reg)
139      return true;
140  return false;
141}
142
143bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
144  for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
145    if (*I == Reg)
146      return true;
147  return false;
148}
149
150static cl::opt<bool>
151SchedLiveInCopies("schedule-livein-copies", cl::Hidden,
152                  cl::desc("Schedule copies of livein registers"),
153                  cl::init(false));
154
155/// EmitLiveInCopy - Emit a copy for a live in physical register. If the
156/// physical register has only a single copy use, then coalesced the copy
157/// if possible.
158static void EmitLiveInCopy(MachineBasicBlock *MBB,
159                           MachineBasicBlock::iterator &InsertPos,
160                           unsigned VirtReg, unsigned PhysReg,
161                           const TargetRegisterClass *RC,
162                           DenseMap<MachineInstr*, unsigned> &CopyRegMap,
163                           const MachineRegisterInfo &MRI,
164                           const TargetRegisterInfo &TRI,
165                           const TargetInstrInfo &TII) {
166  unsigned NumUses = 0;
167  MachineInstr *UseMI = NULL;
168  for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
169         UE = MRI.use_end(); UI != UE; ++UI) {
170    UseMI = &*UI;
171    if (++NumUses > 1)
172      break;
173  }
174
175  // If the number of uses is not one, or the use is not a move instruction,
176  // don't coalesce. Also, only coalesce away a virtual register to virtual
177  // register copy.
178  bool Coalesced = false;
179  unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
180  if (NumUses == 1 &&
181      TII.isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
182      TargetRegisterInfo::isVirtualRegister(DstReg)) {
183    VirtReg = DstReg;
184    Coalesced = true;
185  }
186
187  // Now find an ideal location to insert the copy.
188  MachineBasicBlock::iterator Pos = InsertPos;
189  while (Pos != MBB->begin()) {
190    MachineInstr *PrevMI = prior(Pos);
191    DenseMap<MachineInstr*, unsigned>::iterator RI = CopyRegMap.find(PrevMI);
192    // copyRegToReg might emit multiple instructions to do a copy.
193    unsigned CopyDstReg = (RI == CopyRegMap.end()) ? 0 : RI->second;
194    if (CopyDstReg && !TRI.regsOverlap(CopyDstReg, PhysReg))
195      // This is what the BB looks like right now:
196      // r1024 = mov r0
197      // ...
198      // r1    = mov r1024
199      //
200      // We want to insert "r1025 = mov r1". Inserting this copy below the
201      // move to r1024 makes it impossible for that move to be coalesced.
202      //
203      // r1025 = mov r1
204      // r1024 = mov r0
205      // ...
206      // r1    = mov 1024
207      // r2    = mov 1025
208      break; // Woot! Found a good location.
209    --Pos;
210  }
211
212  bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
213  assert(Emitted && "Unable to issue a live-in copy instruction!\n");
214  (void) Emitted;
215
216  CopyRegMap.insert(std::make_pair(prior(Pos), VirtReg));
217  if (Coalesced) {
218    if (&*InsertPos == UseMI) ++InsertPos;
219    MBB->erase(UseMI);
220  }
221}
222
223/// InsertLiveInDbgValue - Insert a DBG_VALUE instruction for each live-in
224/// register that has a corresponding source information metadata. e.g.
225/// function parameters.
226static void InsertLiveInDbgValue(MachineBasicBlock *MBB,
227                                 MachineBasicBlock::iterator InsertPos,
228                                 unsigned LiveInReg, unsigned VirtReg,
229                                 const MachineRegisterInfo &MRI,
230                                 const TargetInstrInfo &TII) {
231  for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(VirtReg),
232         UE = MRI.use_end(); UI != UE; ++UI) {
233    MachineInstr *UseMI = &*UI;
234    if (!UseMI->isDebugValue() || UseMI->getParent() != MBB)
235      continue;
236    // Found local dbg_value. FIXME: Verify it's not possible to have multiple
237    // dbg_value's which reference the vr in the same mbb.
238    uint64_t Offset = UseMI->getOperand(1).getImm();
239    const MDNode *MDPtr = UseMI->getOperand(2).getMetadata();
240    BuildMI(*MBB, InsertPos, InsertPos->getDebugLoc(),
241            TII.get(TargetOpcode::DBG_VALUE))
242      .addReg(LiveInReg).addImm(Offset).addMetadata(MDPtr);
243    return;
244  }
245}
246
247/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
248/// into the given entry block.
249void
250MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
251                                      const TargetRegisterInfo &TRI,
252                                      const TargetInstrInfo &TII) {
253  if (SchedLiveInCopies) {
254    // Emit the copies at a heuristically-determined location in the block.
255    DenseMap<MachineInstr*, unsigned> CopyRegMap;
256    MachineBasicBlock::iterator InsertPos = EntryMBB->begin();
257    for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
258           E = livein_end(); LI != E; ++LI)
259      if (LI->second) {
260        const TargetRegisterClass *RC = getRegClass(LI->second);
261        EmitLiveInCopy(EntryMBB, InsertPos, LI->second, LI->first,
262                       RC, CopyRegMap, *this, TRI, TII);
263        InsertLiveInDbgValue(EntryMBB, InsertPos,
264                             LI->first, LI->second, *this, TII);
265      }
266  } else {
267    // Emit the copies into the top of the block.
268    for (MachineRegisterInfo::livein_iterator LI = livein_begin(),
269           E = livein_end(); LI != E; ++LI)
270      if (LI->second) {
271        const TargetRegisterClass *RC = getRegClass(LI->second);
272        bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
273                                        LI->second, LI->first, RC, RC);
274        assert(Emitted && "Unable to issue a live-in copy instruction!\n");
275        (void) Emitted;
276        InsertLiveInDbgValue(EntryMBB, EntryMBB->begin(),
277                             LI->first, LI->second, *this, TII);
278      }
279  }
280
281  // Add function live-ins to entry block live-in set.
282  for (MachineRegisterInfo::livein_iterator I = livein_begin(),
283       E = livein_end(); I != E; ++I)
284    EntryMBB->addLiveIn(I->first);
285}
286
287#ifndef NDEBUG
288void MachineRegisterInfo::dumpUses(unsigned Reg) const {
289  for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
290    I.getOperand().getParent()->dump();
291}
292#endif
293