MachineRegisterInfo.cpp revision fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cd 
1//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Implementation of the MachineRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineRegisterInfo.h"
15#include "llvm/CodeGen/MachineInstrBuilder.h"
16#include "llvm/Target/TargetInstrInfo.h"
17#include "llvm/Support/CommandLine.h"
18using namespace llvm;
19
20MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) {
21  VRegInfo.reserve(256);
22  RegAllocHints.reserve(256);
23  RegClass2VRegMap = new std::vector<unsigned>[TRI.getNumRegClasses()];
24  UsedPhysRegs.resize(TRI.getNumRegs());
25
26  // Create the physreg use/def lists.
27  PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
28  memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
29}
30
31MachineRegisterInfo::~MachineRegisterInfo() {
32#ifndef NDEBUG
33  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
34    assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
35  for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
36    assert(!PhysRegUseDefLists[i] &&
37           "PhysRegUseDefLists has entries after all instructions are deleted");
38#endif
39  delete [] PhysRegUseDefLists;
40  delete [] RegClass2VRegMap;
41}
42
43/// setRegClass - Set the register class of the specified virtual register.
44///
45void
46MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47  unsigned VR = Reg;
48  Reg -= TargetRegisterInfo::FirstVirtualRegister;
49  assert(Reg < VRegInfo.size() && "Invalid vreg!");
50  const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
51  VRegInfo[Reg].first = RC;
52
53  // Remove from old register class's vregs list. This may be slow but
54  // fortunately this operation is rarely needed.
55  std::vector<unsigned> &VRegs = RegClass2VRegMap[OldRC->getID()];
56  std::vector<unsigned>::iterator I = std::find(VRegs.begin(), VRegs.end(), VR);
57  VRegs.erase(I);
58
59  // Add to new register class's vregs list.
60  RegClass2VRegMap[RC->getID()].push_back(VR);
61}
62
63/// createVirtualRegister - Create and return a new virtual register in the
64/// function with the specified register class.
65///
66unsigned
67MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
68  assert(RegClass && "Cannot create register without RegClass!");
69  // Add a reg, but keep track of whether the vector reallocated or not.
70  void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
71  VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
72  RegAllocHints.push_back(std::make_pair(0, 0));
73
74  if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
75    // The vector reallocated, handle this now.
76    HandleVRegListReallocation();
77  unsigned VR = getLastVirtReg();
78  RegClass2VRegMap[RegClass->getID()].push_back(VR);
79  return VR;
80}
81
82/// HandleVRegListReallocation - We just added a virtual register to the
83/// VRegInfo info list and it reallocated.  Update the use/def lists info
84/// pointers.
85void MachineRegisterInfo::HandleVRegListReallocation() {
86  // The back pointers for the vreg lists point into the previous vector.
87  // Update them to point to their correct slots.
88  for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
89    MachineOperand *List = VRegInfo[i].second;
90    if (!List) continue;
91    // Update the back-pointer to be accurate once more.
92    List->Contents.Reg.Prev = &VRegInfo[i].second;
93  }
94}
95
96/// replaceRegWith - Replace all instances of FromReg with ToReg in the
97/// machine function.  This is like llvm-level X->replaceAllUsesWith(Y),
98/// except that it also changes any definitions of the register as well.
99void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
100  assert(FromReg != ToReg && "Cannot replace a reg with itself");
101
102  // TODO: This could be more efficient by bulk changing the operands.
103  for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
104    MachineOperand &O = I.getOperand();
105    ++I;
106    O.setReg(ToReg);
107  }
108}
109
110
111/// getVRegDef - Return the machine instr that defines the specified virtual
112/// register or null if none is found.  This assumes that the code is in SSA
113/// form, so there should only be one definition.
114MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
115  assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
116         "Invalid vreg!");
117  // Since we are in SSA form, we can use the first definition.
118  if (!def_empty(Reg))
119    return &*def_begin(Reg);
120  return 0;
121}
122
123bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const {
124  use_iterator UI = use_begin(RegNo);
125  if (UI == use_end())
126    return false;
127  return ++UI == use_end();
128}
129
130bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
131  use_nodbg_iterator UI = use_nodbg_begin(RegNo);
132  if (UI == use_nodbg_end())
133    return false;
134  return ++UI == use_nodbg_end();
135}
136
137/// clearKillFlags - Iterate over all the uses of the given register and
138/// clear the kill flag from the MachineOperand. This function is used by
139/// optimization passes which extend register lifetimes and need only
140/// preserve conservative kill flag information.
141void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
142  for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI)
143    UI.getOperand().setIsKill(false);
144}
145
146bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
147  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
148    if (I->first == Reg || I->second == Reg)
149      return true;
150  return false;
151}
152
153bool MachineRegisterInfo::isLiveOut(unsigned Reg) const {
154  for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
155    if (*I == Reg)
156      return true;
157  return false;
158}
159
160/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
161/// corresponding live-in physical register.
162unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
163  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
164    if (I->second == VReg)
165      return I->first;
166  return 0;
167}
168
169/// getLiveInVirtReg - If PReg is a live-in physical register, return the
170/// corresponding live-in physical register.
171unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
172  for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
173    if (I->first == PReg)
174      return I->second;
175  return 0;
176}
177
178/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
179/// into the given entry block.
180void
181MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
182                                      const TargetRegisterInfo &TRI,
183                                      const TargetInstrInfo &TII) {
184  // Emit the copies into the top of the block.
185  for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
186    if (LiveIns[i].second) {
187      if (use_empty(LiveIns[i].second)) {
188        // The livein has no uses. Drop it.
189        //
190        // It would be preferable to have isel avoid creating live-in
191        // records for unused arguments in the first place, but it's
192        // complicated by the debug info code for arguments.
193        LiveIns.erase(LiveIns.begin() + i);
194        --i; --e;
195      } else {
196        // Emit a copy.
197        const TargetRegisterClass *RC = getRegClass(LiveIns[i].second);
198        bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
199                                        LiveIns[i].second, LiveIns[i].first,
200                                        RC, RC, DebugLoc());
201        assert(Emitted && "Unable to issue a live-in copy instruction!\n");
202        (void) Emitted;
203
204        // Add the register to the entry block live-in set.
205        EntryMBB->addLiveIn(LiveIns[i].first);
206      }
207    } else {
208      // Add the register to the entry block live-in set.
209      EntryMBB->addLiveIn(LiveIns[i].first);
210    }
211}
212
213void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) {
214  for (int i = UsedPhysRegs.find_first(); i >= 0;
215       i = UsedPhysRegs.find_next(i))
216         for (const unsigned *SS = TRI.getSubRegisters(i);
217              unsigned SubReg = *SS; ++SS)
218           if (SubReg > unsigned(i))
219             UsedPhysRegs.set(SubReg);
220}
221
222#ifndef NDEBUG
223void MachineRegisterInfo::dumpUses(unsigned Reg) const {
224  for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I)
225    I.getOperand().getParent()->dump();
226}
227#endif
228