MachineScheduler.cpp revision 3bf23304ee80946409626cf64282a76c13a44352
1//===- MachineScheduler.cpp - Machine Instruction Scheduler ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// MachineScheduler schedules machine instructions after phi elimination. It 11// preserves LiveIntervals so it can be invoked before register allocation. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "misched" 16 17#include "llvm/CodeGen/MachineScheduler.h" 18#include "llvm/ADT/OwningPtr.h" 19#include "llvm/ADT/PriorityQueue.h" 20#include "llvm/Analysis/AliasAnalysis.h" 21#include "llvm/CodeGen/LiveIntervalAnalysis.h" 22#include "llvm/CodeGen/MachineDominators.h" 23#include "llvm/CodeGen/MachineLoopInfo.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/Passes.h" 26#include "llvm/CodeGen/RegisterClassInfo.h" 27#include "llvm/CodeGen/ScheduleDFS.h" 28#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/GraphWriter.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetInstrInfo.h" 35#include <queue> 36 37using namespace llvm; 38 39namespace llvm { 40cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden, 41 cl::desc("Force top-down list scheduling")); 42cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden, 43 cl::desc("Force bottom-up list scheduling")); 44} 45 46#ifndef NDEBUG 47static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden, 48 cl::desc("Pop up a window to show MISched dags after they are processed")); 49 50static cl::opt<unsigned> MISchedCutoff("misched-cutoff", cl::Hidden, 51 cl::desc("Stop scheduling after N instructions"), cl::init(~0U)); 52#else 53static bool ViewMISchedDAGs = false; 54#endif // NDEBUG 55 56static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden, 57 cl::desc("Enable load clustering."), cl::init(true)); 58 59// Experimental heuristics 60static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden, 61 cl::desc("Enable scheduling for macro fusion."), cl::init(true)); 62 63static cl::opt<bool> VerifyScheduling("verify-misched", cl::Hidden, 64 cl::desc("Verify machine instrs before and after machine scheduling")); 65 66// DAG subtrees must have at least this many nodes. 67static const unsigned MinSubtreeSize = 8; 68 69//===----------------------------------------------------------------------===// 70// Machine Instruction Scheduling Pass and Registry 71//===----------------------------------------------------------------------===// 72 73MachineSchedContext::MachineSchedContext(): 74 MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) { 75 RegClassInfo = new RegisterClassInfo(); 76} 77 78MachineSchedContext::~MachineSchedContext() { 79 delete RegClassInfo; 80} 81 82namespace { 83/// MachineScheduler runs after coalescing and before register allocation. 84class MachineScheduler : public MachineSchedContext, 85 public MachineFunctionPass { 86public: 87 MachineScheduler(); 88 89 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 90 91 virtual void releaseMemory() {} 92 93 virtual bool runOnMachineFunction(MachineFunction&); 94 95 virtual void print(raw_ostream &O, const Module* = 0) const; 96 97 static char ID; // Class identification, replacement for typeinfo 98}; 99} // namespace 100 101char MachineScheduler::ID = 0; 102 103char &llvm::MachineSchedulerID = MachineScheduler::ID; 104 105INITIALIZE_PASS_BEGIN(MachineScheduler, "misched", 106 "Machine Instruction Scheduler", false, false) 107INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 108INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 109INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 110INITIALIZE_PASS_END(MachineScheduler, "misched", 111 "Machine Instruction Scheduler", false, false) 112 113MachineScheduler::MachineScheduler() 114: MachineFunctionPass(ID) { 115 initializeMachineSchedulerPass(*PassRegistry::getPassRegistry()); 116} 117 118void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { 119 AU.setPreservesCFG(); 120 AU.addRequiredID(MachineDominatorsID); 121 AU.addRequired<MachineLoopInfo>(); 122 AU.addRequired<AliasAnalysis>(); 123 AU.addRequired<TargetPassConfig>(); 124 AU.addRequired<SlotIndexes>(); 125 AU.addPreserved<SlotIndexes>(); 126 AU.addRequired<LiveIntervals>(); 127 AU.addPreserved<LiveIntervals>(); 128 MachineFunctionPass::getAnalysisUsage(AU); 129} 130 131MachinePassRegistry MachineSchedRegistry::Registry; 132 133/// A dummy default scheduler factory indicates whether the scheduler 134/// is overridden on the command line. 135static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) { 136 return 0; 137} 138 139/// MachineSchedOpt allows command line selection of the scheduler. 140static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false, 141 RegisterPassParser<MachineSchedRegistry> > 142MachineSchedOpt("misched", 143 cl::init(&useDefaultMachineSched), cl::Hidden, 144 cl::desc("Machine instruction scheduler to use")); 145 146static MachineSchedRegistry 147DefaultSchedRegistry("default", "Use the target's default scheduler choice.", 148 useDefaultMachineSched); 149 150/// Forward declare the standard machine scheduler. This will be used as the 151/// default scheduler if the target does not set a default. 152static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C); 153 154 155/// Decrement this iterator until reaching the top or a non-debug instr. 156static MachineBasicBlock::iterator 157priorNonDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator Beg) { 158 assert(I != Beg && "reached the top of the region, cannot decrement"); 159 while (--I != Beg) { 160 if (!I->isDebugValue()) 161 break; 162 } 163 return I; 164} 165 166/// If this iterator is a debug value, increment until reaching the End or a 167/// non-debug instruction. 168static MachineBasicBlock::iterator 169nextIfDebug(MachineBasicBlock::iterator I, MachineBasicBlock::iterator End) { 170 for(; I != End; ++I) { 171 if (!I->isDebugValue()) 172 break; 173 } 174 return I; 175} 176 177/// Top-level MachineScheduler pass driver. 178/// 179/// Visit blocks in function order. Divide each block into scheduling regions 180/// and visit them bottom-up. Visiting regions bottom-up is not required, but is 181/// consistent with the DAG builder, which traverses the interior of the 182/// scheduling regions bottom-up. 183/// 184/// This design avoids exposing scheduling boundaries to the DAG builder, 185/// simplifying the DAG builder's support for "special" target instructions. 186/// At the same time the design allows target schedulers to operate across 187/// scheduling boundaries, for example to bundle the boudary instructions 188/// without reordering them. This creates complexity, because the target 189/// scheduler must update the RegionBegin and RegionEnd positions cached by 190/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler 191/// design would be to split blocks at scheduling boundaries, but LLVM has a 192/// general bias against block splitting purely for implementation simplicity. 193bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { 194 DEBUG(dbgs() << "Before MISsched:\n"; mf.print(dbgs())); 195 196 // Initialize the context of the pass. 197 MF = &mf; 198 MLI = &getAnalysis<MachineLoopInfo>(); 199 MDT = &getAnalysis<MachineDominatorTree>(); 200 PassConfig = &getAnalysis<TargetPassConfig>(); 201 AA = &getAnalysis<AliasAnalysis>(); 202 203 LIS = &getAnalysis<LiveIntervals>(); 204 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 205 206 if (VerifyScheduling) { 207 DEBUG(LIS->print(dbgs())); 208 MF->verify(this, "Before machine scheduling."); 209 } 210 RegClassInfo->runOnMachineFunction(*MF); 211 212 // Select the scheduler, or set the default. 213 MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt; 214 if (Ctor == useDefaultMachineSched) { 215 // Get the default scheduler set by the target. 216 Ctor = MachineSchedRegistry::getDefault(); 217 if (!Ctor) { 218 Ctor = createConvergingSched; 219 MachineSchedRegistry::setDefault(Ctor); 220 } 221 } 222 // Instantiate the selected scheduler. 223 OwningPtr<ScheduleDAGInstrs> Scheduler(Ctor(this)); 224 225 // Visit all machine basic blocks. 226 // 227 // TODO: Visit blocks in global postorder or postorder within the bottom-up 228 // loop tree. Then we can optionally compute global RegPressure. 229 for (MachineFunction::iterator MBB = MF->begin(), MBBEnd = MF->end(); 230 MBB != MBBEnd; ++MBB) { 231 232 Scheduler->startBlock(MBB); 233 234 // Break the block into scheduling regions [I, RegionEnd), and schedule each 235 // region as soon as it is discovered. RegionEnd points the scheduling 236 // boundary at the bottom of the region. The DAG does not include RegionEnd, 237 // but the region does (i.e. the next RegionEnd is above the previous 238 // RegionBegin). If the current block has no terminator then RegionEnd == 239 // MBB->end() for the bottom region. 240 // 241 // The Scheduler may insert instructions during either schedule() or 242 // exitRegion(), even for empty regions. So the local iterators 'I' and 243 // 'RegionEnd' are invalid across these calls. 244 unsigned RemainingInstrs = MBB->size(); 245 for(MachineBasicBlock::iterator RegionEnd = MBB->end(); 246 RegionEnd != MBB->begin(); RegionEnd = Scheduler->begin()) { 247 248 // Avoid decrementing RegionEnd for blocks with no terminator. 249 if (RegionEnd != MBB->end() 250 || TII->isSchedulingBoundary(llvm::prior(RegionEnd), MBB, *MF)) { 251 --RegionEnd; 252 // Count the boundary instruction. 253 --RemainingInstrs; 254 } 255 256 // The next region starts above the previous region. Look backward in the 257 // instruction stream until we find the nearest boundary. 258 MachineBasicBlock::iterator I = RegionEnd; 259 for(;I != MBB->begin(); --I, --RemainingInstrs) { 260 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, *MF)) 261 break; 262 } 263 // Notify the scheduler of the region, even if we may skip scheduling 264 // it. Perhaps it still needs to be bundled. 265 Scheduler->enterRegion(MBB, I, RegionEnd, RemainingInstrs); 266 267 // Skip empty scheduling regions (0 or 1 schedulable instructions). 268 if (I == RegionEnd || I == llvm::prior(RegionEnd)) { 269 // Close the current region. Bundle the terminator if needed. 270 // This invalidates 'RegionEnd' and 'I'. 271 Scheduler->exitRegion(); 272 continue; 273 } 274 DEBUG(dbgs() << "********** MI Scheduling **********\n"); 275 DEBUG(dbgs() << MF->getName() 276 << ":BB#" << MBB->getNumber() << " " << MBB->getName() 277 << "\n From: " << *I << " To: "; 278 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd; 279 else dbgs() << "End"; 280 dbgs() << " Remaining: " << RemainingInstrs << "\n"); 281 282 // Schedule a region: possibly reorder instructions. 283 // This invalidates 'RegionEnd' and 'I'. 284 Scheduler->schedule(); 285 286 // Close the current region. 287 Scheduler->exitRegion(); 288 289 // Scheduling has invalidated the current iterator 'I'. Ask the 290 // scheduler for the top of it's scheduled region. 291 RegionEnd = Scheduler->begin(); 292 } 293 assert(RemainingInstrs == 0 && "Instruction count mismatch!"); 294 Scheduler->finishBlock(); 295 } 296 Scheduler->finalizeSchedule(); 297 DEBUG(LIS->print(dbgs())); 298 if (VerifyScheduling) 299 MF->verify(this, "After machine scheduling."); 300 return true; 301} 302 303void MachineScheduler::print(raw_ostream &O, const Module* m) const { 304 // unimplemented 305} 306 307#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 308void ReadyQueue::dump() { 309 dbgs() << Name << ": "; 310 for (unsigned i = 0, e = Queue.size(); i < e; ++i) 311 dbgs() << Queue[i]->NodeNum << " "; 312 dbgs() << "\n"; 313} 314#endif 315 316//===----------------------------------------------------------------------===// 317// ScheduleDAGMI - Base class for MachineInstr scheduling with LiveIntervals 318// preservation. 319//===----------------------------------------------------------------------===// 320 321ScheduleDAGMI::~ScheduleDAGMI() { 322 delete DFSResult; 323 DeleteContainerPointers(Mutations); 324 delete SchedImpl; 325} 326 327bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) { 328 return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU); 329} 330 331bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) { 332 if (SuccSU != &ExitSU) { 333 // Do not use WillCreateCycle, it assumes SD scheduling. 334 // If Pred is reachable from Succ, then the edge creates a cycle. 335 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU)) 336 return false; 337 Topo.AddPred(SuccSU, PredDep.getSUnit()); 338 } 339 SuccSU->addPred(PredDep, /*Required=*/!PredDep.isArtificial()); 340 // Return true regardless of whether a new edge needed to be inserted. 341 return true; 342} 343 344/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. When 345/// NumPredsLeft reaches zero, release the successor node. 346/// 347/// FIXME: Adjust SuccSU height based on MinLatency. 348void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { 349 SUnit *SuccSU = SuccEdge->getSUnit(); 350 351 if (SuccEdge->isWeak()) { 352 --SuccSU->WeakPredsLeft; 353 if (SuccEdge->isCluster()) 354 NextClusterSucc = SuccSU; 355 return; 356 } 357#ifndef NDEBUG 358 if (SuccSU->NumPredsLeft == 0) { 359 dbgs() << "*** Scheduling failed! ***\n"; 360 SuccSU->dump(this); 361 dbgs() << " has been released too many times!\n"; 362 llvm_unreachable(0); 363 } 364#endif 365 --SuccSU->NumPredsLeft; 366 if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU) 367 SchedImpl->releaseTopNode(SuccSU); 368} 369 370/// releaseSuccessors - Call releaseSucc on each of SU's successors. 371void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { 372 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 373 I != E; ++I) { 374 releaseSucc(SU, &*I); 375 } 376} 377 378/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When 379/// NumSuccsLeft reaches zero, release the predecessor node. 380/// 381/// FIXME: Adjust PredSU height based on MinLatency. 382void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { 383 SUnit *PredSU = PredEdge->getSUnit(); 384 385 if (PredEdge->isWeak()) { 386 --PredSU->WeakSuccsLeft; 387 if (PredEdge->isCluster()) 388 NextClusterPred = PredSU; 389 return; 390 } 391#ifndef NDEBUG 392 if (PredSU->NumSuccsLeft == 0) { 393 dbgs() << "*** Scheduling failed! ***\n"; 394 PredSU->dump(this); 395 dbgs() << " has been released too many times!\n"; 396 llvm_unreachable(0); 397 } 398#endif 399 --PredSU->NumSuccsLeft; 400 if (PredSU->NumSuccsLeft == 0 && PredSU != &EntrySU) 401 SchedImpl->releaseBottomNode(PredSU); 402} 403 404/// releasePredecessors - Call releasePred on each of SU's predecessors. 405void ScheduleDAGMI::releasePredecessors(SUnit *SU) { 406 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 407 I != E; ++I) { 408 releasePred(SU, &*I); 409 } 410} 411 412/// This is normally called from the main scheduler loop but may also be invoked 413/// by the scheduling strategy to perform additional code motion. 414void ScheduleDAGMI::moveInstruction(MachineInstr *MI, 415 MachineBasicBlock::iterator InsertPos) { 416 // Advance RegionBegin if the first instruction moves down. 417 if (&*RegionBegin == MI) 418 ++RegionBegin; 419 420 // Update the instruction stream. 421 BB->splice(InsertPos, BB, MI); 422 423 // Update LiveIntervals 424 LIS->handleMove(MI, /*UpdateFlags=*/true); 425 426 // Recede RegionBegin if an instruction moves above the first. 427 if (RegionBegin == InsertPos) 428 RegionBegin = MI; 429} 430 431bool ScheduleDAGMI::checkSchedLimit() { 432#ifndef NDEBUG 433 if (NumInstrsScheduled == MISchedCutoff && MISchedCutoff != ~0U) { 434 CurrentTop = CurrentBottom; 435 return false; 436 } 437 ++NumInstrsScheduled; 438#endif 439 return true; 440} 441 442/// enterRegion - Called back from MachineScheduler::runOnMachineFunction after 443/// crossing a scheduling boundary. [begin, end) includes all instructions in 444/// the region, including the boundary itself and single-instruction regions 445/// that don't get scheduled. 446void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb, 447 MachineBasicBlock::iterator begin, 448 MachineBasicBlock::iterator end, 449 unsigned endcount) 450{ 451 ScheduleDAGInstrs::enterRegion(bb, begin, end, endcount); 452 453 // For convenience remember the end of the liveness region. 454 LiveRegionEnd = 455 (RegionEnd == bb->end()) ? RegionEnd : llvm::next(RegionEnd); 456} 457 458// Setup the register pressure trackers for the top scheduled top and bottom 459// scheduled regions. 460void ScheduleDAGMI::initRegPressure() { 461 TopRPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin); 462 BotRPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd); 463 464 // Close the RPTracker to finalize live ins. 465 RPTracker.closeRegion(); 466 467 DEBUG(RPTracker.getPressure().dump(TRI)); 468 469 // Initialize the live ins and live outs. 470 TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs); 471 BotRPTracker.addLiveRegs(RPTracker.getPressure().LiveOutRegs); 472 473 // Close one end of the tracker so we can call 474 // getMaxUpward/DownwardPressureDelta before advancing across any 475 // instructions. This converts currently live regs into live ins/outs. 476 TopRPTracker.closeTop(); 477 BotRPTracker.closeBottom(); 478 479 // Account for liveness generated by the region boundary. 480 if (LiveRegionEnd != RegionEnd) 481 BotRPTracker.recede(); 482 483 assert(BotRPTracker.getPos() == RegionEnd && "Can't find the region bottom"); 484 485 // Cache the list of excess pressure sets in this region. This will also track 486 // the max pressure in the scheduled code for these sets. 487 RegionCriticalPSets.clear(); 488 const std::vector<unsigned> &RegionPressure = 489 RPTracker.getPressure().MaxSetPressure; 490 for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) { 491 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); 492 if (RegionPressure[i] > Limit) { 493 DEBUG(dbgs() << TRI->getRegPressureSetName(i) 494 << " Limit " << Limit 495 << " Actual " << RegionPressure[i] << "\n"); 496 RegionCriticalPSets.push_back(PressureElement(i, 0)); 497 } 498 } 499 DEBUG(dbgs() << "Excess PSets: "; 500 for (unsigned i = 0, e = RegionCriticalPSets.size(); i != e; ++i) 501 dbgs() << TRI->getRegPressureSetName( 502 RegionCriticalPSets[i].PSetID) << " "; 503 dbgs() << "\n"); 504} 505 506// FIXME: When the pressure tracker deals in pressure differences then we won't 507// iterate over all RegionCriticalPSets[i]. 508void ScheduleDAGMI:: 509updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure) { 510 for (unsigned i = 0, e = RegionCriticalPSets.size(); i < e; ++i) { 511 unsigned ID = RegionCriticalPSets[i].PSetID; 512 int &MaxUnits = RegionCriticalPSets[i].UnitIncrease; 513 if ((int)NewMaxPressure[ID] > MaxUnits) 514 MaxUnits = NewMaxPressure[ID]; 515 } 516 DEBUG( 517 for (unsigned i = 0, e = NewMaxPressure.size(); i < e; ++i) { 518 unsigned Limit = RegClassInfo->getRegPressureSetLimit(i); 519 if (NewMaxPressure[i] > Limit ) { 520 dbgs() << " " << TRI->getRegPressureSetName(i) << ": " 521 << NewMaxPressure[i] << " > " << Limit << "\n"; 522 } 523 }); 524} 525 526/// schedule - Called back from MachineScheduler::runOnMachineFunction 527/// after setting up the current scheduling region. [RegionBegin, RegionEnd) 528/// only includes instructions that have DAG nodes, not scheduling boundaries. 529/// 530/// This is a skeletal driver, with all the functionality pushed into helpers, 531/// so that it can be easilly extended by experimental schedulers. Generally, 532/// implementing MachineSchedStrategy should be sufficient to implement a new 533/// scheduling algorithm. However, if a scheduler further subclasses 534/// ScheduleDAGMI then it will want to override this virtual method in order to 535/// update any specialized state. 536void ScheduleDAGMI::schedule() { 537 buildDAGWithRegPressure(); 538 539 Topo.InitDAGTopologicalSorting(); 540 541 postprocessDAG(); 542 543 SmallVector<SUnit*, 8> TopRoots, BotRoots; 544 findRootsAndBiasEdges(TopRoots, BotRoots); 545 546 // Initialize the strategy before modifying the DAG. 547 // This may initialize a DFSResult to be used for queue priority. 548 SchedImpl->initialize(this); 549 550 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) 551 SUnits[su].dumpAll(this)); 552 if (ViewMISchedDAGs) viewGraph(); 553 554 // Initialize ready queues now that the DAG and priority data are finalized. 555 initQueues(TopRoots, BotRoots); 556 557 bool IsTopNode = false; 558 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) { 559 assert(!SU->isScheduled && "Node already scheduled"); 560 if (!checkSchedLimit()) 561 break; 562 563 scheduleMI(SU, IsTopNode); 564 565 updateQueues(SU, IsTopNode); 566 } 567 assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone."); 568 569 placeDebugValues(); 570 571 DEBUG({ 572 unsigned BBNum = begin()->getParent()->getNumber(); 573 dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n"; 574 dumpSchedule(); 575 dbgs() << '\n'; 576 }); 577} 578 579/// Build the DAG and setup three register pressure trackers. 580void ScheduleDAGMI::buildDAGWithRegPressure() { 581 // Initialize the register pressure tracker used by buildSchedGraph. 582 RPTracker.init(&MF, RegClassInfo, LIS, BB, LiveRegionEnd); 583 584 // Account for liveness generate by the region boundary. 585 if (LiveRegionEnd != RegionEnd) 586 RPTracker.recede(); 587 588 // Build the DAG, and compute current register pressure. 589 buildSchedGraph(AA, &RPTracker); 590 591 // Initialize top/bottom trackers after computing region pressure. 592 initRegPressure(); 593} 594 595/// Apply each ScheduleDAGMutation step in order. 596void ScheduleDAGMI::postprocessDAG() { 597 for (unsigned i = 0, e = Mutations.size(); i < e; ++i) { 598 Mutations[i]->apply(this); 599 } 600} 601 602void ScheduleDAGMI::computeDFSResult() { 603 if (!DFSResult) 604 DFSResult = new SchedDFSResult(/*BottomU*/true, MinSubtreeSize); 605 DFSResult->clear(); 606 ScheduledTrees.clear(); 607 DFSResult->resize(SUnits.size()); 608 DFSResult->compute(SUnits); 609 ScheduledTrees.resize(DFSResult->getNumSubtrees()); 610} 611 612void ScheduleDAGMI::findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots, 613 SmallVectorImpl<SUnit*> &BotRoots) { 614 for (std::vector<SUnit>::iterator 615 I = SUnits.begin(), E = SUnits.end(); I != E; ++I) { 616 SUnit *SU = &(*I); 617 assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits"); 618 619 // Order predecessors so DFSResult follows the critical path. 620 SU->biasCriticalPath(); 621 622 // A SUnit is ready to top schedule if it has no predecessors. 623 if (!I->NumPredsLeft) 624 TopRoots.push_back(SU); 625 // A SUnit is ready to bottom schedule if it has no successors. 626 if (!I->NumSuccsLeft) 627 BotRoots.push_back(SU); 628 } 629 ExitSU.biasCriticalPath(); 630} 631 632/// Identify DAG roots and setup scheduler queues. 633void ScheduleDAGMI::initQueues(ArrayRef<SUnit*> TopRoots, 634 ArrayRef<SUnit*> BotRoots) { 635 NextClusterSucc = NULL; 636 NextClusterPred = NULL; 637 638 // Release all DAG roots for scheduling, not including EntrySU/ExitSU. 639 // 640 // Nodes with unreleased weak edges can still be roots. 641 // Release top roots in forward order. 642 for (SmallVectorImpl<SUnit*>::const_iterator 643 I = TopRoots.begin(), E = TopRoots.end(); I != E; ++I) { 644 SchedImpl->releaseTopNode(*I); 645 } 646 // Release bottom roots in reverse order so the higher priority nodes appear 647 // first. This is more natural and slightly more efficient. 648 for (SmallVectorImpl<SUnit*>::const_reverse_iterator 649 I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I) { 650 SchedImpl->releaseBottomNode(*I); 651 } 652 653 releaseSuccessors(&EntrySU); 654 releasePredecessors(&ExitSU); 655 656 SchedImpl->registerRoots(); 657 658 // Advance past initial DebugValues. 659 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"); 660 CurrentTop = nextIfDebug(RegionBegin, RegionEnd); 661 TopRPTracker.setPos(CurrentTop); 662 663 CurrentBottom = RegionEnd; 664} 665 666/// Move an instruction and update register pressure. 667void ScheduleDAGMI::scheduleMI(SUnit *SU, bool IsTopNode) { 668 // Move the instruction to its new location in the instruction stream. 669 MachineInstr *MI = SU->getInstr(); 670 671 if (IsTopNode) { 672 assert(SU->isTopReady() && "node still has unscheduled dependencies"); 673 if (&*CurrentTop == MI) 674 CurrentTop = nextIfDebug(++CurrentTop, CurrentBottom); 675 else { 676 moveInstruction(MI, CurrentTop); 677 TopRPTracker.setPos(MI); 678 } 679 680 // Update top scheduled pressure. 681 TopRPTracker.advance(); 682 assert(TopRPTracker.getPos() == CurrentTop && "out of sync"); 683 updateScheduledPressure(TopRPTracker.getPressure().MaxSetPressure); 684 } 685 else { 686 assert(SU->isBottomReady() && "node still has unscheduled dependencies"); 687 MachineBasicBlock::iterator priorII = 688 priorNonDebug(CurrentBottom, CurrentTop); 689 if (&*priorII == MI) 690 CurrentBottom = priorII; 691 else { 692 if (&*CurrentTop == MI) { 693 CurrentTop = nextIfDebug(++CurrentTop, priorII); 694 TopRPTracker.setPos(CurrentTop); 695 } 696 moveInstruction(MI, CurrentBottom); 697 CurrentBottom = MI; 698 } 699 // Update bottom scheduled pressure. 700 BotRPTracker.recede(); 701 assert(BotRPTracker.getPos() == CurrentBottom && "out of sync"); 702 updateScheduledPressure(BotRPTracker.getPressure().MaxSetPressure); 703 } 704} 705 706/// Update scheduler queues after scheduling an instruction. 707void ScheduleDAGMI::updateQueues(SUnit *SU, bool IsTopNode) { 708 // Release dependent instructions for scheduling. 709 if (IsTopNode) 710 releaseSuccessors(SU); 711 else 712 releasePredecessors(SU); 713 714 SU->isScheduled = true; 715 716 if (DFSResult) { 717 unsigned SubtreeID = DFSResult->getSubtreeID(SU); 718 if (!ScheduledTrees.test(SubtreeID)) { 719 ScheduledTrees.set(SubtreeID); 720 DFSResult->scheduleTree(SubtreeID); 721 SchedImpl->scheduleTree(SubtreeID); 722 } 723 } 724 725 // Notify the scheduling strategy after updating the DAG. 726 SchedImpl->schedNode(SU, IsTopNode); 727} 728 729/// Reinsert any remaining debug_values, just like the PostRA scheduler. 730void ScheduleDAGMI::placeDebugValues() { 731 // If first instruction was a DBG_VALUE then put it back. 732 if (FirstDbgValue) { 733 BB->splice(RegionBegin, BB, FirstDbgValue); 734 RegionBegin = FirstDbgValue; 735 } 736 737 for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator 738 DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) { 739 std::pair<MachineInstr *, MachineInstr *> P = *prior(DI); 740 MachineInstr *DbgValue = P.first; 741 MachineBasicBlock::iterator OrigPrevMI = P.second; 742 if (&*RegionBegin == DbgValue) 743 ++RegionBegin; 744 BB->splice(++OrigPrevMI, BB, DbgValue); 745 if (OrigPrevMI == llvm::prior(RegionEnd)) 746 RegionEnd = DbgValue; 747 } 748 DbgValues.clear(); 749 FirstDbgValue = NULL; 750} 751 752#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 753void ScheduleDAGMI::dumpSchedule() const { 754 for (MachineBasicBlock::iterator MI = begin(), ME = end(); MI != ME; ++MI) { 755 if (SUnit *SU = getSUnit(&(*MI))) 756 SU->dump(this); 757 else 758 dbgs() << "Missing SUnit\n"; 759 } 760} 761#endif 762 763//===----------------------------------------------------------------------===// 764// LoadClusterMutation - DAG post-processing to cluster loads. 765//===----------------------------------------------------------------------===// 766 767namespace { 768/// \brief Post-process the DAG to create cluster edges between neighboring 769/// loads. 770class LoadClusterMutation : public ScheduleDAGMutation { 771 struct LoadInfo { 772 SUnit *SU; 773 unsigned BaseReg; 774 unsigned Offset; 775 LoadInfo(SUnit *su, unsigned reg, unsigned ofs) 776 : SU(su), BaseReg(reg), Offset(ofs) {} 777 }; 778 static bool LoadInfoLess(const LoadClusterMutation::LoadInfo &LHS, 779 const LoadClusterMutation::LoadInfo &RHS); 780 781 const TargetInstrInfo *TII; 782 const TargetRegisterInfo *TRI; 783public: 784 LoadClusterMutation(const TargetInstrInfo *tii, 785 const TargetRegisterInfo *tri) 786 : TII(tii), TRI(tri) {} 787 788 virtual void apply(ScheduleDAGMI *DAG); 789protected: 790 void clusterNeighboringLoads(ArrayRef<SUnit*> Loads, ScheduleDAGMI *DAG); 791}; 792} // anonymous 793 794bool LoadClusterMutation::LoadInfoLess( 795 const LoadClusterMutation::LoadInfo &LHS, 796 const LoadClusterMutation::LoadInfo &RHS) { 797 if (LHS.BaseReg != RHS.BaseReg) 798 return LHS.BaseReg < RHS.BaseReg; 799 return LHS.Offset < RHS.Offset; 800} 801 802void LoadClusterMutation::clusterNeighboringLoads(ArrayRef<SUnit*> Loads, 803 ScheduleDAGMI *DAG) { 804 SmallVector<LoadClusterMutation::LoadInfo,32> LoadRecords; 805 for (unsigned Idx = 0, End = Loads.size(); Idx != End; ++Idx) { 806 SUnit *SU = Loads[Idx]; 807 unsigned BaseReg; 808 unsigned Offset; 809 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI)) 810 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset)); 811 } 812 if (LoadRecords.size() < 2) 813 return; 814 std::sort(LoadRecords.begin(), LoadRecords.end(), LoadInfoLess); 815 unsigned ClusterLength = 1; 816 for (unsigned Idx = 0, End = LoadRecords.size(); Idx < (End - 1); ++Idx) { 817 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) { 818 ClusterLength = 1; 819 continue; 820 } 821 822 SUnit *SUa = LoadRecords[Idx].SU; 823 SUnit *SUb = LoadRecords[Idx+1].SU; 824 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength) 825 && DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) { 826 827 DEBUG(dbgs() << "Cluster loads SU(" << SUa->NodeNum << ") - SU(" 828 << SUb->NodeNum << ")\n"); 829 // Copy successor edges from SUa to SUb. Interleaving computation 830 // dependent on SUa can prevent load combining due to register reuse. 831 // Predecessor edges do not need to be copied from SUb to SUa since nearby 832 // loads should have effectively the same inputs. 833 for (SUnit::const_succ_iterator 834 SI = SUa->Succs.begin(), SE = SUa->Succs.end(); SI != SE; ++SI) { 835 if (SI->getSUnit() == SUb) 836 continue; 837 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n"); 838 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial)); 839 } 840 ++ClusterLength; 841 } 842 else 843 ClusterLength = 1; 844 } 845} 846 847/// \brief Callback from DAG postProcessing to create cluster edges for loads. 848void LoadClusterMutation::apply(ScheduleDAGMI *DAG) { 849 // Map DAG NodeNum to store chain ID. 850 DenseMap<unsigned, unsigned> StoreChainIDs; 851 // Map each store chain to a set of dependent loads. 852 SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents; 853 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) { 854 SUnit *SU = &DAG->SUnits[Idx]; 855 if (!SU->getInstr()->mayLoad()) 856 continue; 857 unsigned ChainPredID = DAG->SUnits.size(); 858 for (SUnit::const_pred_iterator 859 PI = SU->Preds.begin(), PE = SU->Preds.end(); PI != PE; ++PI) { 860 if (PI->isCtrl()) { 861 ChainPredID = PI->getSUnit()->NodeNum; 862 break; 863 } 864 } 865 // Check if this chain-like pred has been seen 866 // before. ChainPredID==MaxNodeID for loads at the top of the schedule. 867 unsigned NumChains = StoreChainDependents.size(); 868 std::pair<DenseMap<unsigned, unsigned>::iterator, bool> Result = 869 StoreChainIDs.insert(std::make_pair(ChainPredID, NumChains)); 870 if (Result.second) 871 StoreChainDependents.resize(NumChains + 1); 872 StoreChainDependents[Result.first->second].push_back(SU); 873 } 874 // Iterate over the store chains. 875 for (unsigned Idx = 0, End = StoreChainDependents.size(); Idx != End; ++Idx) 876 clusterNeighboringLoads(StoreChainDependents[Idx], DAG); 877} 878 879//===----------------------------------------------------------------------===// 880// MacroFusion - DAG post-processing to encourage fusion of macro ops. 881//===----------------------------------------------------------------------===// 882 883namespace { 884/// \brief Post-process the DAG to create cluster edges between instructions 885/// that may be fused by the processor into a single operation. 886class MacroFusion : public ScheduleDAGMutation { 887 const TargetInstrInfo *TII; 888public: 889 MacroFusion(const TargetInstrInfo *tii): TII(tii) {} 890 891 virtual void apply(ScheduleDAGMI *DAG); 892}; 893} // anonymous 894 895/// \brief Callback from DAG postProcessing to create cluster edges to encourage 896/// fused operations. 897void MacroFusion::apply(ScheduleDAGMI *DAG) { 898 // For now, assume targets can only fuse with the branch. 899 MachineInstr *Branch = DAG->ExitSU.getInstr(); 900 if (!Branch) 901 return; 902 903 for (unsigned Idx = DAG->SUnits.size(); Idx > 0;) { 904 SUnit *SU = &DAG->SUnits[--Idx]; 905 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch)) 906 continue; 907 908 // Create a single weak edge from SU to ExitSU. The only effect is to cause 909 // bottom-up scheduling to heavily prioritize the clustered SU. There is no 910 // need to copy predecessor edges from ExitSU to SU, since top-down 911 // scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling 912 // of SU, we could create an artificial edge from the deepest root, but it 913 // hasn't been needed yet. 914 bool Success = DAG->addEdge(&DAG->ExitSU, SDep(SU, SDep::Cluster)); 915 (void)Success; 916 assert(Success && "No DAG nodes should be reachable from ExitSU"); 917 918 DEBUG(dbgs() << "Macro Fuse SU(" << SU->NodeNum << ")\n"); 919 break; 920 } 921} 922 923//===----------------------------------------------------------------------===// 924// CopyConstrain - DAG post-processing to encourage copy elimination. 925//===----------------------------------------------------------------------===// 926 927namespace { 928/// \brief Post-process the DAG to create weak edges from all uses of a copy to 929/// the one use that defines the copy's source vreg, most likely an induction 930/// variable increment. 931class CopyConstrain : public ScheduleDAGMutation { 932 // Transient state. 933 SlotIndex RegionBeginIdx; 934 // RegionEndIdx is the slot index of the last non-debug instruction in the 935 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx. 936 SlotIndex RegionEndIdx; 937public: 938 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {} 939 940 virtual void apply(ScheduleDAGMI *DAG); 941 942protected: 943 void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG); 944}; 945} // anonymous 946 947/// constrainLocalCopy handles two possibilities: 948/// 1) Local src: 949/// I0: = dst 950/// I1: src = ... 951/// I2: = dst 952/// I3: dst = src (copy) 953/// (create pred->succ edges I0->I1, I2->I1) 954/// 955/// 2) Local copy: 956/// I0: dst = src (copy) 957/// I1: = dst 958/// I2: src = ... 959/// I3: = dst 960/// (create pred->succ edges I1->I2, I3->I2) 961/// 962/// Although the MachineScheduler is currently constrained to single blocks, 963/// this algorithm should handle extended blocks. An EBB is a set of 964/// contiguously numbered blocks such that the previous block in the EBB is 965/// always the single predecessor. 966void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMI *DAG) { 967 LiveIntervals *LIS = DAG->getLIS(); 968 MachineInstr *Copy = CopySU->getInstr(); 969 970 // Check for pure vreg copies. 971 unsigned SrcReg = Copy->getOperand(1).getReg(); 972 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) 973 return; 974 975 unsigned DstReg = Copy->getOperand(0).getReg(); 976 if (!TargetRegisterInfo::isVirtualRegister(DstReg)) 977 return; 978 979 // Check if either the dest or source is local. If it's live across a back 980 // edge, it's not local. Note that if both vregs are live across the back 981 // edge, we cannot successfully contrain the copy without cyclic scheduling. 982 unsigned LocalReg = DstReg; 983 unsigned GlobalReg = SrcReg; 984 LiveInterval *LocalLI = &LIS->getInterval(LocalReg); 985 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) { 986 LocalReg = SrcReg; 987 GlobalReg = DstReg; 988 LocalLI = &LIS->getInterval(LocalReg); 989 if (!LocalLI->isLocal(RegionBeginIdx, RegionEndIdx)) 990 return; 991 } 992 LiveInterval *GlobalLI = &LIS->getInterval(GlobalReg); 993 994 // Find the global segment after the start of the local LI. 995 LiveInterval::iterator GlobalSegment = GlobalLI->find(LocalLI->beginIndex()); 996 // If GlobalLI does not overlap LocalLI->start, then a copy directly feeds a 997 // local live range. We could create edges from other global uses to the local 998 // start, but the coalescer should have already eliminated these cases, so 999 // don't bother dealing with it. 1000 if (GlobalSegment == GlobalLI->end()) 1001 return; 1002 1003 // If GlobalSegment is killed at the LocalLI->start, the call to find() 1004 // returned the next global segment. But if GlobalSegment overlaps with 1005 // LocalLI->start, then advance to the next segement. If a hole in GlobalLI 1006 // exists in LocalLI's vicinity, GlobalSegment will be the end of the hole. 1007 if (GlobalSegment->contains(LocalLI->beginIndex())) 1008 ++GlobalSegment; 1009 1010 if (GlobalSegment == GlobalLI->end()) 1011 return; 1012 1013 // Check if GlobalLI contains a hole in the vicinity of LocalLI. 1014 if (GlobalSegment != GlobalLI->begin()) { 1015 // Two address defs have no hole. 1016 if (SlotIndex::isSameInstr(llvm::prior(GlobalSegment)->end, 1017 GlobalSegment->start)) { 1018 return; 1019 } 1020 // If GlobalLI has a prior segment, it must be live into the EBB. Otherwise 1021 // it would be a disconnected component in the live range. 1022 assert(llvm::prior(GlobalSegment)->start < LocalLI->beginIndex() && 1023 "Disconnected LRG within the scheduling region."); 1024 } 1025 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start); 1026 if (!GlobalDef) 1027 return; 1028 1029 SUnit *GlobalSU = DAG->getSUnit(GlobalDef); 1030 if (!GlobalSU) 1031 return; 1032 1033 // GlobalDef is the bottom of the GlobalLI hole. Open the hole by 1034 // constraining the uses of the last local def to precede GlobalDef. 1035 SmallVector<SUnit*,8> LocalUses; 1036 const VNInfo *LastLocalVN = LocalLI->getVNInfoBefore(LocalLI->endIndex()); 1037 MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def); 1038 SUnit *LastLocalSU = DAG->getSUnit(LastLocalDef); 1039 for (SUnit::const_succ_iterator 1040 I = LastLocalSU->Succs.begin(), E = LastLocalSU->Succs.end(); 1041 I != E; ++I) { 1042 if (I->getKind() != SDep::Data || I->getReg() != LocalReg) 1043 continue; 1044 if (I->getSUnit() == GlobalSU) 1045 continue; 1046 if (!DAG->canAddEdge(GlobalSU, I->getSUnit())) 1047 return; 1048 LocalUses.push_back(I->getSUnit()); 1049 } 1050 // Open the top of the GlobalLI hole by constraining any earlier global uses 1051 // to precede the start of LocalLI. 1052 SmallVector<SUnit*,8> GlobalUses; 1053 MachineInstr *FirstLocalDef = 1054 LIS->getInstructionFromIndex(LocalLI->beginIndex()); 1055 SUnit *FirstLocalSU = DAG->getSUnit(FirstLocalDef); 1056 for (SUnit::const_pred_iterator 1057 I = GlobalSU->Preds.begin(), E = GlobalSU->Preds.end(); I != E; ++I) { 1058 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg) 1059 continue; 1060 if (I->getSUnit() == FirstLocalSU) 1061 continue; 1062 if (!DAG->canAddEdge(FirstLocalSU, I->getSUnit())) 1063 return; 1064 GlobalUses.push_back(I->getSUnit()); 1065 } 1066 DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n"); 1067 // Add the weak edges. 1068 for (SmallVectorImpl<SUnit*>::const_iterator 1069 I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) { 1070 DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU(" 1071 << GlobalSU->NodeNum << ")\n"); 1072 DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak)); 1073 } 1074 for (SmallVectorImpl<SUnit*>::const_iterator 1075 I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) { 1076 DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU(" 1077 << FirstLocalSU->NodeNum << ")\n"); 1078 DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak)); 1079 } 1080} 1081 1082/// \brief Callback from DAG postProcessing to create weak edges to encourage 1083/// copy elimination. 1084void CopyConstrain::apply(ScheduleDAGMI *DAG) { 1085 MachineBasicBlock::iterator FirstPos = nextIfDebug(DAG->begin(), DAG->end()); 1086 if (FirstPos == DAG->end()) 1087 return; 1088 RegionBeginIdx = DAG->getLIS()->getInstructionIndex(&*FirstPos); 1089 RegionEndIdx = DAG->getLIS()->getInstructionIndex( 1090 &*priorNonDebug(DAG->end(), DAG->begin())); 1091 1092 for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) { 1093 SUnit *SU = &DAG->SUnits[Idx]; 1094 if (!SU->getInstr()->isCopy()) 1095 continue; 1096 1097 constrainLocalCopy(SU, DAG); 1098 } 1099} 1100 1101//===----------------------------------------------------------------------===// 1102// ConvergingScheduler - Implementation of the generic MachineSchedStrategy. 1103//===----------------------------------------------------------------------===// 1104 1105namespace { 1106/// ConvergingScheduler shrinks the unscheduled zone using heuristics to balance 1107/// the schedule. 1108class ConvergingScheduler : public MachineSchedStrategy { 1109public: 1110 /// Represent the type of SchedCandidate found within a single queue. 1111 /// pickNodeBidirectional depends on these listed by decreasing priority. 1112 enum CandReason { 1113 NoCand, PhysRegCopy, RegExcess, RegCritical, Cluster, Weak, RegMax, 1114 ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce, 1115 TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder}; 1116 1117#ifndef NDEBUG 1118 static const char *getReasonStr(ConvergingScheduler::CandReason Reason); 1119#endif 1120 1121 /// Policy for scheduling the next instruction in the candidate's zone. 1122 struct CandPolicy { 1123 bool ReduceLatency; 1124 unsigned ReduceResIdx; 1125 unsigned DemandResIdx; 1126 1127 CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {} 1128 }; 1129 1130 /// Status of an instruction's critical resource consumption. 1131 struct SchedResourceDelta { 1132 // Count critical resources in the scheduled region required by SU. 1133 unsigned CritResources; 1134 1135 // Count critical resources from another region consumed by SU. 1136 unsigned DemandedResources; 1137 1138 SchedResourceDelta(): CritResources(0), DemandedResources(0) {} 1139 1140 bool operator==(const SchedResourceDelta &RHS) const { 1141 return CritResources == RHS.CritResources 1142 && DemandedResources == RHS.DemandedResources; 1143 } 1144 bool operator!=(const SchedResourceDelta &RHS) const { 1145 return !operator==(RHS); 1146 } 1147 }; 1148 1149 /// Store the state used by ConvergingScheduler heuristics, required for the 1150 /// lifetime of one invocation of pickNode(). 1151 struct SchedCandidate { 1152 CandPolicy Policy; 1153 1154 // The best SUnit candidate. 1155 SUnit *SU; 1156 1157 // The reason for this candidate. 1158 CandReason Reason; 1159 1160 // Set of reasons that apply to multiple candidates. 1161 uint32_t RepeatReasonSet; 1162 1163 // Register pressure values for the best candidate. 1164 RegPressureDelta RPDelta; 1165 1166 // Critical resource consumption of the best candidate. 1167 SchedResourceDelta ResDelta; 1168 1169 SchedCandidate(const CandPolicy &policy) 1170 : Policy(policy), SU(NULL), Reason(NoCand), RepeatReasonSet(0) {} 1171 1172 bool isValid() const { return SU; } 1173 1174 // Copy the status of another candidate without changing policy. 1175 void setBest(SchedCandidate &Best) { 1176 assert(Best.Reason != NoCand && "uninitialized Sched candidate"); 1177 SU = Best.SU; 1178 Reason = Best.Reason; 1179 RPDelta = Best.RPDelta; 1180 ResDelta = Best.ResDelta; 1181 } 1182 1183 bool isRepeat(CandReason R) { return RepeatReasonSet & (1 << R); } 1184 void setRepeat(CandReason R) { RepeatReasonSet |= (1 << R); } 1185 1186 void initResourceDelta(const ScheduleDAGMI *DAG, 1187 const TargetSchedModel *SchedModel); 1188 }; 1189 1190 /// Summarize the unscheduled region. 1191 struct SchedRemainder { 1192 // Critical path through the DAG in expected latency. 1193 unsigned CriticalPath; 1194 1195 // Scaled count of micro-ops left to schedule. 1196 unsigned RemIssueCount; 1197 1198 // Unscheduled resources 1199 SmallVector<unsigned, 16> RemainingCounts; 1200 1201 void reset() { 1202 CriticalPath = 0; 1203 RemIssueCount = 0; 1204 RemainingCounts.clear(); 1205 } 1206 1207 SchedRemainder() { reset(); } 1208 1209 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel); 1210 }; 1211 1212 /// Each Scheduling boundary is associated with ready queues. It tracks the 1213 /// current cycle in the direction of movement, and maintains the state 1214 /// of "hazards" and other interlocks at the current cycle. 1215 struct SchedBoundary { 1216 ScheduleDAGMI *DAG; 1217 const TargetSchedModel *SchedModel; 1218 SchedRemainder *Rem; 1219 1220 ReadyQueue Available; 1221 ReadyQueue Pending; 1222 bool CheckPending; 1223 1224 // For heuristics, keep a list of the nodes that immediately depend on the 1225 // most recently scheduled node. 1226 SmallPtrSet<const SUnit*, 8> NextSUs; 1227 1228 ScheduleHazardRecognizer *HazardRec; 1229 1230 /// Number of cycles it takes to issue the instructions scheduled in this 1231 /// zone. It is defined as: scheduled-micro-ops / issue-width + stalls. 1232 /// See getStalls(). 1233 unsigned CurrCycle; 1234 1235 /// Micro-ops issued in the current cycle 1236 unsigned CurrMOps; 1237 1238 /// MinReadyCycle - Cycle of the soonest available instruction. 1239 unsigned MinReadyCycle; 1240 1241 // The expected latency of the critical path in this scheduled zone. 1242 unsigned ExpectedLatency; 1243 1244 // The latency of dependence chains leading into this zone. 1245 // For each node scheduled top-down: DLat = max DLat, N.Depth. 1246 // For each cycle scheduled: DLat -= 1. 1247 unsigned DependentLatency; 1248 1249 /// Count the scheduled (issued) micro-ops that can be retired by 1250 /// time=CurrCycle assuming the first scheduled instr is retired at time=0. 1251 unsigned RetiredMOps; 1252 1253 // Count scheduled resources that have been executed. Resources are 1254 // considered executed if they become ready in the time that it takes to 1255 // saturate any resource including the one in question. Counts are scaled 1256 // for direct comparison with other resources. Counts ca be compared with 1257 // MOps * getMicroOpFactor and Latency * getLatencyFactor. 1258 SmallVector<unsigned, 16> ExecutedResCounts; 1259 1260 /// Cache the max count for a single resource. 1261 unsigned MaxExecutedResCount; 1262 1263 // Cache the critical resources ID in this scheduled zone. 1264 unsigned ZoneCritResIdx; 1265 1266 // Is the scheduled region resource limited vs. latency limited. 1267 bool IsResourceLimited; 1268 1269#ifndef NDEBUG 1270 // Remember the greatest operand latency as an upper bound on the number of 1271 // times we should retry the pending queue because of a hazard. 1272 unsigned MaxObservedLatency; 1273#endif 1274 1275 void reset() { 1276 // A new HazardRec is created for each DAG and owned by SchedBoundary. 1277 delete HazardRec; 1278 1279 Available.clear(); 1280 Pending.clear(); 1281 CheckPending = false; 1282 NextSUs.clear(); 1283 HazardRec = 0; 1284 CurrCycle = 0; 1285 CurrMOps = 0; 1286 MinReadyCycle = UINT_MAX; 1287 ExpectedLatency = 0; 1288 DependentLatency = 0; 1289 RetiredMOps = 0; 1290 MaxExecutedResCount = 0; 1291 ZoneCritResIdx = 0; 1292 IsResourceLimited = false; 1293#ifndef NDEBUG 1294 MaxObservedLatency = 0; 1295#endif 1296 // Reserve a zero-count for invalid CritResIdx. 1297 ExecutedResCounts.resize(1); 1298 assert(!ExecutedResCounts[0] && "nonzero count for bad resource"); 1299 } 1300 1301 /// Pending queues extend the ready queues with the same ID and the 1302 /// PendingFlag set. 1303 SchedBoundary(unsigned ID, const Twine &Name): 1304 DAG(0), SchedModel(0), Rem(0), Available(ID, Name+".A"), 1305 Pending(ID << ConvergingScheduler::LogMaxQID, Name+".P"), 1306 HazardRec(0) { 1307 reset(); 1308 } 1309 1310 ~SchedBoundary() { delete HazardRec; } 1311 1312 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, 1313 SchedRemainder *rem); 1314 1315 bool isTop() const { 1316 return Available.getID() == ConvergingScheduler::TopQID; 1317 } 1318 1319#ifndef NDEBUG 1320 const char *getResourceName(unsigned PIdx) { 1321 if (!PIdx) 1322 return "MOps"; 1323 return SchedModel->getProcResource(PIdx)->Name; 1324 } 1325#endif 1326 1327 /// Get the number of latency cycles "covered" by the scheduled 1328 /// instructions. This is the larger of the critical path within the zone 1329 /// and the number of cycles required to issue the instructions. 1330 unsigned getScheduledLatency() const { 1331 return std::max(ExpectedLatency, CurrCycle); 1332 } 1333 1334 unsigned getUnscheduledLatency(SUnit *SU) const { 1335 return isTop() ? SU->getHeight() : SU->getDepth(); 1336 } 1337 1338 unsigned getResourceCount(unsigned ResIdx) const { 1339 return ExecutedResCounts[ResIdx]; 1340 } 1341 1342 /// Get the scaled count of scheduled micro-ops and resources, including 1343 /// executed resources. 1344 unsigned getCriticalCount() const { 1345 if (!ZoneCritResIdx) 1346 return RetiredMOps * SchedModel->getMicroOpFactor(); 1347 return getResourceCount(ZoneCritResIdx); 1348 } 1349 1350 /// Get a scaled count for the minimum execution time of the scheduled 1351 /// micro-ops that are ready to execute by getExecutedCount. Notice the 1352 /// feedback loop. 1353 unsigned getExecutedCount() const { 1354 return std::max(CurrCycle * SchedModel->getLatencyFactor(), 1355 MaxExecutedResCount); 1356 } 1357 1358 bool checkHazard(SUnit *SU); 1359 1360 unsigned findMaxLatency(ArrayRef<SUnit*> ReadySUs); 1361 1362 unsigned getOtherResourceCount(unsigned &OtherCritIdx); 1363 1364 void setPolicy(CandPolicy &Policy, SchedBoundary &OtherZone); 1365 1366 void releaseNode(SUnit *SU, unsigned ReadyCycle); 1367 1368 void bumpCycle(unsigned NextCycle); 1369 1370 void incExecutedResources(unsigned PIdx, unsigned Count); 1371 1372 unsigned countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle); 1373 1374 void bumpNode(SUnit *SU); 1375 1376 void releasePending(); 1377 1378 void removeReady(SUnit *SU); 1379 1380 SUnit *pickOnlyChoice(); 1381 1382#ifndef NDEBUG 1383 void dumpScheduledState(); 1384#endif 1385 }; 1386 1387private: 1388 ScheduleDAGMI *DAG; 1389 const TargetSchedModel *SchedModel; 1390 const TargetRegisterInfo *TRI; 1391 1392 // State of the top and bottom scheduled instruction boundaries. 1393 SchedRemainder Rem; 1394 SchedBoundary Top; 1395 SchedBoundary Bot; 1396 1397public: 1398 /// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both) 1399 enum { 1400 TopQID = 1, 1401 BotQID = 2, 1402 LogMaxQID = 2 1403 }; 1404 1405 ConvergingScheduler(): 1406 DAG(0), SchedModel(0), TRI(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} 1407 1408 virtual void initialize(ScheduleDAGMI *dag); 1409 1410 virtual SUnit *pickNode(bool &IsTopNode); 1411 1412 virtual void schedNode(SUnit *SU, bool IsTopNode); 1413 1414 virtual void releaseTopNode(SUnit *SU); 1415 1416 virtual void releaseBottomNode(SUnit *SU); 1417 1418 virtual void registerRoots(); 1419 1420protected: 1421 void tryCandidate(SchedCandidate &Cand, 1422 SchedCandidate &TryCand, 1423 SchedBoundary &Zone, 1424 const RegPressureTracker &RPTracker, 1425 RegPressureTracker &TempTracker); 1426 1427 SUnit *pickNodeBidirectional(bool &IsTopNode); 1428 1429 void pickNodeFromQueue(SchedBoundary &Zone, 1430 const RegPressureTracker &RPTracker, 1431 SchedCandidate &Candidate); 1432 1433 void reschedulePhysRegCopies(SUnit *SU, bool isTop); 1434 1435#ifndef NDEBUG 1436 void traceCandidate(const SchedCandidate &Cand); 1437#endif 1438}; 1439} // namespace 1440 1441void ConvergingScheduler::SchedRemainder:: 1442init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { 1443 reset(); 1444 if (!SchedModel->hasInstrSchedModel()) 1445 return; 1446 RemainingCounts.resize(SchedModel->getNumProcResourceKinds()); 1447 for (std::vector<SUnit>::iterator 1448 I = DAG->SUnits.begin(), E = DAG->SUnits.end(); I != E; ++I) { 1449 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I); 1450 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC) 1451 * SchedModel->getMicroOpFactor(); 1452 for (TargetSchedModel::ProcResIter 1453 PI = SchedModel->getWriteProcResBegin(SC), 1454 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { 1455 unsigned PIdx = PI->ProcResourceIdx; 1456 unsigned Factor = SchedModel->getResourceFactor(PIdx); 1457 RemainingCounts[PIdx] += (Factor * PI->Cycles); 1458 } 1459 } 1460} 1461 1462void ConvergingScheduler::SchedBoundary:: 1463init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) { 1464 reset(); 1465 DAG = dag; 1466 SchedModel = smodel; 1467 Rem = rem; 1468 if (SchedModel->hasInstrSchedModel()) 1469 ExecutedResCounts.resize(SchedModel->getNumProcResourceKinds()); 1470} 1471 1472void ConvergingScheduler::initialize(ScheduleDAGMI *dag) { 1473 DAG = dag; 1474 SchedModel = DAG->getSchedModel(); 1475 TRI = DAG->TRI; 1476 1477 Rem.init(DAG, SchedModel); 1478 Top.init(DAG, SchedModel, &Rem); 1479 Bot.init(DAG, SchedModel, &Rem); 1480 1481 // Initialize resource counts. 1482 1483 // Initialize the HazardRecognizers. If itineraries don't exist, are empty, or 1484 // are disabled, then these HazardRecs will be disabled. 1485 const InstrItineraryData *Itin = SchedModel->getInstrItineraries(); 1486 const TargetMachine &TM = DAG->MF.getTarget(); 1487 Top.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG); 1488 Bot.HazardRec = TM.getInstrInfo()->CreateTargetMIHazardRecognizer(Itin, DAG); 1489 1490 assert((!ForceTopDown || !ForceBottomUp) && 1491 "-misched-topdown incompatible with -misched-bottomup"); 1492} 1493 1494void ConvergingScheduler::releaseTopNode(SUnit *SU) { 1495 if (SU->isScheduled) 1496 return; 1497 1498 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 1499 I != E; ++I) { 1500 if (I->isWeak()) 1501 continue; 1502 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle; 1503 unsigned Latency = I->getLatency(); 1504#ifndef NDEBUG 1505 Top.MaxObservedLatency = std::max(Latency, Top.MaxObservedLatency); 1506#endif 1507 if (SU->TopReadyCycle < PredReadyCycle + Latency) 1508 SU->TopReadyCycle = PredReadyCycle + Latency; 1509 } 1510 Top.releaseNode(SU, SU->TopReadyCycle); 1511} 1512 1513void ConvergingScheduler::releaseBottomNode(SUnit *SU) { 1514 if (SU->isScheduled) 1515 return; 1516 1517 assert(SU->getInstr() && "Scheduled SUnit must have instr"); 1518 1519 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 1520 I != E; ++I) { 1521 if (I->isWeak()) 1522 continue; 1523 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; 1524 unsigned Latency = I->getLatency(); 1525#ifndef NDEBUG 1526 Bot.MaxObservedLatency = std::max(Latency, Bot.MaxObservedLatency); 1527#endif 1528 if (SU->BotReadyCycle < SuccReadyCycle + Latency) 1529 SU->BotReadyCycle = SuccReadyCycle + Latency; 1530 } 1531 Bot.releaseNode(SU, SU->BotReadyCycle); 1532} 1533 1534void ConvergingScheduler::registerRoots() { 1535 Rem.CriticalPath = DAG->ExitSU.getDepth(); 1536 // Some roots may not feed into ExitSU. Check all of them in case. 1537 for (std::vector<SUnit*>::const_iterator 1538 I = Bot.Available.begin(), E = Bot.Available.end(); I != E; ++I) { 1539 if ((*I)->getDepth() > Rem.CriticalPath) 1540 Rem.CriticalPath = (*I)->getDepth(); 1541 } 1542 DEBUG(dbgs() << "Critical Path: " << Rem.CriticalPath << '\n'); 1543} 1544 1545/// Does this SU have a hazard within the current instruction group. 1546/// 1547/// The scheduler supports two modes of hazard recognition. The first is the 1548/// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that 1549/// supports highly complicated in-order reservation tables 1550/// (ScoreboardHazardRecognizer) and arbitraty target-specific logic. 1551/// 1552/// The second is a streamlined mechanism that checks for hazards based on 1553/// simple counters that the scheduler itself maintains. It explicitly checks 1554/// for instruction dispatch limitations, including the number of micro-ops that 1555/// can dispatch per cycle. 1556/// 1557/// TODO: Also check whether the SU must start a new group. 1558bool ConvergingScheduler::SchedBoundary::checkHazard(SUnit *SU) { 1559 if (HazardRec->isEnabled()) 1560 return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard; 1561 1562 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); 1563 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) { 1564 DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops=" 1565 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n'); 1566 return true; 1567 } 1568 return false; 1569} 1570 1571// Find the unscheduled node in ReadySUs with the highest latency. 1572unsigned ConvergingScheduler::SchedBoundary:: 1573findMaxLatency(ArrayRef<SUnit*> ReadySUs) { 1574 SUnit *LateSU = 0; 1575 unsigned RemLatency = 0; 1576 for (ArrayRef<SUnit*>::iterator I = ReadySUs.begin(), E = ReadySUs.end(); 1577 I != E; ++I) { 1578 unsigned L = getUnscheduledLatency(*I); 1579 if (L > RemLatency) { 1580 RemLatency = L; 1581 LateSU = *I; 1582 } 1583 } 1584 if (LateSU) { 1585 DEBUG(dbgs() << Available.getName() << " RemLatency SU(" 1586 << LateSU->NodeNum << ") " << RemLatency << "c\n"); 1587 } 1588 return RemLatency; 1589} 1590 1591// Count resources in this zone and the remaining unscheduled 1592// instruction. Return the max count, scaled. Set OtherCritIdx to the critical 1593// resource index, or zero if the zone is issue limited. 1594unsigned ConvergingScheduler::SchedBoundary:: 1595getOtherResourceCount(unsigned &OtherCritIdx) { 1596 if (!SchedModel->hasInstrSchedModel()) 1597 return 0; 1598 1599 unsigned OtherCritCount = Rem->RemIssueCount 1600 + (RetiredMOps * SchedModel->getMicroOpFactor()); 1601 DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: " 1602 << OtherCritCount / SchedModel->getMicroOpFactor() << '\n'); 1603 OtherCritIdx = 0; 1604 for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds(); 1605 PIdx != PEnd; ++PIdx) { 1606 unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx]; 1607 if (OtherCount > OtherCritCount) { 1608 OtherCritCount = OtherCount; 1609 OtherCritIdx = PIdx; 1610 } 1611 } 1612 if (OtherCritIdx) { 1613 DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: " 1614 << OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx) 1615 << " " << getResourceName(OtherCritIdx) << "\n"); 1616 } 1617 return OtherCritCount; 1618} 1619 1620/// Set the CandPolicy for this zone given the current resources and latencies 1621/// inside and outside the zone. 1622void ConvergingScheduler::SchedBoundary::setPolicy(CandPolicy &Policy, 1623 SchedBoundary &OtherZone) { 1624 // Now that potential stalls have been considered, apply preemptive heuristics 1625 // based on the the total latency and resources inside and outside this 1626 // zone. 1627 1628 // Compute remaining latency. We need this both to determine whether the 1629 // overall schedule has become latency-limited and whether the instructions 1630 // outside this zone are resource or latency limited. 1631 // 1632 // The "dependent" latency is updated incrementally during scheduling as the 1633 // max height/depth of scheduled nodes minus the cycles since it was 1634 // scheduled: 1635 // DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone 1636 // 1637 // The "independent" latency is the max ready queue depth: 1638 // ILat = max N.depth for N in Available|Pending 1639 // 1640 // RemainingLatency is the greater of independent and dependent latency. 1641 unsigned RemLatency = DependentLatency; 1642 RemLatency = std::max(RemLatency, findMaxLatency(Available.elements())); 1643 RemLatency = std::max(RemLatency, findMaxLatency(Pending.elements())); 1644 1645 // Compute the critical resource outside the zone. 1646 unsigned OtherCritIdx; 1647 unsigned OtherCount = OtherZone.getOtherResourceCount(OtherCritIdx); 1648 1649 bool OtherResLimited = false; 1650 if (SchedModel->hasInstrSchedModel()) { 1651 unsigned LFactor = SchedModel->getLatencyFactor(); 1652 OtherResLimited = (int)(OtherCount - (RemLatency * LFactor)) > (int)LFactor; 1653 } 1654 if (!OtherResLimited && (RemLatency + CurrCycle > Rem->CriticalPath)) { 1655 Policy.ReduceLatency |= true; 1656 DEBUG(dbgs() << " " << Available.getName() << " RemainingLatency " 1657 << RemLatency << " + " << CurrCycle << "c > CritPath " 1658 << Rem->CriticalPath << "\n"); 1659 } 1660 // If the same resource is limiting inside and outside the zone, do nothing. 1661 if (IsResourceLimited && OtherResLimited && (ZoneCritResIdx == OtherCritIdx)) 1662 return; 1663 1664 DEBUG( 1665 if (IsResourceLimited) { 1666 dbgs() << " " << Available.getName() << " ResourceLimited: " 1667 << getResourceName(ZoneCritResIdx) << "\n"; 1668 } 1669 if (OtherResLimited) 1670 dbgs() << " RemainingLimit: " << getResourceName(OtherCritIdx) << "\n"; 1671 if (!IsResourceLimited && !OtherResLimited) 1672 dbgs() << " Latency limited both directions.\n"); 1673 1674 if (IsResourceLimited && !Policy.ReduceResIdx) 1675 Policy.ReduceResIdx = ZoneCritResIdx; 1676 1677 if (OtherResLimited) 1678 Policy.DemandResIdx = OtherCritIdx; 1679} 1680 1681void ConvergingScheduler::SchedBoundary::releaseNode(SUnit *SU, 1682 unsigned ReadyCycle) { 1683 if (ReadyCycle < MinReadyCycle) 1684 MinReadyCycle = ReadyCycle; 1685 1686 // Check for interlocks first. For the purpose of other heuristics, an 1687 // instruction that cannot issue appears as if it's not in the ReadyQueue. 1688 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0; 1689 if ((!IsBuffered && ReadyCycle > CurrCycle) || checkHazard(SU)) 1690 Pending.push(SU); 1691 else 1692 Available.push(SU); 1693 1694 // Record this node as an immediate dependent of the scheduled node. 1695 NextSUs.insert(SU); 1696} 1697 1698/// Move the boundary of scheduled code by one cycle. 1699void ConvergingScheduler::SchedBoundary::bumpCycle(unsigned NextCycle) { 1700 if (SchedModel->getMicroOpBufferSize() == 0) { 1701 assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized"); 1702 if (MinReadyCycle > NextCycle) 1703 NextCycle = MinReadyCycle; 1704 } 1705 // Update the current micro-ops, which will issue in the next cycle. 1706 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle); 1707 CurrMOps = (CurrMOps <= DecMOps) ? 0 : CurrMOps - DecMOps; 1708 1709 // Decrement DependentLatency based on the next cycle. 1710 if ((NextCycle - CurrCycle) > DependentLatency) 1711 DependentLatency = 0; 1712 else 1713 DependentLatency -= (NextCycle - CurrCycle); 1714 1715 if (!HazardRec->isEnabled()) { 1716 // Bypass HazardRec virtual calls. 1717 CurrCycle = NextCycle; 1718 } 1719 else { 1720 // Bypass getHazardType calls in case of long latency. 1721 for (; CurrCycle != NextCycle; ++CurrCycle) { 1722 if (isTop()) 1723 HazardRec->AdvanceCycle(); 1724 else 1725 HazardRec->RecedeCycle(); 1726 } 1727 } 1728 CheckPending = true; 1729 unsigned LFactor = SchedModel->getLatencyFactor(); 1730 IsResourceLimited = 1731 (int)(getCriticalCount() - (getScheduledLatency() * LFactor)) 1732 > (int)LFactor; 1733 1734 DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n'); 1735} 1736 1737void ConvergingScheduler::SchedBoundary::incExecutedResources(unsigned PIdx, 1738 unsigned Count) { 1739 ExecutedResCounts[PIdx] += Count; 1740 if (ExecutedResCounts[PIdx] > MaxExecutedResCount) 1741 MaxExecutedResCount = ExecutedResCounts[PIdx]; 1742} 1743 1744/// Add the given processor resource to this scheduled zone. 1745/// 1746/// \param Cycles indicates the number of consecutive (non-pipelined) cycles 1747/// during which this resource is consumed. 1748/// 1749/// \return the next cycle at which the instruction may execute without 1750/// oversubscribing resources. 1751unsigned ConvergingScheduler::SchedBoundary:: 1752countResource(unsigned PIdx, unsigned Cycles, unsigned ReadyCycle) { 1753 unsigned Factor = SchedModel->getResourceFactor(PIdx); 1754 unsigned Count = Factor * Cycles; 1755 DEBUG(dbgs() << " " << getResourceName(PIdx) 1756 << " +" << Cycles << "x" << Factor << "u\n"); 1757 1758 // Update Executed resources counts. 1759 incExecutedResources(PIdx, Count); 1760 assert(Rem->RemainingCounts[PIdx] >= Count && "resource double counted"); 1761 Rem->RemainingCounts[PIdx] -= Count; 1762 1763 // Check if this resource exceeds the current critical resource by a full 1764 // cycle. If so, it becomes the critical resource. 1765 if (ZoneCritResIdx != PIdx 1766 && ((int)(getResourceCount(PIdx) - getCriticalCount()) 1767 >= (int)SchedModel->getLatencyFactor())) { 1768 ZoneCritResIdx = PIdx; 1769 DEBUG(dbgs() << " *** Critical resource " 1770 << getResourceName(PIdx) << ": " 1771 << getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n"); 1772 } 1773 // TODO: We don't yet model reserved resources. It's not hard though. 1774 return CurrCycle; 1775} 1776 1777/// Move the boundary of scheduled code by one SUnit. 1778void ConvergingScheduler::SchedBoundary::bumpNode(SUnit *SU) { 1779 // Update the reservation table. 1780 if (HazardRec->isEnabled()) { 1781 if (!isTop() && SU->isCall) { 1782 // Calls are scheduled with their preceding instructions. For bottom-up 1783 // scheduling, clear the pipeline state before emitting. 1784 HazardRec->Reset(); 1785 } 1786 HazardRec->EmitInstruction(SU); 1787 } 1788 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); 1789 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr()); 1790 CurrMOps += IncMOps; 1791 // checkHazard prevents scheduling multiple instructions per cycle that exceed 1792 // issue width. However, we commonly reach the maximum. In this case 1793 // opportunistically bump the cycle to avoid uselessly checking everything in 1794 // the readyQ. Furthermore, a single instruction may produce more than one 1795 // cycle's worth of micro-ops. 1796 // 1797 // TODO: Also check if this SU must end a dispatch group. 1798 unsigned NextCycle = CurrCycle; 1799 if (CurrMOps >= SchedModel->getIssueWidth()) { 1800 ++NextCycle; 1801 DEBUG(dbgs() << " *** Max MOps " << CurrMOps 1802 << " at cycle " << CurrCycle << '\n'); 1803 } 1804 unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle); 1805 DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n"); 1806 1807 switch (SchedModel->getMicroOpBufferSize()) { 1808 case 0: 1809 assert(ReadyCycle <= CurrCycle && "Broken PendingQueue"); 1810 break; 1811 case 1: 1812 if (ReadyCycle > NextCycle) { 1813 NextCycle = ReadyCycle; 1814 DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n"); 1815 } 1816 break; 1817 default: 1818 // We don't currently model the OOO reorder buffer, so consider all 1819 // scheduled MOps to be "retired". 1820 break; 1821 } 1822 RetiredMOps += IncMOps; 1823 1824 // Update resource counts and critical resource. 1825 if (SchedModel->hasInstrSchedModel()) { 1826 unsigned DecRemIssue = IncMOps * SchedModel->getMicroOpFactor(); 1827 assert(Rem->RemIssueCount >= DecRemIssue && "MOps double counted"); 1828 Rem->RemIssueCount -= DecRemIssue; 1829 if (ZoneCritResIdx) { 1830 // Scale scheduled micro-ops for comparing with the critical resource. 1831 unsigned ScaledMOps = 1832 RetiredMOps * SchedModel->getMicroOpFactor(); 1833 1834 // If scaled micro-ops are now more than the previous critical resource by 1835 // a full cycle, then micro-ops issue becomes critical. 1836 if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx)) 1837 >= (int)SchedModel->getLatencyFactor()) { 1838 ZoneCritResIdx = 0; 1839 DEBUG(dbgs() << " *** Critical resource NumMicroOps: " 1840 << ScaledMOps / SchedModel->getLatencyFactor() << "c\n"); 1841 } 1842 } 1843 for (TargetSchedModel::ProcResIter 1844 PI = SchedModel->getWriteProcResBegin(SC), 1845 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { 1846 unsigned RCycle = 1847 countResource(PI->ProcResourceIdx, PI->Cycles, ReadyCycle); 1848 if (RCycle > NextCycle) 1849 NextCycle = RCycle; 1850 } 1851 } 1852 // Update ExpectedLatency and DependentLatency. 1853 unsigned &TopLatency = isTop() ? ExpectedLatency : DependentLatency; 1854 unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency; 1855 if (SU->getDepth() > TopLatency) { 1856 TopLatency = SU->getDepth(); 1857 DEBUG(dbgs() << " " << Available.getName() 1858 << " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n"); 1859 } 1860 if (SU->getHeight() > BotLatency) { 1861 BotLatency = SU->getHeight(); 1862 DEBUG(dbgs() << " " << Available.getName() 1863 << " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n"); 1864 } 1865 // If we stall for any reason, bump the cycle. 1866 if (NextCycle > CurrCycle) { 1867 bumpCycle(NextCycle); 1868 } 1869 else { 1870 // After updating ZoneCritResIdx and ExpectedLatency, check if we're 1871 // resource limited. If a stall occured, bumpCycle does this. 1872 unsigned LFactor = SchedModel->getLatencyFactor(); 1873 IsResourceLimited = 1874 (int)(getCriticalCount() - (getScheduledLatency() * LFactor)) 1875 > (int)LFactor; 1876 } 1877 DEBUG(dumpScheduledState()); 1878} 1879 1880/// Release pending ready nodes in to the available queue. This makes them 1881/// visible to heuristics. 1882void ConvergingScheduler::SchedBoundary::releasePending() { 1883 // If the available queue is empty, it is safe to reset MinReadyCycle. 1884 if (Available.empty()) 1885 MinReadyCycle = UINT_MAX; 1886 1887 // Check to see if any of the pending instructions are ready to issue. If 1888 // so, add them to the available queue. 1889 bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0; 1890 for (unsigned i = 0, e = Pending.size(); i != e; ++i) { 1891 SUnit *SU = *(Pending.begin()+i); 1892 unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle; 1893 1894 if (ReadyCycle < MinReadyCycle) 1895 MinReadyCycle = ReadyCycle; 1896 1897 if (!IsBuffered && ReadyCycle > CurrCycle) 1898 continue; 1899 1900 if (checkHazard(SU)) 1901 continue; 1902 1903 Available.push(SU); 1904 Pending.remove(Pending.begin()+i); 1905 --i; --e; 1906 } 1907 DEBUG(if (!Pending.empty()) Pending.dump()); 1908 CheckPending = false; 1909} 1910 1911/// Remove SU from the ready set for this boundary. 1912void ConvergingScheduler::SchedBoundary::removeReady(SUnit *SU) { 1913 if (Available.isInQueue(SU)) 1914 Available.remove(Available.find(SU)); 1915 else { 1916 assert(Pending.isInQueue(SU) && "bad ready count"); 1917 Pending.remove(Pending.find(SU)); 1918 } 1919} 1920 1921/// If this queue only has one ready candidate, return it. As a side effect, 1922/// defer any nodes that now hit a hazard, and advance the cycle until at least 1923/// one node is ready. If multiple instructions are ready, return NULL. 1924SUnit *ConvergingScheduler::SchedBoundary::pickOnlyChoice() { 1925 if (CheckPending) 1926 releasePending(); 1927 1928 if (CurrMOps > 0) { 1929 // Defer any ready instrs that now have a hazard. 1930 for (ReadyQueue::iterator I = Available.begin(); I != Available.end();) { 1931 if (checkHazard(*I)) { 1932 Pending.push(*I); 1933 I = Available.remove(I); 1934 continue; 1935 } 1936 ++I; 1937 } 1938 } 1939 for (unsigned i = 0; Available.empty(); ++i) { 1940 assert(i <= (HazardRec->getMaxLookAhead() + MaxObservedLatency) && 1941 "permanent hazard"); (void)i; 1942 bumpCycle(CurrCycle + 1); 1943 releasePending(); 1944 } 1945 if (Available.size() == 1) 1946 return *Available.begin(); 1947 return NULL; 1948} 1949 1950#ifndef NDEBUG 1951// This is useful information to dump after bumpNode. 1952// Note that the Queue contents are more useful before pickNodeFromQueue. 1953void ConvergingScheduler::SchedBoundary::dumpScheduledState() { 1954 unsigned ResFactor; 1955 unsigned ResCount; 1956 if (ZoneCritResIdx) { 1957 ResFactor = SchedModel->getResourceFactor(ZoneCritResIdx); 1958 ResCount = getResourceCount(ZoneCritResIdx); 1959 } 1960 else { 1961 ResFactor = SchedModel->getMicroOpFactor(); 1962 ResCount = RetiredMOps * SchedModel->getMicroOpFactor(); 1963 } 1964 unsigned LFactor = SchedModel->getLatencyFactor(); 1965 dbgs() << Available.getName() << " @" << CurrCycle << "c\n" 1966 << " Retired: " << RetiredMOps; 1967 dbgs() << "\n Executed: " << getExecutedCount() / LFactor << "c"; 1968 dbgs() << "\n Critical: " << ResCount / LFactor << "c, " 1969 << ResCount / ResFactor << " " << getResourceName(ZoneCritResIdx) 1970 << "\n ExpectedLatency: " << ExpectedLatency << "c\n" 1971 << (IsResourceLimited ? " - Resource" : " - Latency") 1972 << " limited.\n"; 1973} 1974#endif 1975 1976void ConvergingScheduler::SchedCandidate:: 1977initResourceDelta(const ScheduleDAGMI *DAG, 1978 const TargetSchedModel *SchedModel) { 1979 if (!Policy.ReduceResIdx && !Policy.DemandResIdx) 1980 return; 1981 1982 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); 1983 for (TargetSchedModel::ProcResIter 1984 PI = SchedModel->getWriteProcResBegin(SC), 1985 PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { 1986 if (PI->ProcResourceIdx == Policy.ReduceResIdx) 1987 ResDelta.CritResources += PI->Cycles; 1988 if (PI->ProcResourceIdx == Policy.DemandResIdx) 1989 ResDelta.DemandedResources += PI->Cycles; 1990 } 1991} 1992 1993 1994/// Return true if this heuristic determines order. 1995static bool tryLess(int TryVal, int CandVal, 1996 ConvergingScheduler::SchedCandidate &TryCand, 1997 ConvergingScheduler::SchedCandidate &Cand, 1998 ConvergingScheduler::CandReason Reason) { 1999 if (TryVal < CandVal) { 2000 TryCand.Reason = Reason; 2001 return true; 2002 } 2003 if (TryVal > CandVal) { 2004 if (Cand.Reason > Reason) 2005 Cand.Reason = Reason; 2006 return true; 2007 } 2008 Cand.setRepeat(Reason); 2009 return false; 2010} 2011 2012static bool tryGreater(int TryVal, int CandVal, 2013 ConvergingScheduler::SchedCandidate &TryCand, 2014 ConvergingScheduler::SchedCandidate &Cand, 2015 ConvergingScheduler::CandReason Reason) { 2016 if (TryVal > CandVal) { 2017 TryCand.Reason = Reason; 2018 return true; 2019 } 2020 if (TryVal < CandVal) { 2021 if (Cand.Reason > Reason) 2022 Cand.Reason = Reason; 2023 return true; 2024 } 2025 Cand.setRepeat(Reason); 2026 return false; 2027} 2028 2029static unsigned getWeakLeft(const SUnit *SU, bool isTop) { 2030 return (isTop) ? SU->WeakPredsLeft : SU->WeakSuccsLeft; 2031} 2032 2033/// Minimize physical register live ranges. Regalloc wants them adjacent to 2034/// their physreg def/use. 2035/// 2036/// FIXME: This is an unnecessary check on the critical path. Most are root/leaf 2037/// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled 2038/// with the operation that produces or consumes the physreg. We'll do this when 2039/// regalloc has support for parallel copies. 2040static int biasPhysRegCopy(const SUnit *SU, bool isTop) { 2041 const MachineInstr *MI = SU->getInstr(); 2042 if (!MI->isCopy()) 2043 return 0; 2044 2045 unsigned ScheduledOper = isTop ? 1 : 0; 2046 unsigned UnscheduledOper = isTop ? 0 : 1; 2047 // If we have already scheduled the physreg produce/consumer, immediately 2048 // schedule the copy. 2049 if (TargetRegisterInfo::isPhysicalRegister( 2050 MI->getOperand(ScheduledOper).getReg())) 2051 return 1; 2052 // If the physreg is at the boundary, defer it. Otherwise schedule it 2053 // immediately to free the dependent. We can hoist the copy later. 2054 bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft; 2055 if (TargetRegisterInfo::isPhysicalRegister( 2056 MI->getOperand(UnscheduledOper).getReg())) 2057 return AtBoundary ? -1 : 1; 2058 return 0; 2059} 2060 2061/// Apply a set of heursitics to a new candidate. Heuristics are currently 2062/// hierarchical. This may be more efficient than a graduated cost model because 2063/// we don't need to evaluate all aspects of the model for each node in the 2064/// queue. But it's really done to make the heuristics easier to debug and 2065/// statistically analyze. 2066/// 2067/// \param Cand provides the policy and current best candidate. 2068/// \param TryCand refers to the next SUnit candidate, otherwise uninitialized. 2069/// \param Zone describes the scheduled zone that we are extending. 2070/// \param RPTracker describes reg pressure within the scheduled zone. 2071/// \param TempTracker is a scratch pressure tracker to reuse in queries. 2072void ConvergingScheduler::tryCandidate(SchedCandidate &Cand, 2073 SchedCandidate &TryCand, 2074 SchedBoundary &Zone, 2075 const RegPressureTracker &RPTracker, 2076 RegPressureTracker &TempTracker) { 2077 2078 // Always initialize TryCand's RPDelta. 2079 TempTracker.getMaxPressureDelta(TryCand.SU->getInstr(), TryCand.RPDelta, 2080 DAG->getRegionCriticalPSets(), 2081 DAG->getRegPressure().MaxSetPressure); 2082 2083 // Initialize the candidate if needed. 2084 if (!Cand.isValid()) { 2085 TryCand.Reason = NodeOrder; 2086 return; 2087 } 2088 2089 if (tryGreater(biasPhysRegCopy(TryCand.SU, Zone.isTop()), 2090 biasPhysRegCopy(Cand.SU, Zone.isTop()), 2091 TryCand, Cand, PhysRegCopy)) 2092 return; 2093 2094 // Avoid exceeding the target's limit. 2095 if (tryLess(TryCand.RPDelta.Excess.UnitIncrease, 2096 Cand.RPDelta.Excess.UnitIncrease, TryCand, Cand, RegExcess)) 2097 return; 2098 2099 // Avoid increasing the max critical pressure in the scheduled region. 2100 if (tryLess(TryCand.RPDelta.CriticalMax.UnitIncrease, 2101 Cand.RPDelta.CriticalMax.UnitIncrease, 2102 TryCand, Cand, RegCritical)) 2103 return; 2104 2105 // Keep clustered nodes together to encourage downstream peephole 2106 // optimizations which may reduce resource requirements. 2107 // 2108 // This is a best effort to set things up for a post-RA pass. Optimizations 2109 // like generating loads of multiple registers should ideally be done within 2110 // the scheduler pass by combining the loads during DAG postprocessing. 2111 const SUnit *NextClusterSU = 2112 Zone.isTop() ? DAG->getNextClusterSucc() : DAG->getNextClusterPred(); 2113 if (tryGreater(TryCand.SU == NextClusterSU, Cand.SU == NextClusterSU, 2114 TryCand, Cand, Cluster)) 2115 return; 2116 2117 // Weak edges are for clustering and other constraints. 2118 if (tryLess(getWeakLeft(TryCand.SU, Zone.isTop()), 2119 getWeakLeft(Cand.SU, Zone.isTop()), 2120 TryCand, Cand, Weak)) { 2121 return; 2122 } 2123 // Avoid increasing the max pressure of the entire region. 2124 if (tryLess(TryCand.RPDelta.CurrentMax.UnitIncrease, 2125 Cand.RPDelta.CurrentMax.UnitIncrease, TryCand, Cand, RegMax)) 2126 return; 2127 2128 // Avoid critical resource consumption and balance the schedule. 2129 TryCand.initResourceDelta(DAG, SchedModel); 2130 if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources, 2131 TryCand, Cand, ResourceReduce)) 2132 return; 2133 if (tryGreater(TryCand.ResDelta.DemandedResources, 2134 Cand.ResDelta.DemandedResources, 2135 TryCand, Cand, ResourceDemand)) 2136 return; 2137 2138 // Avoid serializing long latency dependence chains. 2139 if (Cand.Policy.ReduceLatency) { 2140 if (Zone.isTop()) { 2141 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) { 2142 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(), 2143 TryCand, Cand, TopDepthReduce)) 2144 return; 2145 } 2146 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2147 TryCand, Cand, TopPathReduce)) 2148 return; 2149 } 2150 else { 2151 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) { 2152 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2153 TryCand, Cand, BotHeightReduce)) 2154 return; 2155 } 2156 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(), 2157 TryCand, Cand, BotPathReduce)) 2158 return; 2159 } 2160 } 2161 2162 // Prefer immediate defs/users of the last scheduled instruction. This is a 2163 // local pressure avoidance strategy that also makes the machine code 2164 // readable. 2165 if (tryGreater(Zone.NextSUs.count(TryCand.SU), Zone.NextSUs.count(Cand.SU), 2166 TryCand, Cand, NextDefUse)) 2167 return; 2168 2169 // Fall through to original instruction order. 2170 if ((Zone.isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) 2171 || (!Zone.isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { 2172 TryCand.Reason = NodeOrder; 2173 } 2174} 2175 2176#ifndef NDEBUG 2177const char *ConvergingScheduler::getReasonStr( 2178 ConvergingScheduler::CandReason Reason) { 2179 switch (Reason) { 2180 case NoCand: return "NOCAND "; 2181 case PhysRegCopy: return "PREG-COPY"; 2182 case RegExcess: return "REG-EXCESS"; 2183 case RegCritical: return "REG-CRIT "; 2184 case Cluster: return "CLUSTER "; 2185 case Weak: return "WEAK "; 2186 case RegMax: return "REG-MAX "; 2187 case ResourceReduce: return "RES-REDUCE"; 2188 case ResourceDemand: return "RES-DEMAND"; 2189 case TopDepthReduce: return "TOP-DEPTH "; 2190 case TopPathReduce: return "TOP-PATH "; 2191 case BotHeightReduce:return "BOT-HEIGHT"; 2192 case BotPathReduce: return "BOT-PATH "; 2193 case NextDefUse: return "DEF-USE "; 2194 case NodeOrder: return "ORDER "; 2195 }; 2196 llvm_unreachable("Unknown reason!"); 2197} 2198 2199void ConvergingScheduler::traceCandidate(const SchedCandidate &Cand) { 2200 PressureElement P; 2201 unsigned ResIdx = 0; 2202 unsigned Latency = 0; 2203 switch (Cand.Reason) { 2204 default: 2205 break; 2206 case RegExcess: 2207 P = Cand.RPDelta.Excess; 2208 break; 2209 case RegCritical: 2210 P = Cand.RPDelta.CriticalMax; 2211 break; 2212 case RegMax: 2213 P = Cand.RPDelta.CurrentMax; 2214 break; 2215 case ResourceReduce: 2216 ResIdx = Cand.Policy.ReduceResIdx; 2217 break; 2218 case ResourceDemand: 2219 ResIdx = Cand.Policy.DemandResIdx; 2220 break; 2221 case TopDepthReduce: 2222 Latency = Cand.SU->getDepth(); 2223 break; 2224 case TopPathReduce: 2225 Latency = Cand.SU->getHeight(); 2226 break; 2227 case BotHeightReduce: 2228 Latency = Cand.SU->getHeight(); 2229 break; 2230 case BotPathReduce: 2231 Latency = Cand.SU->getDepth(); 2232 break; 2233 } 2234 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); 2235 if (P.isValid()) 2236 dbgs() << " " << TRI->getRegPressureSetName(P.PSetID) 2237 << ":" << P.UnitIncrease << " "; 2238 else 2239 dbgs() << " "; 2240 if (ResIdx) 2241 dbgs() << " " << SchedModel->getProcResource(ResIdx)->Name << " "; 2242 else 2243 dbgs() << " "; 2244 if (Latency) 2245 dbgs() << " " << Latency << " cycles "; 2246 else 2247 dbgs() << " "; 2248 dbgs() << '\n'; 2249} 2250#endif 2251 2252/// Pick the best candidate from the top queue. 2253/// 2254/// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during 2255/// DAG building. To adjust for the current scheduling location we need to 2256/// maintain the number of vreg uses remaining to be top-scheduled. 2257void ConvergingScheduler::pickNodeFromQueue(SchedBoundary &Zone, 2258 const RegPressureTracker &RPTracker, 2259 SchedCandidate &Cand) { 2260 ReadyQueue &Q = Zone.Available; 2261 2262 DEBUG(Q.dump()); 2263 2264 // getMaxPressureDelta temporarily modifies the tracker. 2265 RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker); 2266 2267 for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) { 2268 2269 SchedCandidate TryCand(Cand.Policy); 2270 TryCand.SU = *I; 2271 tryCandidate(Cand, TryCand, Zone, RPTracker, TempTracker); 2272 if (TryCand.Reason != NoCand) { 2273 // Initialize resource delta if needed in case future heuristics query it. 2274 if (TryCand.ResDelta == SchedResourceDelta()) 2275 TryCand.initResourceDelta(DAG, SchedModel); 2276 Cand.setBest(TryCand); 2277 DEBUG(traceCandidate(Cand)); 2278 } 2279 } 2280} 2281 2282static void tracePick(const ConvergingScheduler::SchedCandidate &Cand, 2283 bool IsTop) { 2284 DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ") 2285 << ConvergingScheduler::getReasonStr(Cand.Reason) << '\n'); 2286} 2287 2288/// Pick the best candidate node from either the top or bottom queue. 2289SUnit *ConvergingScheduler::pickNodeBidirectional(bool &IsTopNode) { 2290 // Schedule as far as possible in the direction of no choice. This is most 2291 // efficient, but also provides the best heuristics for CriticalPSets. 2292 if (SUnit *SU = Bot.pickOnlyChoice()) { 2293 IsTopNode = false; 2294 DEBUG(dbgs() << "Pick Bot NOCAND\n"); 2295 return SU; 2296 } 2297 if (SUnit *SU = Top.pickOnlyChoice()) { 2298 IsTopNode = true; 2299 DEBUG(dbgs() << "Pick Top NOCAND\n"); 2300 return SU; 2301 } 2302 CandPolicy NoPolicy; 2303 SchedCandidate BotCand(NoPolicy); 2304 SchedCandidate TopCand(NoPolicy); 2305 Bot.setPolicy(BotCand.Policy, Top); 2306 Top.setPolicy(TopCand.Policy, Bot); 2307 2308 // Prefer bottom scheduling when heuristics are silent. 2309 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand); 2310 assert(BotCand.Reason != NoCand && "failed to find the first candidate"); 2311 2312 // If either Q has a single candidate that provides the least increase in 2313 // Excess pressure, we can immediately schedule from that Q. 2314 // 2315 // RegionCriticalPSets summarizes the pressure within the scheduled region and 2316 // affects picking from either Q. If scheduling in one direction must 2317 // increase pressure for one of the excess PSets, then schedule in that 2318 // direction first to provide more freedom in the other direction. 2319 if ((BotCand.Reason == RegExcess && !BotCand.isRepeat(RegExcess)) 2320 || (BotCand.Reason == RegCritical 2321 && !BotCand.isRepeat(RegCritical))) 2322 { 2323 IsTopNode = false; 2324 tracePick(BotCand, IsTopNode); 2325 return BotCand.SU; 2326 } 2327 // Check if the top Q has a better candidate. 2328 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand); 2329 assert(TopCand.Reason != NoCand && "failed to find the first candidate"); 2330 2331 // Choose the queue with the most important (lowest enum) reason. 2332 if (TopCand.Reason < BotCand.Reason) { 2333 IsTopNode = true; 2334 tracePick(TopCand, IsTopNode); 2335 return TopCand.SU; 2336 } 2337 // Otherwise prefer the bottom candidate, in node order if all else failed. 2338 IsTopNode = false; 2339 tracePick(BotCand, IsTopNode); 2340 return BotCand.SU; 2341} 2342 2343/// Pick the best node to balance the schedule. Implements MachineSchedStrategy. 2344SUnit *ConvergingScheduler::pickNode(bool &IsTopNode) { 2345 if (DAG->top() == DAG->bottom()) { 2346 assert(Top.Available.empty() && Top.Pending.empty() && 2347 Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage"); 2348 return NULL; 2349 } 2350 SUnit *SU; 2351 do { 2352 if (ForceTopDown) { 2353 SU = Top.pickOnlyChoice(); 2354 if (!SU) { 2355 CandPolicy NoPolicy; 2356 SchedCandidate TopCand(NoPolicy); 2357 pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand); 2358 assert(TopCand.Reason != NoCand && "failed to find the first candidate"); 2359 SU = TopCand.SU; 2360 } 2361 IsTopNode = true; 2362 } 2363 else if (ForceBottomUp) { 2364 SU = Bot.pickOnlyChoice(); 2365 if (!SU) { 2366 CandPolicy NoPolicy; 2367 SchedCandidate BotCand(NoPolicy); 2368 pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand); 2369 assert(BotCand.Reason != NoCand && "failed to find the first candidate"); 2370 SU = BotCand.SU; 2371 } 2372 IsTopNode = false; 2373 } 2374 else { 2375 SU = pickNodeBidirectional(IsTopNode); 2376 } 2377 } while (SU->isScheduled); 2378 2379 if (SU->isTopReady()) 2380 Top.removeReady(SU); 2381 if (SU->isBottomReady()) 2382 Bot.removeReady(SU); 2383 2384 DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()); 2385 return SU; 2386} 2387 2388void ConvergingScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) { 2389 2390 MachineBasicBlock::iterator InsertPos = SU->getInstr(); 2391 if (!isTop) 2392 ++InsertPos; 2393 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs; 2394 2395 // Find already scheduled copies with a single physreg dependence and move 2396 // them just above the scheduled instruction. 2397 for (SmallVectorImpl<SDep>::iterator I = Deps.begin(), E = Deps.end(); 2398 I != E; ++I) { 2399 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg())) 2400 continue; 2401 SUnit *DepSU = I->getSUnit(); 2402 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1) 2403 continue; 2404 MachineInstr *Copy = DepSU->getInstr(); 2405 if (!Copy->isCopy()) 2406 continue; 2407 DEBUG(dbgs() << " Rescheduling physreg copy "; 2408 I->getSUnit()->dump(DAG)); 2409 DAG->moveInstruction(Copy, InsertPos); 2410 } 2411} 2412 2413/// Update the scheduler's state after scheduling a node. This is the same node 2414/// that was just returned by pickNode(). However, ScheduleDAGMI needs to update 2415/// it's state based on the current cycle before MachineSchedStrategy does. 2416/// 2417/// FIXME: Eventually, we may bundle physreg copies rather than rescheduling 2418/// them here. See comments in biasPhysRegCopy. 2419void ConvergingScheduler::schedNode(SUnit *SU, bool IsTopNode) { 2420 if (IsTopNode) { 2421 SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.CurrCycle); 2422 Top.bumpNode(SU); 2423 if (SU->hasPhysRegUses) 2424 reschedulePhysRegCopies(SU, true); 2425 } 2426 else { 2427 SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.CurrCycle); 2428 Bot.bumpNode(SU); 2429 if (SU->hasPhysRegDefs) 2430 reschedulePhysRegCopies(SU, false); 2431 } 2432} 2433 2434/// Create the standard converging machine scheduler. This will be used as the 2435/// default scheduler if the target does not set a default. 2436static ScheduleDAGInstrs *createConvergingSched(MachineSchedContext *C) { 2437 assert((!ForceTopDown || !ForceBottomUp) && 2438 "-misched-topdown incompatible with -misched-bottomup"); 2439 ScheduleDAGMI *DAG = new ScheduleDAGMI(C, new ConvergingScheduler()); 2440 // Register DAG post-processors. 2441 // 2442 // FIXME: extend the mutation API to allow earlier mutations to instantiate 2443 // data and pass it to later mutations. Have a single mutation that gathers 2444 // the interesting nodes in one pass. 2445 DAG->addMutation(new CopyConstrain(DAG->TII, DAG->TRI)); 2446 if (EnableLoadCluster) 2447 DAG->addMutation(new LoadClusterMutation(DAG->TII, DAG->TRI)); 2448 if (EnableMacroFusion) 2449 DAG->addMutation(new MacroFusion(DAG->TII)); 2450 return DAG; 2451} 2452static MachineSchedRegistry 2453ConvergingSchedRegistry("converge", "Standard converging scheduler.", 2454 createConvergingSched); 2455 2456//===----------------------------------------------------------------------===// 2457// ILP Scheduler. Currently for experimental analysis of heuristics. 2458//===----------------------------------------------------------------------===// 2459 2460namespace { 2461/// \brief Order nodes by the ILP metric. 2462struct ILPOrder { 2463 const SchedDFSResult *DFSResult; 2464 const BitVector *ScheduledTrees; 2465 bool MaximizeILP; 2466 2467 ILPOrder(bool MaxILP): DFSResult(0), ScheduledTrees(0), MaximizeILP(MaxILP) {} 2468 2469 /// \brief Apply a less-than relation on node priority. 2470 /// 2471 /// (Return true if A comes after B in the Q.) 2472 bool operator()(const SUnit *A, const SUnit *B) const { 2473 unsigned SchedTreeA = DFSResult->getSubtreeID(A); 2474 unsigned SchedTreeB = DFSResult->getSubtreeID(B); 2475 if (SchedTreeA != SchedTreeB) { 2476 // Unscheduled trees have lower priority. 2477 if (ScheduledTrees->test(SchedTreeA) != ScheduledTrees->test(SchedTreeB)) 2478 return ScheduledTrees->test(SchedTreeB); 2479 2480 // Trees with shallower connections have have lower priority. 2481 if (DFSResult->getSubtreeLevel(SchedTreeA) 2482 != DFSResult->getSubtreeLevel(SchedTreeB)) { 2483 return DFSResult->getSubtreeLevel(SchedTreeA) 2484 < DFSResult->getSubtreeLevel(SchedTreeB); 2485 } 2486 } 2487 if (MaximizeILP) 2488 return DFSResult->getILP(A) < DFSResult->getILP(B); 2489 else 2490 return DFSResult->getILP(A) > DFSResult->getILP(B); 2491 } 2492}; 2493 2494/// \brief Schedule based on the ILP metric. 2495class ILPScheduler : public MachineSchedStrategy { 2496 /// In case all subtrees are eventually connected to a common root through 2497 /// data dependence (e.g. reduction), place an upper limit on their size. 2498 /// 2499 /// FIXME: A subtree limit is generally good, but in the situation commented 2500 /// above, where multiple similar subtrees feed a common root, we should 2501 /// only split at a point where the resulting subtrees will be balanced. 2502 /// (a motivating test case must be found). 2503 static const unsigned SubtreeLimit = 16; 2504 2505 ScheduleDAGMI *DAG; 2506 ILPOrder Cmp; 2507 2508 std::vector<SUnit*> ReadyQ; 2509public: 2510 ILPScheduler(bool MaximizeILP): DAG(0), Cmp(MaximizeILP) {} 2511 2512 virtual void initialize(ScheduleDAGMI *dag) { 2513 DAG = dag; 2514 DAG->computeDFSResult(); 2515 Cmp.DFSResult = DAG->getDFSResult(); 2516 Cmp.ScheduledTrees = &DAG->getScheduledTrees(); 2517 ReadyQ.clear(); 2518 } 2519 2520 virtual void registerRoots() { 2521 // Restore the heap in ReadyQ with the updated DFS results. 2522 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp); 2523 } 2524 2525 /// Implement MachineSchedStrategy interface. 2526 /// ----------------------------------------- 2527 2528 /// Callback to select the highest priority node from the ready Q. 2529 virtual SUnit *pickNode(bool &IsTopNode) { 2530 if (ReadyQ.empty()) return NULL; 2531 std::pop_heap(ReadyQ.begin(), ReadyQ.end(), Cmp); 2532 SUnit *SU = ReadyQ.back(); 2533 ReadyQ.pop_back(); 2534 IsTopNode = false; 2535 DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") " 2536 << " ILP: " << DAG->getDFSResult()->getILP(SU) 2537 << " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @" 2538 << DAG->getDFSResult()->getSubtreeLevel( 2539 DAG->getDFSResult()->getSubtreeID(SU)) << '\n' 2540 << "Scheduling " << *SU->getInstr()); 2541 return SU; 2542 } 2543 2544 /// \brief Scheduler callback to notify that a new subtree is scheduled. 2545 virtual void scheduleTree(unsigned SubtreeID) { 2546 std::make_heap(ReadyQ.begin(), ReadyQ.end(), Cmp); 2547 } 2548 2549 /// Callback after a node is scheduled. Mark a newly scheduled tree, notify 2550 /// DFSResults, and resort the priority Q. 2551 virtual void schedNode(SUnit *SU, bool IsTopNode) { 2552 assert(!IsTopNode && "SchedDFSResult needs bottom-up"); 2553 } 2554 2555 virtual void releaseTopNode(SUnit *) { /*only called for top roots*/ } 2556 2557 virtual void releaseBottomNode(SUnit *SU) { 2558 ReadyQ.push_back(SU); 2559 std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp); 2560 } 2561}; 2562} // namespace 2563 2564static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) { 2565 return new ScheduleDAGMI(C, new ILPScheduler(true)); 2566} 2567static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) { 2568 return new ScheduleDAGMI(C, new ILPScheduler(false)); 2569} 2570static MachineSchedRegistry ILPMaxRegistry( 2571 "ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler); 2572static MachineSchedRegistry ILPMinRegistry( 2573 "ilpmin", "Schedule bottom-up for min ILP", createILPMinScheduler); 2574 2575//===----------------------------------------------------------------------===// 2576// Machine Instruction Shuffler for Correctness Testing 2577//===----------------------------------------------------------------------===// 2578 2579#ifndef NDEBUG 2580namespace { 2581/// Apply a less-than relation on the node order, which corresponds to the 2582/// instruction order prior to scheduling. IsReverse implements greater-than. 2583template<bool IsReverse> 2584struct SUnitOrder { 2585 bool operator()(SUnit *A, SUnit *B) const { 2586 if (IsReverse) 2587 return A->NodeNum > B->NodeNum; 2588 else 2589 return A->NodeNum < B->NodeNum; 2590 } 2591}; 2592 2593/// Reorder instructions as much as possible. 2594class InstructionShuffler : public MachineSchedStrategy { 2595 bool IsAlternating; 2596 bool IsTopDown; 2597 2598 // Using a less-than relation (SUnitOrder<false>) for the TopQ priority 2599 // gives nodes with a higher number higher priority causing the latest 2600 // instructions to be scheduled first. 2601 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> > 2602 TopQ; 2603 // When scheduling bottom-up, use greater-than as the queue priority. 2604 PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> > 2605 BottomQ; 2606public: 2607 InstructionShuffler(bool alternate, bool topdown) 2608 : IsAlternating(alternate), IsTopDown(topdown) {} 2609 2610 virtual void initialize(ScheduleDAGMI *) { 2611 TopQ.clear(); 2612 BottomQ.clear(); 2613 } 2614 2615 /// Implement MachineSchedStrategy interface. 2616 /// ----------------------------------------- 2617 2618 virtual SUnit *pickNode(bool &IsTopNode) { 2619 SUnit *SU; 2620 if (IsTopDown) { 2621 do { 2622 if (TopQ.empty()) return NULL; 2623 SU = TopQ.top(); 2624 TopQ.pop(); 2625 } while (SU->isScheduled); 2626 IsTopNode = true; 2627 } 2628 else { 2629 do { 2630 if (BottomQ.empty()) return NULL; 2631 SU = BottomQ.top(); 2632 BottomQ.pop(); 2633 } while (SU->isScheduled); 2634 IsTopNode = false; 2635 } 2636 if (IsAlternating) 2637 IsTopDown = !IsTopDown; 2638 return SU; 2639 } 2640 2641 virtual void schedNode(SUnit *SU, bool IsTopNode) {} 2642 2643 virtual void releaseTopNode(SUnit *SU) { 2644 TopQ.push(SU); 2645 } 2646 virtual void releaseBottomNode(SUnit *SU) { 2647 BottomQ.push(SU); 2648 } 2649}; 2650} // namespace 2651 2652static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) { 2653 bool Alternate = !ForceTopDown && !ForceBottomUp; 2654 bool TopDown = !ForceBottomUp; 2655 assert((TopDown || !ForceTopDown) && 2656 "-misched-topdown incompatible with -misched-bottomup"); 2657 return new ScheduleDAGMI(C, new InstructionShuffler(Alternate, TopDown)); 2658} 2659static MachineSchedRegistry ShufflerRegistry( 2660 "shuffle", "Shuffle machine instructions alternating directions", 2661 createInstructionShuffler); 2662#endif // !NDEBUG 2663 2664//===----------------------------------------------------------------------===// 2665// GraphWriter support for ScheduleDAGMI. 2666//===----------------------------------------------------------------------===// 2667 2668#ifndef NDEBUG 2669namespace llvm { 2670 2671template<> struct GraphTraits< 2672 ScheduleDAGMI*> : public GraphTraits<ScheduleDAG*> {}; 2673 2674template<> 2675struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits { 2676 2677 DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {} 2678 2679 static std::string getGraphName(const ScheduleDAG *G) { 2680 return G->MF.getName(); 2681 } 2682 2683 static bool renderGraphFromBottomUp() { 2684 return true; 2685 } 2686 2687 static bool isNodeHidden(const SUnit *Node) { 2688 return (Node->NumPreds > 10 || Node->NumSuccs > 10); 2689 } 2690 2691 static bool hasNodeAddressLabel(const SUnit *Node, 2692 const ScheduleDAG *Graph) { 2693 return false; 2694 } 2695 2696 /// If you want to override the dot attributes printed for a particular 2697 /// edge, override this method. 2698 static std::string getEdgeAttributes(const SUnit *Node, 2699 SUnitIterator EI, 2700 const ScheduleDAG *Graph) { 2701 if (EI.isArtificialDep()) 2702 return "color=cyan,style=dashed"; 2703 if (EI.isCtrlDep()) 2704 return "color=blue,style=dashed"; 2705 return ""; 2706 } 2707 2708 static std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *G) { 2709 std::string Str; 2710 raw_string_ostream SS(Str); 2711 SS << "SU(" << SU->NodeNum << ')'; 2712 return SS.str(); 2713 } 2714 static std::string getNodeDescription(const SUnit *SU, const ScheduleDAG *G) { 2715 return G->getGraphNodeLabel(SU); 2716 } 2717 2718 static std::string getNodeAttributes(const SUnit *N, 2719 const ScheduleDAG *Graph) { 2720 std::string Str("shape=Mrecord"); 2721 const SchedDFSResult *DFS = 2722 static_cast<const ScheduleDAGMI*>(Graph)->getDFSResult(); 2723 if (DFS) { 2724 Str += ",style=filled,fillcolor=\"#"; 2725 Str += DOT::getColorString(DFS->getSubtreeID(N)); 2726 Str += '"'; 2727 } 2728 return Str; 2729 } 2730}; 2731} // namespace llvm 2732#endif // NDEBUG 2733 2734/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG 2735/// rendered using 'dot'. 2736/// 2737void ScheduleDAGMI::viewGraph(const Twine &Name, const Twine &Title) { 2738#ifndef NDEBUG 2739 ViewGraph(this, Name, false, Title); 2740#else 2741 errs() << "ScheduleDAGMI::viewGraph is only available in debug builds on " 2742 << "systems with Graphviz or gv!\n"; 2743#endif // NDEBUG 2744} 2745 2746/// Out-of-line implementation with no arguments is handy for gdb. 2747void ScheduleDAGMI::viewGraph() { 2748 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName()); 2749} 2750