Passes.cpp revision b6ac11cd03e9dd97b45dc97787171f942ef8e344
1//===-- Passes.cpp - Target independent code generation passes ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines interfaces to access the target independent code 11// generation passes provided by the LLVM backend. 12// 13//===---------------------------------------------------------------------===// 14 15#include "llvm/CodeGen/Passes.h" 16#include "llvm/Analysis/Passes.h" 17#include "llvm/Analysis/Verifier.h" 18#include "llvm/Assembly/PrintModulePass.h" 19#include "llvm/CodeGen/GCStrategy.h" 20#include "llvm/CodeGen/MachineFunctionPass.h" 21#include "llvm/CodeGen/RegAllocRegistry.h" 22#include "llvm/MC/MCAsmInfo.h" 23#include "llvm/PassManager.h" 24#include "llvm/Support/CommandLine.h" 25#include "llvm/Support/Debug.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetSubtargetInfo.h" 29#include "llvm/Transforms/Scalar.h" 30 31using namespace llvm; 32 33static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, 34 cl::desc("Disable Post Regalloc")); 35static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 36 cl::desc("Disable branch folding")); 37static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 38 cl::desc("Disable tail duplication")); 39static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 40 cl::desc("Disable pre-register allocation tail duplication")); 41static cl::opt<bool> DisableBlockPlacement("disable-block-placement", 42 cl::Hidden, cl::desc("Disable probability-driven block placement")); 43static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", 44 cl::Hidden, cl::desc("Collect probability-driven block placement stats")); 45static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 46 cl::desc("Disable Stack Slot Coloring")); 47static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, 48 cl::desc("Disable Machine Dead Code Elimination")); 49static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, 50 cl::desc("Disable Early If-conversion")); 51static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 52 cl::desc("Disable Machine LICM")); 53static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, 54 cl::desc("Disable Machine Common Subexpression Elimination")); 55static cl::opt<cl::boolOrDefault> 56OptimizeRegAlloc("optimize-regalloc", cl::Hidden, 57 cl::desc("Enable optimized register allocation compilation path.")); 58static cl::opt<cl::boolOrDefault> 59EnableMachineSched("enable-misched", cl::Hidden, 60 cl::desc("Enable the machine instruction scheduling pass.")); 61static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden, 62 cl::desc("Use strong PHI elimination.")); 63static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", 64 cl::Hidden, 65 cl::desc("Disable Machine LICM")); 66static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 67 cl::desc("Disable Machine Sinking")); 68static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 69 cl::desc("Disable Loop Strength Reduction Pass")); 70static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 71 cl::desc("Disable Codegen Prepare")); 72static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, 73 cl::desc("Disable Copy Propagation pass")); 74static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 75 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 76static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 77 cl::desc("Print LLVM IR input to isel pass")); 78static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 79 cl::desc("Dump garbage collector data")); 80static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, 81 cl::desc("Verify generated machine code"), 82 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); 83static cl::opt<std::string> 84PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, 85 cl::desc("Print machine instrs"), 86 cl::value_desc("pass-name"), cl::init("option-unspecified")); 87 88// Experimental option to run live interval analysis early. 89static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden, 90 cl::desc("Run live interval analysis earlier in the pipeline")); 91 92/// Allow standard passes to be disabled by command line options. This supports 93/// simple binary flags that either suppress the pass or do nothing. 94/// i.e. -disable-mypass=false has no effect. 95/// These should be converted to boolOrDefault in order to use applyOverride. 96static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, 97 bool Override) { 98 if (Override) 99 return IdentifyingPassPtr(); 100 return PassID; 101} 102 103/// Allow Pass selection to be overriden by command line options. This supports 104/// flags with ternary conditions. TargetID is passed through by default. The 105/// pass is suppressed when the option is false. When the option is true, the 106/// StandardID is selected if the target provides no default. 107static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID, 108 cl::boolOrDefault Override, 109 AnalysisID StandardID) { 110 switch (Override) { 111 case cl::BOU_UNSET: 112 return TargetID; 113 case cl::BOU_TRUE: 114 if (TargetID.isValid()) 115 return TargetID; 116 if (StandardID == 0) 117 report_fatal_error("Target cannot enable pass"); 118 return StandardID; 119 case cl::BOU_FALSE: 120 return IdentifyingPassPtr(); 121 } 122 llvm_unreachable("Invalid command line option state"); 123} 124 125/// Allow standard passes to be disabled by the command line, regardless of who 126/// is adding the pass. 127/// 128/// StandardID is the pass identified in the standard pass pipeline and provided 129/// to addPass(). It may be a target-specific ID in the case that the target 130/// directly adds its own pass, but in that case we harmlessly fall through. 131/// 132/// TargetID is the pass that the target has configured to override StandardID. 133/// 134/// StandardID may be a pseudo ID. In that case TargetID is the name of the real 135/// pass to run. This allows multiple options to control a single pass depending 136/// on where in the pipeline that pass is added. 137static IdentifyingPassPtr overridePass(AnalysisID StandardID, 138 IdentifyingPassPtr TargetID) { 139 if (StandardID == &PostRASchedulerID) 140 return applyDisable(TargetID, DisablePostRA); 141 142 if (StandardID == &BranchFolderPassID) 143 return applyDisable(TargetID, DisableBranchFold); 144 145 if (StandardID == &TailDuplicateID) 146 return applyDisable(TargetID, DisableTailDuplicate); 147 148 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID) 149 return applyDisable(TargetID, DisableEarlyTailDup); 150 151 if (StandardID == &MachineBlockPlacementID) 152 return applyDisable(TargetID, DisableBlockPlacement); 153 154 if (StandardID == &StackSlotColoringID) 155 return applyDisable(TargetID, DisableSSC); 156 157 if (StandardID == &DeadMachineInstructionElimID) 158 return applyDisable(TargetID, DisableMachineDCE); 159 160 if (StandardID == &EarlyIfConverterID) 161 return applyDisable(TargetID, DisableEarlyIfConversion); 162 163 if (StandardID == &MachineLICMID) 164 return applyDisable(TargetID, DisableMachineLICM); 165 166 if (StandardID == &MachineCSEID) 167 return applyDisable(TargetID, DisableMachineCSE); 168 169 if (StandardID == &MachineSchedulerID) 170 return applyOverride(TargetID, EnableMachineSched, StandardID); 171 172 if (StandardID == &TargetPassConfig::PostRAMachineLICMID) 173 return applyDisable(TargetID, DisablePostRAMachineLICM); 174 175 if (StandardID == &MachineSinkingID) 176 return applyDisable(TargetID, DisableMachineSink); 177 178 if (StandardID == &MachineCopyPropagationID) 179 return applyDisable(TargetID, DisableCopyProp); 180 181 return TargetID; 182} 183 184//===---------------------------------------------------------------------===// 185/// TargetPassConfig 186//===---------------------------------------------------------------------===// 187 188INITIALIZE_PASS(TargetPassConfig, "targetpassconfig", 189 "Target Pass Configuration", false, false) 190char TargetPassConfig::ID = 0; 191 192// Pseudo Pass IDs. 193char TargetPassConfig::EarlyTailDuplicateID = 0; 194char TargetPassConfig::PostRAMachineLICMID = 0; 195 196namespace llvm { 197class PassConfigImpl { 198public: 199 // List of passes explicitly substituted by this target. Normally this is 200 // empty, but it is a convenient way to suppress or replace specific passes 201 // that are part of a standard pass pipeline without overridding the entire 202 // pipeline. This mechanism allows target options to inherit a standard pass's 203 // user interface. For example, a target may disable a standard pass by 204 // default by substituting a pass ID of zero, and the user may still enable 205 // that standard pass with an explicit command line option. 206 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses; 207 208 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass 209 /// is inserted after each instance of the first one. 210 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses; 211}; 212} // namespace llvm 213 214// Out of line virtual method. 215TargetPassConfig::~TargetPassConfig() { 216 delete Impl; 217} 218 219// Out of line constructor provides default values for pass options and 220// registers all common codegen passes. 221TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) 222 : ImmutablePass(ID), PM(&pm), StartAfter(0), StopAfter(0), 223 Started(true), Stopped(false), TM(tm), Impl(0), Initialized(false), 224 DisableVerify(false), 225 EnableTailMerge(true) { 226 227 Impl = new PassConfigImpl(); 228 229 // Register all target independent codegen passes to activate their PassIDs, 230 // including this pass itself. 231 initializeCodeGen(*PassRegistry::getPassRegistry()); 232 233 // Substitute Pseudo Pass IDs for real ones. 234 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID); 235 substitutePass(&PostRAMachineLICMID, &MachineLICMID); 236 237 // Temporarily disable experimental passes. 238 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>(); 239 if (!ST.useMachineScheduler()) 240 disablePass(&MachineSchedulerID); 241} 242 243/// Insert InsertedPassID pass after TargetPassID. 244void TargetPassConfig::insertPass(AnalysisID TargetPassID, 245 IdentifyingPassPtr InsertedPassID) { 246 assert(((!InsertedPassID.isInstance() && 247 TargetPassID != InsertedPassID.getID()) || 248 (InsertedPassID.isInstance() && 249 TargetPassID != InsertedPassID.getInstance()->getPassID())) && 250 "Insert a pass after itself!"); 251 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID); 252 Impl->InsertedPasses.push_back(P); 253} 254 255/// createPassConfig - Create a pass configuration object to be used by 256/// addPassToEmitX methods for generating a pipeline of CodeGen passes. 257/// 258/// Targets may override this to extend TargetPassConfig. 259TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 260 return new TargetPassConfig(this, PM); 261} 262 263TargetPassConfig::TargetPassConfig() 264 : ImmutablePass(ID), PM(0) { 265 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); 266} 267 268// Helper to verify the analysis is really immutable. 269void TargetPassConfig::setOpt(bool &Opt, bool Val) { 270 assert(!Initialized && "PassConfig is immutable"); 271 Opt = Val; 272} 273 274void TargetPassConfig::substitutePass(AnalysisID StandardID, 275 IdentifyingPassPtr TargetID) { 276 Impl->TargetPasses[StandardID] = TargetID; 277} 278 279IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const { 280 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator 281 I = Impl->TargetPasses.find(ID); 282 if (I == Impl->TargetPasses.end()) 283 return ID; 284 return I->second; 285} 286 287/// Add a pass to the PassManager if that pass is supposed to be run. If the 288/// Started/Stopped flags indicate either that the compilation should start at 289/// a later pass or that it should stop after an earlier pass, then do not add 290/// the pass. Finally, compare the current pass against the StartAfter 291/// and StopAfter options and change the Started/Stopped flags accordingly. 292void TargetPassConfig::addPass(Pass *P) { 293 assert(!Initialized && "PassConfig is immutable"); 294 295 // Cache the Pass ID here in case the pass manager finds this pass is 296 // redundant with ones already scheduled / available, and deletes it. 297 // Fundamentally, once we add the pass to the manager, we no longer own it 298 // and shouldn't reference it. 299 AnalysisID PassID = P->getPassID(); 300 301 if (Started && !Stopped) 302 PM->add(P); 303 else 304 delete P; 305 if (StopAfter == PassID) 306 Stopped = true; 307 if (StartAfter == PassID) 308 Started = true; 309 if (Stopped && !Started) 310 report_fatal_error("Cannot stop compilation after pass that is not run"); 311} 312 313/// Add a CodeGen pass at this point in the pipeline after checking for target 314/// and command line overrides. 315/// 316/// addPass cannot return a pointer to the pass instance because is internal the 317/// PassManager and the instance we create here may already be freed. 318AnalysisID TargetPassConfig::addPass(AnalysisID PassID) { 319 IdentifyingPassPtr TargetID = getPassSubstitution(PassID); 320 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); 321 if (!FinalPtr.isValid()) 322 return 0; 323 324 Pass *P; 325 if (FinalPtr.isInstance()) 326 P = FinalPtr.getInstance(); 327 else { 328 P = Pass::createPass(FinalPtr.getID()); 329 if (!P) 330 llvm_unreachable("Pass ID not registered"); 331 } 332 AnalysisID FinalID = P->getPassID(); 333 addPass(P); // Ends the lifetime of P. 334 335 // Add the passes after the pass P if there is any. 336 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator 337 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end(); 338 I != E; ++I) { 339 if ((*I).first == PassID) { 340 assert((*I).second.isValid() && "Illegal Pass ID!"); 341 Pass *NP; 342 if ((*I).second.isInstance()) 343 NP = (*I).second.getInstance(); 344 else { 345 NP = Pass::createPass((*I).second.getID()); 346 assert(NP && "Pass ID not registered"); 347 } 348 addPass(NP); 349 } 350 } 351 return FinalID; 352} 353 354void TargetPassConfig::printAndVerify(const char *Banner) { 355 if (TM->shouldPrintMachineCode()) 356 addPass(createMachineFunctionPrinterPass(dbgs(), Banner)); 357 358 if (VerifyMachineCode) 359 addPass(createMachineVerifierPass(Banner)); 360} 361 362/// Add common target configurable passes that perform LLVM IR to IR transforms 363/// following machine independent optimization. 364void TargetPassConfig::addIRPasses() { 365 // Basic AliasAnalysis support. 366 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 367 // BasicAliasAnalysis wins if they disagree. This is intended to help 368 // support "obvious" type-punning idioms. 369 addPass(createTypeBasedAliasAnalysisPass()); 370 addPass(createBasicAliasAnalysisPass()); 371 372 // Before running any passes, run the verifier to determine if the input 373 // coming from the front-end and/or optimizer is valid. 374 if (!DisableVerify) 375 addPass(createVerifierPass()); 376 377 // Run loop strength reduction before anything else. 378 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { 379 addPass(createLoopStrengthReducePass()); 380 if (PrintLSR) 381 addPass(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); 382 } 383 384 addPass(createGCLoweringPass()); 385 386 // Make sure that no unreachable blocks are instruction selected. 387 addPass(createUnreachableBlockEliminationPass()); 388} 389 390/// Turn exception handling constructs into something the code generators can 391/// handle. 392void TargetPassConfig::addPassesToHandleExceptions() { 393 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { 394 case ExceptionHandling::SjLj: 395 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 396 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 397 // catch info can get misplaced when a selector ends up more than one block 398 // removed from the parent invoke(s). This could happen when a landing 399 // pad is shared by multiple invokes and is also a target of a normal 400 // edge from elsewhere. 401 addPass(createSjLjEHPreparePass(TM)); 402 // FALLTHROUGH 403 case ExceptionHandling::DwarfCFI: 404 case ExceptionHandling::ARM: 405 case ExceptionHandling::Win64: 406 addPass(createDwarfEHPass(TM)); 407 break; 408 case ExceptionHandling::None: 409 addPass(createLowerInvokePass(TM)); 410 411 // The lower invoke pass may create unreachable code. Remove it. 412 addPass(createUnreachableBlockEliminationPass()); 413 break; 414 } 415} 416 417/// Add pass to prepare the LLVM IR for code generation. This should be done 418/// before exception handling preparation passes. 419void TargetPassConfig::addCodeGenPrepare() { 420 if (getOptLevel() != CodeGenOpt::None && !DisableCGP) 421 addPass(createCodeGenPreparePass(TM)); 422} 423 424/// Add common passes that perform LLVM IR to IR transforms in preparation for 425/// instruction selection. 426void TargetPassConfig::addISelPrepare() { 427 addPass(createStackProtectorPass(TM)); 428 429 addPreISel(); 430 431 if (PrintISelInput) 432 addPass(createPrintFunctionPass("\n\n" 433 "*** Final LLVM Code input to ISel ***\n", 434 &dbgs())); 435 436 // All passes which modify the LLVM IR are now complete; run the verifier 437 // to ensure that the IR is valid. 438 if (!DisableVerify) 439 addPass(createVerifierPass()); 440} 441 442/// Add the complete set of target-independent postISel code generator passes. 443/// 444/// This can be read as the standard order of major LLVM CodeGen stages. Stages 445/// with nontrivial configuration or multiple passes are broken out below in 446/// add%Stage routines. 447/// 448/// Any TargetPassConfig::addXX routine may be overriden by the Target. The 449/// addPre/Post methods with empty header implementations allow injecting 450/// target-specific fixups just before or after major stages. Additionally, 451/// targets have the flexibility to change pass order within a stage by 452/// overriding default implementation of add%Stage routines below. Each 453/// technique has maintainability tradeoffs because alternate pass orders are 454/// not well supported. addPre/Post works better if the target pass is easily 455/// tied to a common pass. But if it has subtle dependencies on multiple passes, 456/// the target should override the stage instead. 457/// 458/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection 459/// before/after any target-independent pass. But it's currently overkill. 460void TargetPassConfig::addMachinePasses() { 461 // Insert a machine instr printer pass after the specified pass. 462 // If -print-machineinstrs specified, print machineinstrs after all passes. 463 if (StringRef(PrintMachineInstrs.getValue()).equals("")) 464 TM->Options.PrintMachineCode = true; 465 else if (!StringRef(PrintMachineInstrs.getValue()) 466 .equals("option-unspecified")) { 467 const PassRegistry *PR = PassRegistry::getPassRegistry(); 468 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue()); 469 const PassInfo *IPI = PR->getPassInfo(StringRef("print-machineinstrs")); 470 assert (TPI && IPI && "Pass ID not registered!"); 471 const char *TID = (const char *)(TPI->getTypeInfo()); 472 const char *IID = (const char *)(IPI->getTypeInfo()); 473 insertPass(TID, IID); 474 } 475 476 // Print the instruction selected machine code... 477 printAndVerify("After Instruction Selection"); 478 479 // Expand pseudo-instructions emitted by ISel. 480 if (addPass(&ExpandISelPseudosID)) 481 printAndVerify("After ExpandISelPseudos"); 482 483 // Add passes that optimize machine instructions in SSA form. 484 if (getOptLevel() != CodeGenOpt::None) { 485 addMachineSSAOptimization(); 486 } else { 487 // If the target requests it, assign local variables to stack slots relative 488 // to one another and simplify frame index references where possible. 489 addPass(&LocalStackSlotAllocationID); 490 } 491 492 // Run pre-ra passes. 493 if (addPreRegAlloc()) 494 printAndVerify("After PreRegAlloc passes"); 495 496 // Run register allocation and passes that are tightly coupled with it, 497 // including phi elimination and scheduling. 498 if (getOptimizeRegAlloc()) 499 addOptimizedRegAlloc(createRegAllocPass(true)); 500 else 501 addFastRegAlloc(createRegAllocPass(false)); 502 503 // Run post-ra passes. 504 if (addPostRegAlloc()) 505 printAndVerify("After PostRegAlloc passes"); 506 507 // Insert prolog/epilog code. Eliminate abstract frame index references... 508 addPass(&PrologEpilogCodeInserterID); 509 printAndVerify("After PrologEpilogCodeInserter"); 510 511 /// Add passes that optimize machine instructions after register allocation. 512 if (getOptLevel() != CodeGenOpt::None) 513 addMachineLateOptimization(); 514 515 // Expand pseudo instructions before second scheduling pass. 516 addPass(&ExpandPostRAPseudosID); 517 printAndVerify("After ExpandPostRAPseudos"); 518 519 // Run pre-sched2 passes. 520 if (addPreSched2()) 521 printAndVerify("After PreSched2 passes"); 522 523 // Second pass scheduler. 524 if (getOptLevel() != CodeGenOpt::None) { 525 addPass(&PostRASchedulerID); 526 printAndVerify("After PostRAScheduler"); 527 } 528 529 // GC 530 if (addGCPasses()) { 531 if (PrintGCInfo) 532 addPass(createGCInfoPrinter(dbgs())); 533 } 534 535 // Basic block placement. 536 if (getOptLevel() != CodeGenOpt::None) 537 addBlockPlacement(); 538 539 if (addPreEmitPass()) 540 printAndVerify("After PreEmit passes"); 541} 542 543/// Add passes that optimize machine instructions in SSA form. 544void TargetPassConfig::addMachineSSAOptimization() { 545 // Pre-ra tail duplication. 546 if (addPass(&EarlyTailDuplicateID)) 547 printAndVerify("After Pre-RegAlloc TailDuplicate"); 548 549 // Optimize PHIs before DCE: removing dead PHI cycles may make more 550 // instructions dead. 551 addPass(&OptimizePHIsID); 552 553 // This pass merges large allocas. StackSlotColoring is a different pass 554 // which merges spill slots. 555 addPass(&StackColoringID); 556 557 // If the target requests it, assign local variables to stack slots relative 558 // to one another and simplify frame index references where possible. 559 addPass(&LocalStackSlotAllocationID); 560 561 // With optimization, dead code should already be eliminated. However 562 // there is one known exception: lowered code for arguments that are only 563 // used by tail calls, where the tail calls reuse the incoming stack 564 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 565 addPass(&DeadMachineInstructionElimID); 566 printAndVerify("After codegen DCE pass"); 567 568 // Allow targets to insert passes that improve instruction level parallelism, 569 // like if-conversion. Such passes will typically need dominator trees and 570 // loop info, just like LICM and CSE below. 571 if (addILPOpts()) 572 printAndVerify("After ILP optimizations"); 573 574 addPass(&MachineLICMID); 575 addPass(&MachineCSEID); 576 addPass(&MachineSinkingID); 577 printAndVerify("After Machine LICM, CSE and Sinking passes"); 578 579 addPass(&PeepholeOptimizerID); 580 printAndVerify("After codegen peephole optimization pass"); 581} 582 583//===---------------------------------------------------------------------===// 584/// Register Allocation Pass Configuration 585//===---------------------------------------------------------------------===// 586 587bool TargetPassConfig::getOptimizeRegAlloc() const { 588 switch (OptimizeRegAlloc) { 589 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; 590 case cl::BOU_TRUE: return true; 591 case cl::BOU_FALSE: return false; 592 } 593 llvm_unreachable("Invalid optimize-regalloc state"); 594} 595 596/// RegisterRegAlloc's global Registry tracks allocator registration. 597MachinePassRegistry RegisterRegAlloc::Registry; 598 599/// A dummy default pass factory indicates whether the register allocator is 600/// overridden on the command line. 601static FunctionPass *useDefaultRegisterAllocator() { return 0; } 602static RegisterRegAlloc 603defaultRegAlloc("default", 604 "pick register allocator based on -O option", 605 useDefaultRegisterAllocator); 606 607/// -regalloc=... command line option. 608static cl::opt<RegisterRegAlloc::FunctionPassCtor, false, 609 RegisterPassParser<RegisterRegAlloc> > 610RegAlloc("regalloc", 611 cl::init(&useDefaultRegisterAllocator), 612 cl::desc("Register allocator to use")); 613 614 615/// Instantiate the default register allocator pass for this target for either 616/// the optimized or unoptimized allocation path. This will be added to the pass 617/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 618/// in the optimized case. 619/// 620/// A target that uses the standard regalloc pass order for fast or optimized 621/// allocation may still override this for per-target regalloc 622/// selection. But -regalloc=... always takes precedence. 623FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { 624 if (Optimized) 625 return createGreedyRegisterAllocator(); 626 else 627 return createFastRegisterAllocator(); 628} 629 630/// Find and instantiate the register allocation pass requested by this target 631/// at the current optimization level. Different register allocators are 632/// defined as separate passes because they may require different analysis. 633/// 634/// This helper ensures that the regalloc= option is always available, 635/// even for targets that override the default allocator. 636/// 637/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, 638/// this can be folded into addPass. 639FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { 640 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 641 642 // Initialize the global default. 643 if (!Ctor) { 644 Ctor = RegAlloc; 645 RegisterRegAlloc::setDefault(RegAlloc); 646 } 647 if (Ctor != useDefaultRegisterAllocator) 648 return Ctor(); 649 650 // With no -regalloc= override, ask the target for a regalloc pass. 651 return createTargetRegisterAllocator(Optimized); 652} 653 654/// Add the minimum set of target-independent passes that are required for 655/// register allocation. No coalescing or scheduling. 656void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { 657 addPass(&PHIEliminationID); 658 addPass(&TwoAddressInstructionPassID); 659 660 addPass(RegAllocPass); 661 printAndVerify("After Register Allocation"); 662} 663 664/// Add standard target-independent passes that are tightly coupled with 665/// optimized register allocation, including coalescing, machine instruction 666/// scheduling, and register allocation itself. 667void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { 668 addPass(&ProcessImplicitDefsID); 669 670 // LiveVariables currently requires pure SSA form. 671 // 672 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, 673 // LiveVariables can be removed completely, and LiveIntervals can be directly 674 // computed. (We still either need to regenerate kill flags after regalloc, or 675 // preferably fix the scavenger to not depend on them). 676 addPass(&LiveVariablesID); 677 678 // Add passes that move from transformed SSA into conventional SSA. This is a 679 // "copy coalescing" problem. 680 // 681 if (!EnableStrongPHIElim) { 682 // Edge splitting is smarter with machine loop info. 683 addPass(&MachineLoopInfoID); 684 addPass(&PHIEliminationID); 685 } 686 687 // Eventually, we want to run LiveIntervals before PHI elimination. 688 if (EarlyLiveIntervals) 689 addPass(&LiveIntervalsID); 690 691 addPass(&TwoAddressInstructionPassID); 692 693 if (EnableStrongPHIElim) 694 addPass(&StrongPHIEliminationID); 695 696 addPass(&RegisterCoalescerID); 697 698 // PreRA instruction scheduling. 699 if (addPass(&MachineSchedulerID)) 700 printAndVerify("After Machine Scheduling"); 701 702 // Add the selected register allocation pass. 703 addPass(RegAllocPass); 704 printAndVerify("After Register Allocation, before rewriter"); 705 706 // Allow targets to change the register assignments before rewriting. 707 if (addPreRewrite()) 708 printAndVerify("After pre-rewrite passes"); 709 710 // Finally rewrite virtual registers. 711 addPass(&VirtRegRewriterID); 712 printAndVerify("After Virtual Register Rewriter"); 713 714 // Perform stack slot coloring and post-ra machine LICM. 715 // 716 // FIXME: Re-enable coloring with register when it's capable of adding 717 // kill markers. 718 addPass(&StackSlotColoringID); 719 720 // Run post-ra machine LICM to hoist reloads / remats. 721 // 722 // FIXME: can this move into MachineLateOptimization? 723 addPass(&PostRAMachineLICMID); 724 725 printAndVerify("After StackSlotColoring and postra Machine LICM"); 726} 727 728//===---------------------------------------------------------------------===// 729/// Post RegAlloc Pass Configuration 730//===---------------------------------------------------------------------===// 731 732/// Add passes that optimize machine instructions after register allocation. 733void TargetPassConfig::addMachineLateOptimization() { 734 // Branch folding must be run after regalloc and prolog/epilog insertion. 735 if (addPass(&BranchFolderPassID)) 736 printAndVerify("After BranchFolding"); 737 738 // Tail duplication. 739 if (addPass(&TailDuplicateID)) 740 printAndVerify("After TailDuplicate"); 741 742 // Copy propagation. 743 if (addPass(&MachineCopyPropagationID)) 744 printAndVerify("After copy propagation pass"); 745} 746 747/// Add standard GC passes. 748bool TargetPassConfig::addGCPasses() { 749 addPass(&GCMachineCodeAnalysisID); 750 return true; 751} 752 753/// Add standard basic block placement passes. 754void TargetPassConfig::addBlockPlacement() { 755 if (addPass(&MachineBlockPlacementID)) { 756 // Run a separate pass to collect block placement statistics. 757 if (EnableBlockPlacementStats) 758 addPass(&MachineBlockPlacementStatsID); 759 760 printAndVerify("After machine block placement."); 761 } 762} 763