Passes.cpp revision f22fd3f7b557a967b1edc1fa9ae770006a39e97c
1//===-- Passes.cpp - Target independent code generation passes ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines interfaces to access the target independent code 11// generation passes provided by the LLVM backend. 12// 13//===---------------------------------------------------------------------===// 14 15#include "llvm/CodeGen/Passes.h" 16#include "llvm/Analysis/Passes.h" 17#include "llvm/Analysis/Verifier.h" 18#include "llvm/Assembly/PrintModulePass.h" 19#include "llvm/CodeGen/GCStrategy.h" 20#include "llvm/CodeGen/MachineFunctionPass.h" 21#include "llvm/CodeGen/RegAllocRegistry.h" 22#include "llvm/MC/MCAsmInfo.h" 23#include "llvm/PassManager.h" 24#include "llvm/Support/CommandLine.h" 25#include "llvm/Support/Debug.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetSubtargetInfo.h" 29#include "llvm/Transforms/Scalar.h" 30 31using namespace llvm; 32 33static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, 34 cl::desc("Disable Post Regalloc")); 35static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 36 cl::desc("Disable branch folding")); 37static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 38 cl::desc("Disable tail duplication")); 39static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 40 cl::desc("Disable pre-register allocation tail duplication")); 41static cl::opt<bool> DisableBlockPlacement("disable-block-placement", 42 cl::Hidden, cl::desc("Disable probability-driven block placement")); 43static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", 44 cl::Hidden, cl::desc("Collect probability-driven block placement stats")); 45static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 46 cl::desc("Disable Stack Slot Coloring")); 47static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, 48 cl::desc("Disable Machine Dead Code Elimination")); 49static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, 50 cl::desc("Disable Early If-conversion")); 51static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 52 cl::desc("Disable Machine LICM")); 53static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, 54 cl::desc("Disable Machine Common Subexpression Elimination")); 55static cl::opt<cl::boolOrDefault> 56OptimizeRegAlloc("optimize-regalloc", cl::Hidden, 57 cl::desc("Enable optimized register allocation compilation path.")); 58static cl::opt<cl::boolOrDefault> 59EnableMachineSched("enable-misched", cl::Hidden, 60 cl::desc("Enable the machine instruction scheduling pass.")); 61static cl::opt<bool> EnableStrongPHIElim("strong-phi-elim", cl::Hidden, 62 cl::desc("Use strong PHI elimination.")); 63static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", 64 cl::Hidden, 65 cl::desc("Disable Machine LICM")); 66static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 67 cl::desc("Disable Machine Sinking")); 68static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 69 cl::desc("Disable Loop Strength Reduction Pass")); 70static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 71 cl::desc("Disable Codegen Prepare")); 72static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, 73 cl::desc("Disable Copy Propagation pass")); 74static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 75 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 76static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 77 cl::desc("Print LLVM IR input to isel pass")); 78static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 79 cl::desc("Dump garbage collector data")); 80static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, 81 cl::desc("Verify generated machine code"), 82 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL)); 83static cl::opt<std::string> 84PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, 85 cl::desc("Print machine instrs"), 86 cl::value_desc("pass-name"), cl::init("option-unspecified")); 87 88// Experimental option to run live interval analysis early. 89static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden, 90 cl::desc("Run live interval analysis earlier in the pipeline")); 91 92/// Allow standard passes to be disabled by command line options. This supports 93/// simple binary flags that either suppress the pass or do nothing. 94/// i.e. -disable-mypass=false has no effect. 95/// These should be converted to boolOrDefault in order to use applyOverride. 96static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, 97 bool Override) { 98 if (Override) 99 return IdentifyingPassPtr(); 100 return PassID; 101} 102 103/// Allow Pass selection to be overriden by command line options. This supports 104/// flags with ternary conditions. TargetID is passed through by default. The 105/// pass is suppressed when the option is false. When the option is true, the 106/// StandardID is selected if the target provides no default. 107static IdentifyingPassPtr applyOverride(IdentifyingPassPtr TargetID, 108 cl::boolOrDefault Override, 109 AnalysisID StandardID) { 110 switch (Override) { 111 case cl::BOU_UNSET: 112 return TargetID; 113 case cl::BOU_TRUE: 114 if (TargetID.isValid()) 115 return TargetID; 116 if (StandardID == 0) 117 report_fatal_error("Target cannot enable pass"); 118 return StandardID; 119 case cl::BOU_FALSE: 120 return IdentifyingPassPtr(); 121 } 122 llvm_unreachable("Invalid command line option state"); 123} 124 125/// Allow standard passes to be disabled by the command line, regardless of who 126/// is adding the pass. 127/// 128/// StandardID is the pass identified in the standard pass pipeline and provided 129/// to addPass(). It may be a target-specific ID in the case that the target 130/// directly adds its own pass, but in that case we harmlessly fall through. 131/// 132/// TargetID is the pass that the target has configured to override StandardID. 133/// 134/// StandardID may be a pseudo ID. In that case TargetID is the name of the real 135/// pass to run. This allows multiple options to control a single pass depending 136/// on where in the pipeline that pass is added. 137static IdentifyingPassPtr overridePass(AnalysisID StandardID, 138 IdentifyingPassPtr TargetID) { 139 if (StandardID == &PostRASchedulerID) 140 return applyDisable(TargetID, DisablePostRA); 141 142 if (StandardID == &BranchFolderPassID) 143 return applyDisable(TargetID, DisableBranchFold); 144 145 if (StandardID == &TailDuplicateID) 146 return applyDisable(TargetID, DisableTailDuplicate); 147 148 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID) 149 return applyDisable(TargetID, DisableEarlyTailDup); 150 151 if (StandardID == &MachineBlockPlacementID) 152 return applyDisable(TargetID, DisableBlockPlacement); 153 154 if (StandardID == &StackSlotColoringID) 155 return applyDisable(TargetID, DisableSSC); 156 157 if (StandardID == &DeadMachineInstructionElimID) 158 return applyDisable(TargetID, DisableMachineDCE); 159 160 if (StandardID == &EarlyIfConverterID) 161 return applyDisable(TargetID, DisableEarlyIfConversion); 162 163 if (StandardID == &MachineLICMID) 164 return applyDisable(TargetID, DisableMachineLICM); 165 166 if (StandardID == &MachineCSEID) 167 return applyDisable(TargetID, DisableMachineCSE); 168 169 if (StandardID == &MachineSchedulerID) 170 return applyOverride(TargetID, EnableMachineSched, StandardID); 171 172 if (StandardID == &TargetPassConfig::PostRAMachineLICMID) 173 return applyDisable(TargetID, DisablePostRAMachineLICM); 174 175 if (StandardID == &MachineSinkingID) 176 return applyDisable(TargetID, DisableMachineSink); 177 178 if (StandardID == &MachineCopyPropagationID) 179 return applyDisable(TargetID, DisableCopyProp); 180 181 return TargetID; 182} 183 184//===---------------------------------------------------------------------===// 185/// TargetPassConfig 186//===---------------------------------------------------------------------===// 187 188INITIALIZE_PASS(TargetPassConfig, "targetpassconfig", 189 "Target Pass Configuration", false, false) 190char TargetPassConfig::ID = 0; 191 192// Pseudo Pass IDs. 193char TargetPassConfig::EarlyTailDuplicateID = 0; 194char TargetPassConfig::PostRAMachineLICMID = 0; 195 196namespace llvm { 197class PassConfigImpl { 198public: 199 // List of passes explicitly substituted by this target. Normally this is 200 // empty, but it is a convenient way to suppress or replace specific passes 201 // that are part of a standard pass pipeline without overridding the entire 202 // pipeline. This mechanism allows target options to inherit a standard pass's 203 // user interface. For example, a target may disable a standard pass by 204 // default by substituting a pass ID of zero, and the user may still enable 205 // that standard pass with an explicit command line option. 206 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses; 207 208 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass 209 /// is inserted after each instance of the first one. 210 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses; 211}; 212} // namespace llvm 213 214// Out of line virtual method. 215TargetPassConfig::~TargetPassConfig() { 216 delete Impl; 217} 218 219// Out of line constructor provides default values for pass options and 220// registers all common codegen passes. 221TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) 222 : ImmutablePass(ID), PM(&pm), StartAfter(0), StopAfter(0), 223 Started(true), Stopped(false), TM(tm), Impl(0), Initialized(false), 224 DisableVerify(false), 225 EnableTailMerge(true) { 226 227 Impl = new PassConfigImpl(); 228 229 // Register all target independent codegen passes to activate their PassIDs, 230 // including this pass itself. 231 initializeCodeGen(*PassRegistry::getPassRegistry()); 232 233 // Substitute Pseudo Pass IDs for real ones. 234 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID); 235 substitutePass(&PostRAMachineLICMID, &MachineLICMID); 236 237 // Temporarily disable experimental passes. 238 const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>(); 239 if (!ST.enableMachineScheduler()) 240 disablePass(&MachineSchedulerID); 241} 242 243/// Insert InsertedPassID pass after TargetPassID. 244void TargetPassConfig::insertPass(AnalysisID TargetPassID, 245 IdentifyingPassPtr InsertedPassID) { 246 assert(((!InsertedPassID.isInstance() && 247 TargetPassID != InsertedPassID.getID()) || 248 (InsertedPassID.isInstance() && 249 TargetPassID != InsertedPassID.getInstance()->getPassID())) && 250 "Insert a pass after itself!"); 251 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID); 252 Impl->InsertedPasses.push_back(P); 253} 254 255/// createPassConfig - Create a pass configuration object to be used by 256/// addPassToEmitX methods for generating a pipeline of CodeGen passes. 257/// 258/// Targets may override this to extend TargetPassConfig. 259TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 260 return new TargetPassConfig(this, PM); 261} 262 263TargetPassConfig::TargetPassConfig() 264 : ImmutablePass(ID), PM(0) { 265 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); 266} 267 268// Helper to verify the analysis is really immutable. 269void TargetPassConfig::setOpt(bool &Opt, bool Val) { 270 assert(!Initialized && "PassConfig is immutable"); 271 Opt = Val; 272} 273 274void TargetPassConfig::substitutePass(AnalysisID StandardID, 275 IdentifyingPassPtr TargetID) { 276 Impl->TargetPasses[StandardID] = TargetID; 277} 278 279IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const { 280 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator 281 I = Impl->TargetPasses.find(ID); 282 if (I == Impl->TargetPasses.end()) 283 return ID; 284 return I->second; 285} 286 287/// Add a pass to the PassManager if that pass is supposed to be run. If the 288/// Started/Stopped flags indicate either that the compilation should start at 289/// a later pass or that it should stop after an earlier pass, then do not add 290/// the pass. Finally, compare the current pass against the StartAfter 291/// and StopAfter options and change the Started/Stopped flags accordingly. 292void TargetPassConfig::addPass(Pass *P) { 293 assert(!Initialized && "PassConfig is immutable"); 294 295 // Cache the Pass ID here in case the pass manager finds this pass is 296 // redundant with ones already scheduled / available, and deletes it. 297 // Fundamentally, once we add the pass to the manager, we no longer own it 298 // and shouldn't reference it. 299 AnalysisID PassID = P->getPassID(); 300 301 if (Started && !Stopped) 302 PM->add(P); 303 if (StopAfter == PassID) 304 Stopped = true; 305 if (StartAfter == PassID) 306 Started = true; 307 if (Stopped && !Started) 308 report_fatal_error("Cannot stop compilation after pass that is not run"); 309} 310 311/// Add a CodeGen pass at this point in the pipeline after checking for target 312/// and command line overrides. 313/// 314/// addPass cannot return a pointer to the pass instance because is internal the 315/// PassManager and the instance we create here may already be freed. 316AnalysisID TargetPassConfig::addPass(AnalysisID PassID) { 317 IdentifyingPassPtr TargetID = getPassSubstitution(PassID); 318 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); 319 if (!FinalPtr.isValid()) 320 return 0; 321 322 Pass *P; 323 if (FinalPtr.isInstance()) 324 P = FinalPtr.getInstance(); 325 else { 326 P = Pass::createPass(FinalPtr.getID()); 327 if (!P) 328 llvm_unreachable("Pass ID not registered"); 329 } 330 AnalysisID FinalID = P->getPassID(); 331 addPass(P); // Ends the lifetime of P. 332 333 // Add the passes after the pass P if there is any. 334 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator 335 I = Impl->InsertedPasses.begin(), E = Impl->InsertedPasses.end(); 336 I != E; ++I) { 337 if ((*I).first == PassID) { 338 assert((*I).second.isValid() && "Illegal Pass ID!"); 339 Pass *NP; 340 if ((*I).second.isInstance()) 341 NP = (*I).second.getInstance(); 342 else { 343 NP = Pass::createPass((*I).second.getID()); 344 assert(NP && "Pass ID not registered"); 345 } 346 addPass(NP); 347 } 348 } 349 return FinalID; 350} 351 352void TargetPassConfig::printAndVerify(const char *Banner) { 353 if (TM->shouldPrintMachineCode()) 354 addPass(createMachineFunctionPrinterPass(dbgs(), Banner)); 355 356 if (VerifyMachineCode) 357 addPass(createMachineVerifierPass(Banner)); 358} 359 360/// Add common target configurable passes that perform LLVM IR to IR transforms 361/// following machine independent optimization. 362void TargetPassConfig::addIRPasses() { 363 // Basic AliasAnalysis support. 364 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 365 // BasicAliasAnalysis wins if they disagree. This is intended to help 366 // support "obvious" type-punning idioms. 367 addPass(createTypeBasedAliasAnalysisPass()); 368 addPass(createBasicAliasAnalysisPass()); 369 370 // Before running any passes, run the verifier to determine if the input 371 // coming from the front-end and/or optimizer is valid. 372 if (!DisableVerify) 373 addPass(createVerifierPass()); 374 375 // Run loop strength reduction before anything else. 376 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { 377 addPass(createLoopStrengthReducePass()); 378 if (PrintLSR) 379 addPass(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); 380 } 381 382 addPass(createGCLoweringPass()); 383 384 // Make sure that no unreachable blocks are instruction selected. 385 addPass(createUnreachableBlockEliminationPass()); 386} 387 388/// Turn exception handling constructs into something the code generators can 389/// handle. 390void TargetPassConfig::addPassesToHandleExceptions() { 391 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { 392 case ExceptionHandling::SjLj: 393 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 394 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 395 // catch info can get misplaced when a selector ends up more than one block 396 // removed from the parent invoke(s). This could happen when a landing 397 // pad is shared by multiple invokes and is also a target of a normal 398 // edge from elsewhere. 399 addPass(createSjLjEHPreparePass(TM)); 400 // FALLTHROUGH 401 case ExceptionHandling::DwarfCFI: 402 case ExceptionHandling::ARM: 403 case ExceptionHandling::Win64: 404 addPass(createDwarfEHPass(TM)); 405 break; 406 case ExceptionHandling::None: 407 addPass(createLowerInvokePass(TM)); 408 409 // The lower invoke pass may create unreachable code. Remove it. 410 addPass(createUnreachableBlockEliminationPass()); 411 break; 412 } 413} 414 415/// Add pass to prepare the LLVM IR for code generation. This should be done 416/// before exception handling preparation passes. 417void TargetPassConfig::addCodeGenPrepare() { 418 if (getOptLevel() != CodeGenOpt::None && !DisableCGP) 419 addPass(createCodeGenPreparePass(TM)); 420} 421 422/// Add common passes that perform LLVM IR to IR transforms in preparation for 423/// instruction selection. 424void TargetPassConfig::addISelPrepare() { 425 addPass(createStackProtectorPass(TM)); 426 427 addPreISel(); 428 429 if (PrintISelInput) 430 addPass(createPrintFunctionPass("\n\n" 431 "*** Final LLVM Code input to ISel ***\n", 432 &dbgs())); 433 434 // All passes which modify the LLVM IR are now complete; run the verifier 435 // to ensure that the IR is valid. 436 if (!DisableVerify) 437 addPass(createVerifierPass()); 438} 439 440/// Add the complete set of target-independent postISel code generator passes. 441/// 442/// This can be read as the standard order of major LLVM CodeGen stages. Stages 443/// with nontrivial configuration or multiple passes are broken out below in 444/// add%Stage routines. 445/// 446/// Any TargetPassConfig::addXX routine may be overriden by the Target. The 447/// addPre/Post methods with empty header implementations allow injecting 448/// target-specific fixups just before or after major stages. Additionally, 449/// targets have the flexibility to change pass order within a stage by 450/// overriding default implementation of add%Stage routines below. Each 451/// technique has maintainability tradeoffs because alternate pass orders are 452/// not well supported. addPre/Post works better if the target pass is easily 453/// tied to a common pass. But if it has subtle dependencies on multiple passes, 454/// the target should override the stage instead. 455/// 456/// TODO: We could use a single addPre/Post(ID) hook to allow pass injection 457/// before/after any target-independent pass. But it's currently overkill. 458void TargetPassConfig::addMachinePasses() { 459 // Insert a machine instr printer pass after the specified pass. 460 // If -print-machineinstrs specified, print machineinstrs after all passes. 461 if (StringRef(PrintMachineInstrs.getValue()).equals("")) 462 TM->Options.PrintMachineCode = true; 463 else if (!StringRef(PrintMachineInstrs.getValue()) 464 .equals("option-unspecified")) { 465 const PassRegistry *PR = PassRegistry::getPassRegistry(); 466 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue()); 467 const PassInfo *IPI = PR->getPassInfo(StringRef("print-machineinstrs")); 468 assert (TPI && IPI && "Pass ID not registered!"); 469 const char *TID = (const char *)(TPI->getTypeInfo()); 470 const char *IID = (const char *)(IPI->getTypeInfo()); 471 insertPass(TID, IID); 472 } 473 474 // Print the instruction selected machine code... 475 printAndVerify("After Instruction Selection"); 476 477 // Expand pseudo-instructions emitted by ISel. 478 if (addPass(&ExpandISelPseudosID)) 479 printAndVerify("After ExpandISelPseudos"); 480 481 // Add passes that optimize machine instructions in SSA form. 482 if (getOptLevel() != CodeGenOpt::None) { 483 addMachineSSAOptimization(); 484 } else { 485 // If the target requests it, assign local variables to stack slots relative 486 // to one another and simplify frame index references where possible. 487 addPass(&LocalStackSlotAllocationID); 488 } 489 490 // Run pre-ra passes. 491 if (addPreRegAlloc()) 492 printAndVerify("After PreRegAlloc passes"); 493 494 // Run register allocation and passes that are tightly coupled with it, 495 // including phi elimination and scheduling. 496 if (getOptimizeRegAlloc()) 497 addOptimizedRegAlloc(createRegAllocPass(true)); 498 else 499 addFastRegAlloc(createRegAllocPass(false)); 500 501 // Run post-ra passes. 502 if (addPostRegAlloc()) 503 printAndVerify("After PostRegAlloc passes"); 504 505 // Insert prolog/epilog code. Eliminate abstract frame index references... 506 addPass(&PrologEpilogCodeInserterID); 507 printAndVerify("After PrologEpilogCodeInserter"); 508 509 /// Add passes that optimize machine instructions after register allocation. 510 if (getOptLevel() != CodeGenOpt::None) 511 addMachineLateOptimization(); 512 513 // Expand pseudo instructions before second scheduling pass. 514 addPass(&ExpandPostRAPseudosID); 515 printAndVerify("After ExpandPostRAPseudos"); 516 517 // Run pre-sched2 passes. 518 if (addPreSched2()) 519 printAndVerify("After PreSched2 passes"); 520 521 // Second pass scheduler. 522 if (getOptLevel() != CodeGenOpt::None) { 523 addPass(&PostRASchedulerID); 524 printAndVerify("After PostRAScheduler"); 525 } 526 527 // GC 528 if (addGCPasses()) { 529 if (PrintGCInfo) 530 addPass(createGCInfoPrinter(dbgs())); 531 } 532 533 // Basic block placement. 534 if (getOptLevel() != CodeGenOpt::None) 535 addBlockPlacement(); 536 537 if (addPreEmitPass()) 538 printAndVerify("After PreEmit passes"); 539} 540 541/// Add passes that optimize machine instructions in SSA form. 542void TargetPassConfig::addMachineSSAOptimization() { 543 // Pre-ra tail duplication. 544 if (addPass(&EarlyTailDuplicateID)) 545 printAndVerify("After Pre-RegAlloc TailDuplicate"); 546 547 // Optimize PHIs before DCE: removing dead PHI cycles may make more 548 // instructions dead. 549 addPass(&OptimizePHIsID); 550 551 // This pass merges large allocas. StackSlotColoring is a different pass 552 // which merges spill slots. 553 addPass(&StackColoringID); 554 555 // If the target requests it, assign local variables to stack slots relative 556 // to one another and simplify frame index references where possible. 557 addPass(&LocalStackSlotAllocationID); 558 559 // With optimization, dead code should already be eliminated. However 560 // there is one known exception: lowered code for arguments that are only 561 // used by tail calls, where the tail calls reuse the incoming stack 562 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 563 addPass(&DeadMachineInstructionElimID); 564 printAndVerify("After codegen DCE pass"); 565 566 // Allow targets to insert passes that improve instruction level parallelism, 567 // like if-conversion. Such passes will typically need dominator trees and 568 // loop info, just like LICM and CSE below. 569 if (addILPOpts()) 570 printAndVerify("After ILP optimizations"); 571 572 addPass(&MachineLICMID); 573 addPass(&MachineCSEID); 574 addPass(&MachineSinkingID); 575 printAndVerify("After Machine LICM, CSE and Sinking passes"); 576 577 addPass(&PeepholeOptimizerID); 578 printAndVerify("After codegen peephole optimization pass"); 579} 580 581//===---------------------------------------------------------------------===// 582/// Register Allocation Pass Configuration 583//===---------------------------------------------------------------------===// 584 585bool TargetPassConfig::getOptimizeRegAlloc() const { 586 switch (OptimizeRegAlloc) { 587 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; 588 case cl::BOU_TRUE: return true; 589 case cl::BOU_FALSE: return false; 590 } 591 llvm_unreachable("Invalid optimize-regalloc state"); 592} 593 594/// RegisterRegAlloc's global Registry tracks allocator registration. 595MachinePassRegistry RegisterRegAlloc::Registry; 596 597/// A dummy default pass factory indicates whether the register allocator is 598/// overridden on the command line. 599static FunctionPass *useDefaultRegisterAllocator() { return 0; } 600static RegisterRegAlloc 601defaultRegAlloc("default", 602 "pick register allocator based on -O option", 603 useDefaultRegisterAllocator); 604 605/// -regalloc=... command line option. 606static cl::opt<RegisterRegAlloc::FunctionPassCtor, false, 607 RegisterPassParser<RegisterRegAlloc> > 608RegAlloc("regalloc", 609 cl::init(&useDefaultRegisterAllocator), 610 cl::desc("Register allocator to use")); 611 612 613/// Instantiate the default register allocator pass for this target for either 614/// the optimized or unoptimized allocation path. This will be added to the pass 615/// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 616/// in the optimized case. 617/// 618/// A target that uses the standard regalloc pass order for fast or optimized 619/// allocation may still override this for per-target regalloc 620/// selection. But -regalloc=... always takes precedence. 621FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { 622 if (Optimized) 623 return createGreedyRegisterAllocator(); 624 else 625 return createFastRegisterAllocator(); 626} 627 628/// Find and instantiate the register allocation pass requested by this target 629/// at the current optimization level. Different register allocators are 630/// defined as separate passes because they may require different analysis. 631/// 632/// This helper ensures that the regalloc= option is always available, 633/// even for targets that override the default allocator. 634/// 635/// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, 636/// this can be folded into addPass. 637FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { 638 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 639 640 // Initialize the global default. 641 if (!Ctor) { 642 Ctor = RegAlloc; 643 RegisterRegAlloc::setDefault(RegAlloc); 644 } 645 if (Ctor != useDefaultRegisterAllocator) 646 return Ctor(); 647 648 // With no -regalloc= override, ask the target for a regalloc pass. 649 return createTargetRegisterAllocator(Optimized); 650} 651 652/// Add the minimum set of target-independent passes that are required for 653/// register allocation. No coalescing or scheduling. 654void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { 655 addPass(&PHIEliminationID); 656 addPass(&TwoAddressInstructionPassID); 657 658 addPass(RegAllocPass); 659 printAndVerify("After Register Allocation"); 660} 661 662/// Add standard target-independent passes that are tightly coupled with 663/// optimized register allocation, including coalescing, machine instruction 664/// scheduling, and register allocation itself. 665void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { 666 addPass(&ProcessImplicitDefsID); 667 668 // LiveVariables currently requires pure SSA form. 669 // 670 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, 671 // LiveVariables can be removed completely, and LiveIntervals can be directly 672 // computed. (We still either need to regenerate kill flags after regalloc, or 673 // preferably fix the scavenger to not depend on them). 674 addPass(&LiveVariablesID); 675 676 // Add passes that move from transformed SSA into conventional SSA. This is a 677 // "copy coalescing" problem. 678 // 679 if (!EnableStrongPHIElim) { 680 // Edge splitting is smarter with machine loop info. 681 addPass(&MachineLoopInfoID); 682 addPass(&PHIEliminationID); 683 } 684 685 // Eventually, we want to run LiveIntervals before PHI elimination. 686 if (EarlyLiveIntervals) 687 addPass(&LiveIntervalsID); 688 689 addPass(&TwoAddressInstructionPassID); 690 691 if (EnableStrongPHIElim) 692 addPass(&StrongPHIEliminationID); 693 694 addPass(&RegisterCoalescerID); 695 696 // PreRA instruction scheduling. 697 if (addPass(&MachineSchedulerID)) 698 printAndVerify("After Machine Scheduling"); 699 700 // Add the selected register allocation pass. 701 addPass(RegAllocPass); 702 printAndVerify("After Register Allocation, before rewriter"); 703 704 // Allow targets to change the register assignments before rewriting. 705 if (addPreRewrite()) 706 printAndVerify("After pre-rewrite passes"); 707 708 // Finally rewrite virtual registers. 709 addPass(&VirtRegRewriterID); 710 printAndVerify("After Virtual Register Rewriter"); 711 712 // Perform stack slot coloring and post-ra machine LICM. 713 // 714 // FIXME: Re-enable coloring with register when it's capable of adding 715 // kill markers. 716 addPass(&StackSlotColoringID); 717 718 // Run post-ra machine LICM to hoist reloads / remats. 719 // 720 // FIXME: can this move into MachineLateOptimization? 721 addPass(&PostRAMachineLICMID); 722 723 printAndVerify("After StackSlotColoring and postra Machine LICM"); 724} 725 726//===---------------------------------------------------------------------===// 727/// Post RegAlloc Pass Configuration 728//===---------------------------------------------------------------------===// 729 730/// Add passes that optimize machine instructions after register allocation. 731void TargetPassConfig::addMachineLateOptimization() { 732 // Branch folding must be run after regalloc and prolog/epilog insertion. 733 if (addPass(&BranchFolderPassID)) 734 printAndVerify("After BranchFolding"); 735 736 // Tail duplication. 737 if (addPass(&TailDuplicateID)) 738 printAndVerify("After TailDuplicate"); 739 740 // Copy propagation. 741 if (addPass(&MachineCopyPropagationID)) 742 printAndVerify("After copy propagation pass"); 743} 744 745/// Add standard GC passes. 746bool TargetPassConfig::addGCPasses() { 747 addPass(&GCMachineCodeAnalysisID); 748 return true; 749} 750 751/// Add standard basic block placement passes. 752void TargetPassConfig::addBlockPlacement() { 753 if (addPass(&MachineBlockPlacementID)) { 754 // Run a separate pass to collect block placement statistics. 755 if (EnableBlockPlacementStats) 756 addPass(&MachineBlockPlacementStatsID); 757 758 printAndVerify("After machine block placement."); 759 } 760} 761