ProcessImplicitDefs.cpp revision 8dd26253f54247e77e5accfdd70e7b4bf27b39c2 
1//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "processimplicitdefs"
11
12#include "llvm/CodeGen/ProcessImplicitDefs.h"
13
14#include "llvm/ADT/DepthFirstIterator.h"
15#include "llvm/ADT/SmallSet.h"
16#include "llvm/Analysis/AliasAnalysis.h"
17#include "llvm/CodeGen/LiveVariables.h"
18#include "llvm/CodeGen/MachineInstr.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/Passes.h"
21#include "llvm/Support/Debug.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24
25
26using namespace llvm;
27
28char ProcessImplicitDefs::ID = 0;
29char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID;
30
31INITIALIZE_PASS_BEGIN(ProcessImplicitDefs, "processimpdefs",
32                "Process Implicit Definitions", false, false)
33INITIALIZE_PASS_DEPENDENCY(LiveVariables)
34INITIALIZE_PASS_END(ProcessImplicitDefs, "processimpdefs",
35                "Process Implicit Definitions", false, false)
36
37void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
38  AU.setPreservesCFG();
39  AU.addPreserved<AliasAnalysis>();
40  AU.addPreserved<LiveVariables>();
41  AU.addPreservedID(MachineLoopInfoID);
42  AU.addPreservedID(MachineDominatorsID);
43  AU.addPreservedID(TwoAddressInstructionPassID);
44  AU.addPreservedID(PHIEliminationID);
45  MachineFunctionPass::getAnalysisUsage(AU);
46}
47
48bool
49ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
50                                            unsigned Reg, unsigned OpIdx,
51                                            SmallSet<unsigned, 8> &ImpDefRegs) {
52  switch(OpIdx) {
53  case 1:
54    return MI->isCopy() && (!MI->getOperand(0).readsReg() ||
55                            ImpDefRegs.count(MI->getOperand(0).getReg()));
56  case 2:
57    return MI->isSubregToReg() && (!MI->getOperand(0).readsReg() ||
58                                  ImpDefRegs.count(MI->getOperand(0).getReg()));
59  default: return false;
60  }
61}
62
63static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
64                        SmallSet<unsigned, 8> &ImpDefRegs) {
65  if (MI->isCopy()) {
66    MachineOperand &MO0 = MI->getOperand(0);
67    MachineOperand &MO1 = MI->getOperand(1);
68    if (MO1.getReg() != Reg)
69      return false;
70    if (!MO0.readsReg() || ImpDefRegs.count(MO0.getReg()))
71      return true;
72    return false;
73  }
74  return false;
75}
76
77/// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
78/// there is one implicit_def for each use. Add isUndef marker to
79/// implicit_def defs and their uses.
80bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
81
82  DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
83               << "********** Function: "
84               << ((Value*)fn.getFunction())->getName() << '\n');
85
86  bool Changed = false;
87
88  TII = fn.getTarget().getInstrInfo();
89  TRI = fn.getTarget().getRegisterInfo();
90  MRI = &fn.getRegInfo();
91  LV = getAnalysisIfAvailable<LiveVariables>();
92
93  SmallSet<unsigned, 8> ImpDefRegs;
94  SmallVector<MachineInstr*, 8> ImpDefMIs;
95  SmallVector<MachineInstr*, 4> RUses;
96  SmallPtrSet<MachineBasicBlock*,16> Visited;
97  SmallPtrSet<MachineInstr*, 8> ModInsts;
98
99  MachineBasicBlock *Entry = fn.begin();
100  for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
101         DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
102       DFI != E; ++DFI) {
103    MachineBasicBlock *MBB = *DFI;
104    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
105         I != E; ) {
106      MachineInstr *MI = &*I;
107      ++I;
108      if (MI->isImplicitDef()) {
109        ImpDefMIs.push_back(MI);
110        // Is this a sub-register read-modify-write?
111        if (MI->getOperand(0).readsReg())
112          continue;
113        unsigned Reg = MI->getOperand(0).getReg();
114        ImpDefRegs.insert(Reg);
115        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
116          for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
117            ImpDefRegs.insert(*SS);
118        }
119        continue;
120      }
121
122      // Eliminate %reg1032:sub<def> = COPY undef.
123      if (MI->isCopy() && MI->getOperand(0).readsReg()) {
124        MachineOperand &MO = MI->getOperand(1);
125        if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) {
126          if (LV && MO.isKill()) {
127            LiveVariables::VarInfo& vi = LV->getVarInfo(MO.getReg());
128            vi.removeKill(MI);
129          }
130          unsigned Reg = MI->getOperand(0).getReg();
131          MI->eraseFromParent();
132          Changed = true;
133
134          // A REG_SEQUENCE may have been expanded into partial definitions.
135          // If this was the last one, mark Reg as implicitly defined.
136          if (TargetRegisterInfo::isVirtualRegister(Reg) && MRI->def_empty(Reg))
137            ImpDefRegs.insert(Reg);
138          continue;
139        }
140      }
141
142      bool ChangedToImpDef = false;
143      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
144        MachineOperand& MO = MI->getOperand(i);
145        if (!MO.isReg() || !MO.readsReg())
146          continue;
147        unsigned Reg = MO.getReg();
148        if (!Reg)
149          continue;
150        if (!ImpDefRegs.count(Reg))
151          continue;
152        // Use is a copy, just turn it into an implicit_def.
153        if (CanTurnIntoImplicitDef(MI, Reg, i, ImpDefRegs)) {
154          bool isKill = MO.isKill();
155          MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
156          for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
157            MI->RemoveOperand(j);
158          if (isKill) {
159            ImpDefRegs.erase(Reg);
160            if (LV) {
161              LiveVariables::VarInfo& vi = LV->getVarInfo(Reg);
162              vi.removeKill(MI);
163            }
164          }
165          ChangedToImpDef = true;
166          Changed = true;
167          break;
168        }
169
170        Changed = true;
171        MO.setIsUndef();
172        // This is a partial register redef of an implicit def.
173        // Make sure the whole register is defined by the instruction.
174        if (MO.isDef()) {
175          MI->addRegisterDefined(Reg);
176          continue;
177        }
178        if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
179          // Make sure other reads of Reg are also marked <undef>.
180          for (unsigned j = i+1; j != e; ++j) {
181            MachineOperand &MOJ = MI->getOperand(j);
182            if (MOJ.isReg() && MOJ.getReg() == Reg && MOJ.readsReg())
183              MOJ.setIsUndef();
184          }
185          ImpDefRegs.erase(Reg);
186        }
187      }
188
189      if (ChangedToImpDef) {
190        // Backtrack to process this new implicit_def.
191        --I;
192      } else {
193        for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
194          MachineOperand& MO = MI->getOperand(i);
195          if (!MO.isReg() || !MO.isDef())
196            continue;
197          ImpDefRegs.erase(MO.getReg());
198        }
199      }
200    }
201
202    // Any outstanding liveout implicit_def's?
203    for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) {
204      MachineInstr *MI = ImpDefMIs[i];
205      unsigned Reg = MI->getOperand(0).getReg();
206      if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
207          !ImpDefRegs.count(Reg)) {
208        // Delete all "local" implicit_def's. That include those which define
209        // physical registers since they cannot be liveout.
210        MI->eraseFromParent();
211        Changed = true;
212        continue;
213      }
214
215      // If there are multiple defs of the same register and at least one
216      // is not an implicit_def, do not insert implicit_def's before the
217      // uses.
218      bool Skip = false;
219      SmallVector<MachineInstr*, 4> DeadImpDefs;
220      for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
221             DE = MRI->def_end(); DI != DE; ++DI) {
222        MachineInstr *DeadImpDef = &*DI;
223        if (!DeadImpDef->isImplicitDef()) {
224          Skip = true;
225          break;
226        }
227        DeadImpDefs.push_back(DeadImpDef);
228      }
229      if (Skip)
230        continue;
231
232      // The only implicit_def which we want to keep are those that are live
233      // out of its block.
234      for (unsigned j = 0, ee = DeadImpDefs.size(); j != ee; ++j)
235        DeadImpDefs[j]->eraseFromParent();
236      Changed = true;
237
238      // Process each use instruction once.
239      for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
240             UE = MRI->use_end(); UI != UE; ++UI) {
241        if (UI.getOperand().isUndef())
242          continue;
243        MachineInstr *RMI = &*UI;
244        if (ModInsts.insert(RMI))
245          RUses.push_back(RMI);
246      }
247
248      for (unsigned i = 0, e = RUses.size(); i != e; ++i) {
249        MachineInstr *RMI = RUses[i];
250
251        // Turn a copy use into an implicit_def.
252        if (isUndefCopy(RMI, Reg, ImpDefRegs)) {
253          RMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
254
255          bool isKill = false;
256          SmallVector<unsigned, 4> Ops;
257          for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
258            MachineOperand &RRMO = RMI->getOperand(j);
259            if (RRMO.isReg() && RRMO.getReg() == Reg) {
260              Ops.push_back(j);
261              if (RRMO.isKill())
262                isKill = true;
263            }
264          }
265          // Leave the other operands along.
266          for (unsigned j = 0, ee = Ops.size(); j != ee; ++j) {
267            unsigned OpIdx = Ops[j];
268            RMI->RemoveOperand(OpIdx-j);
269          }
270
271          // Update LiveVariables varinfo if the instruction is a kill.
272          if (LV && isKill) {
273            LiveVariables::VarInfo& vi = LV->getVarInfo(Reg);
274            vi.removeKill(RMI);
275          }
276          continue;
277        }
278
279        // Replace Reg with a new vreg that's marked implicit.
280        const TargetRegisterClass* RC = MRI->getRegClass(Reg);
281        unsigned NewVReg = MRI->createVirtualRegister(RC);
282        bool isKill = true;
283        for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
284          MachineOperand &RRMO = RMI->getOperand(j);
285          if (RRMO.isReg() && RRMO.getReg() == Reg) {
286            RRMO.setReg(NewVReg);
287            RRMO.setIsUndef();
288            if (isKill) {
289              // Only the first operand of NewVReg is marked kill.
290              RRMO.setIsKill();
291              isKill = false;
292            }
293          }
294        }
295      }
296      RUses.clear();
297      ModInsts.clear();
298    }
299    ImpDefRegs.clear();
300    ImpDefMIs.clear();
301  }
302
303  return Changed;
304}
305
306