README.txt revision 877333b99dd830c3e8bb7eaa1345ea942d29fc06
1//===---------------------------------------------------------------------===// 2 3Common register allocation / spilling problem: 4 5 mul lr, r4, lr 6 str lr, [sp, #+52] 7 ldr lr, [r1, #+32] 8 sxth r3, r3 9 ldr r4, [sp, #+52] 10 mla r4, r3, lr, r4 11 12can be: 13 14 mul lr, r4, lr 15 mov r4, lr 16 str lr, [sp, #+52] 17 ldr lr, [r1, #+32] 18 sxth r3, r3 19 mla r4, r3, lr, r4 20 21and then "merge" mul and mov: 22 23 mul r4, r4, lr 24 str lr, [sp, #+52] 25 ldr lr, [r1, #+32] 26 sxth r3, r3 27 mla r4, r3, lr, r4 28 29It also increase the likelyhood the store may become dead. 30 31//===---------------------------------------------------------------------===// 32 33I think we should have a "hasSideEffects" flag (which is automatically set for 34stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able 35to remat any instruction that has no side effects, if it can handle it and if 36profitable. 37 38For now, I'd suggest having the remat stuff work like this: 39 401. I need to spill/reload this thing. 412. Check to see if it has side effects. 423. Check to see if it is simple enough: e.g. it only has one register 43destination and no register input. 444. If so, clone the instruction, do the xform, etc. 45 46Advantages of this are: 47 481. the .td file describes the behavior of the instructions, not the way the 49 algorithm should work. 502. as remat gets smarter in the future, we shouldn't have to be changing the .td 51 files. 523. it is easier to explain what the flag means in the .td file, because you 53 don't have to pull in the explanation of how the current remat algo works. 54 55Some potential added complexities: 56 571. Some instructions have to be glued to it's predecessor or successor. All of 58 the PC relative instructions and condition code setting instruction. We could 59 mark them as hasSideEffects, but that's not quite right. PC relative loads 60 from constantpools can be remat'ed, for example. But it requires more than 61 just cloning the instruction. Some instructions can be remat'ed but it 62 expands to more than one instruction. But allocator will have to make a 63 decision. 64 654. As stated in 3, not as simple as cloning in some cases. The target will have 66 to decide how to remat it. For example, an ARM 2-piece constant generation 67 instruction is remat'ed as a load from constantpool. 68 69//===---------------------------------------------------------------------===// 70 71bb27 ... 72 ... 73 %reg1037 = ADDri %reg1039, 1 74 %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10 75 Successors according to CFG: 0x8b03bf0 (#5) 76 77bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5): 78 Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4) 79 %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0> 80 81Note ADDri is not a two-address instruction. However, its result %reg1037 is an 82operand of the PHI node in bb76 and its operand %reg1039 is the result of the 83PHI node. We should treat it as a two-address code and make sure the ADDri is 84scheduled after any node that reads %reg1039. 85 86//===---------------------------------------------------------------------===// 87 88Use local info (i.e. register scavenger) to assign it a free register to allow 89reuse: 90 ldr r3, [sp, #+4] 91 add r3, r3, #3 92 ldr r2, [sp, #+8] 93 add r2, r2, #2 94 ldr r1, [sp, #+4] <== 95 add r1, r1, #1 96 ldr r0, [sp, #+4] 97 add r0, r0, #2 98 99//===---------------------------------------------------------------------===// 100 101LLVM aggressively lift CSE out of loop. Sometimes this can be negative side- 102effects: 103 104R1 = X + 4 105R2 = X + 7 106R3 = X + 15 107 108loop: 109load [i + R1] 110... 111load [i + R2] 112... 113load [i + R3] 114 115Suppose there is high register pressure, R1, R2, R3, can be spilled. We need 116to implement proper re-materialization to handle this: 117 118R1 = X + 4 119R2 = X + 7 120R3 = X + 15 121 122loop: 123R1 = X + 4 @ re-materialized 124load [i + R1] 125... 126R2 = X + 7 @ re-materialized 127load [i + R2] 128... 129R3 = X + 15 @ re-materialized 130load [i + R3] 131 132Furthermore, with re-association, we can enable sharing: 133 134R1 = X + 4 135R2 = X + 7 136R3 = X + 15 137 138loop: 139T = i + X 140load [T + 4] 141... 142load [T + 7] 143... 144load [T + 15] 145//===---------------------------------------------------------------------===// 146 147It's not always a good idea to choose rematerialization over spilling. If all 148the load / store instructions would be folded then spilling is cheaper because 149it won't require new live intervals / registers. See 2003-05-31-LongShifts for 150an example. 151 152//===---------------------------------------------------------------------===// 153 154With a copying garbage collector, derived pointers must not be retained across 155collector safe points; the collector could move the objects and invalidate the 156derived pointer. This is bad enough in the first place, but safe points can 157crop up unpredictably. Consider: 158 159 %array = load { i32, [0 x %obj] }** %array_addr 160 %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n 161 %old = load %obj** %nth_el 162 %z = div i64 %x, %y 163 store %obj* %new, %obj** %nth_el 164 165If the i64 division is lowered to a libcall, then a safe point will (must) 166appear for the call site. If a collection occurs, %array and %nth_el no longer 167point into the correct object. 168 169The fix for this is to copy address calculations so that dependent pointers 170are never live across safe point boundaries. But the loads cannot be copied 171like this if there was an intervening store, so may be hard to get right. 172 173Only a concurrent mutator can trigger a collection at the libcall safe point. 174So single-threaded programs do not have this requirement, even with a copying 175collector. Still, LLVM optimizations would probably undo a front-end's careful 176work. 177 178//===---------------------------------------------------------------------===// 179 180The ocaml frametable structure supports liveness information. It would be good 181to support it. 182 183//===---------------------------------------------------------------------===// 184 185The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be 186revisited. The check is there to work around a misuse of directives in inline 187assembly. 188 189//===---------------------------------------------------------------------===// 190 191It would be good to detect collector/target compatibility instead of silently 192doing the wrong thing. 193 194//===---------------------------------------------------------------------===// 195 196It would be really nice to be able to write patterns in .td files for copies, 197which would eliminate a bunch of explicit predicates on them (e.g. no side 198effects). Once this is in place, it would be even better to have tblgen 199synthesize the various copy insertion/inspection methods in TargetInstrInfo. 200 201//===---------------------------------------------------------------------===// 202 203Stack coloring improvments: 204 2051. Do proper LiveStackAnalysis on all stack objects including those which are 206 not spill slots. 2072. Reorder objects to fill in gaps between objects. 208 e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4 209