RegAllocBase.h revision 4680dec5fb3a1b624f13ca9b2a555ca90a07973e
1//===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the RegAllocBase class, which is the skeleton of a basic 11// register allocation algorithm and interface for extending it. It provides the 12// building blocks on which to construct other experimental allocators and test 13// the validity of two principles: 14// 15// - If virtual and physical register liveness is modeled using intervals, then 16// on-the-fly interference checking is cheap. Furthermore, interferences can be 17// lazily cached and reused. 18// 19// - Register allocation complexity, and generated code performance is 20// determined by the effectiveness of live range splitting rather than optimal 21// coloring. 22// 23// Following the first principle, interfering checking revolves around the 24// LiveIntervalUnion data structure. 25// 26// To fulfill the second principle, the basic allocator provides a driver for 27// incremental splitting. It essentially punts on the problem of register 28// coloring, instead driving the assignment of virtual to physical registers by 29// the cost of splitting. The basic allocator allows for heuristic reassignment 30// of registers, if a more sophisticated allocator chooses to do that. 31// 32// This framework provides a way to engineer the compile time vs. code 33// quality trade-off without relying a particular theoretical solver. 34// 35//===----------------------------------------------------------------------===// 36 37#ifndef LLVM_CODEGEN_REGALLOCBASE 38#define LLVM_CODEGEN_REGALLOCBASE 39 40#include "llvm/ADT/OwningPtr.h" 41#include "LiveIntervalUnion.h" 42#include <queue> 43 44namespace llvm { 45 46template<typename T> class SmallVectorImpl; 47class TargetRegisterInfo; 48class VirtRegMap; 49class LiveIntervals; 50class Spiller; 51 52// Forward declare a priority queue of live virtual registers. If an 53// implementation needs to prioritize by anything other than spill weight, then 54// this will become an abstract base class with virtual calls to push/get. 55class LiveVirtRegQueue; 56 57/// RegAllocBase provides the register allocation driver and interface that can 58/// be extended to add interesting heuristics. 59/// 60/// Register allocators must override the selectOrSplit() method to implement 61/// live range splitting. They may also override getPriority() which otherwise 62/// defaults to the spill weight computed by CalculateSpillWeights. 63class RegAllocBase { 64 LiveIntervalUnion::Allocator UnionAllocator; 65protected: 66 // Array of LiveIntervalUnions indexed by physical register. 67 class LiveUnionArray { 68 unsigned NumRegs; 69 LiveIntervalUnion *Array; 70 public: 71 LiveUnionArray(): NumRegs(0), Array(0) {} 72 ~LiveUnionArray() { clear(); } 73 74 unsigned numRegs() const { return NumRegs; } 75 76 void init(LiveIntervalUnion::Allocator &, unsigned NRegs); 77 78 void clear(); 79 80 LiveIntervalUnion& operator[](unsigned PhysReg) { 81 assert(PhysReg < NumRegs && "physReg out of bounds"); 82 return Array[PhysReg]; 83 } 84 }; 85 86 const TargetRegisterInfo *TRI; 87 MachineRegisterInfo *MRI; 88 VirtRegMap *VRM; 89 LiveIntervals *LIS; 90 LiveUnionArray PhysReg2LiveUnion; 91 92 // Current queries, one per physreg. They must be reinitialized each time we 93 // query on a new live virtual register. 94 OwningArrayPtr<LiveIntervalUnion::Query> Queries; 95 96 RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0) {} 97 98 virtual ~RegAllocBase() {} 99 100 // A RegAlloc pass should call this before allocatePhysRegs. 101 void init(VirtRegMap &vrm, LiveIntervals &lis); 102 103 // Get an initialized query to check interferences between lvr and preg. Note 104 // that Query::init must be called at least once for each physical register 105 // before querying a new live virtual register. This ties Queries and 106 // PhysReg2LiveUnion together. 107 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) { 108 Queries[PhysReg].init(&VirtReg, &PhysReg2LiveUnion[PhysReg]); 109 return Queries[PhysReg]; 110 } 111 112 // The top-level driver. The output is a VirtRegMap that us updated with 113 // physical register assignments. 114 // 115 // If an implementation wants to override the LiveInterval comparator, we 116 // should modify this interface to allow passing in an instance derived from 117 // LiveVirtRegQueue. 118 void allocatePhysRegs(); 119 120 // Get a temporary reference to a Spiller instance. 121 virtual Spiller &spiller() = 0; 122 123 // getPriority - Calculate the allocation priority for VirtReg. 124 // Virtual registers with higher priorities are allocated first. 125 virtual float getPriority(LiveInterval *LI) = 0; 126 127 // A RegAlloc pass should override this to provide the allocation heuristics. 128 // Each call must guarantee forward progess by returning an available PhysReg 129 // or new set of split live virtual registers. It is up to the splitter to 130 // converge quickly toward fully spilled live ranges. 131 virtual unsigned selectOrSplit(LiveInterval &VirtReg, 132 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0; 133 134 // A RegAlloc pass should call this when PassManager releases its memory. 135 virtual void releaseMemory(); 136 137 // Helper for checking interference between a live virtual register and a 138 // physical register, including all its register aliases. If an interference 139 // exists, return the interfering register, which may be preg or an alias. 140 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg); 141 142 // Helper for spilling all live virtual registers currently unified under preg 143 // that interfere with the most recently queried lvr. Return true if spilling 144 // was successful, and append any new spilled/split intervals to splitLVRs. 145 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, 146 SmallVectorImpl<LiveInterval*> &SplitVRegs); 147 148 /// addMBBLiveIns - Add physreg liveins to basic blocks. 149 void addMBBLiveIns(MachineFunction *); 150 151#ifndef NDEBUG 152 // Verify each LiveIntervalUnion. 153 void verify(); 154#endif 155 156private: 157 void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&); 158 159 void spillReg(LiveInterval &VirtReg, unsigned PhysReg, 160 SmallVectorImpl<LiveInterval*> &SplitVRegs); 161}; 162 163} // end namespace llvm 164 165#endif // !defined(LLVM_CODEGEN_REGALLOCBASE) 166