RegAllocBase.h revision 98d9648de7d571b2e6d139b65961a70d1833b0d7 
1//===-- RegAllocBase.h - basic regalloc interface and driver --*- C++ -*---===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the RegAllocBase class, which is the skeleton of a basic
11// register allocation algorithm and interface for extending it. It provides the
12// building blocks on which to construct other experimental allocators and test
13// the validity of two principles:
14//
15// - If virtual and physical register liveness is modeled using intervals, then
16// on-the-fly interference checking is cheap. Furthermore, interferences can be
17// lazily cached and reused.
18//
19// - Register allocation complexity, and generated code performance is
20// determined by the effectiveness of live range splitting rather than optimal
21// coloring.
22//
23// Following the first principle, interfering checking revolves around the
24// LiveIntervalUnion data structure.
25//
26// To fulfill the second principle, the basic allocator provides a driver for
27// incremental splitting. It essentially punts on the problem of register
28// coloring, instead driving the assignment of virtual to physical registers by
29// the cost of splitting. The basic allocator allows for heuristic reassignment
30// of registers, if a more sophisticated allocator chooses to do that.
31//
32// This framework provides a way to engineer the compile time vs. code
33// quality trade-off without relying on a particular theoretical solver.
34//
35//===----------------------------------------------------------------------===//
36
37#ifndef LLVM_CODEGEN_REGALLOCBASE
38#define LLVM_CODEGEN_REGALLOCBASE
39
40#include "llvm/ADT/OwningPtr.h"
41#include "LiveIntervalUnion.h"
42
43namespace llvm {
44
45template<typename T> class SmallVectorImpl;
46class TargetRegisterInfo;
47class VirtRegMap;
48class LiveIntervals;
49class Spiller;
50
51// Forward declare a priority queue of live virtual registers. If an
52// implementation needs to prioritize by anything other than spill weight, then
53// this will become an abstract base class with virtual calls to push/get.
54class LiveVirtRegQueue;
55
56/// RegAllocBase provides the register allocation driver and interface that can
57/// be extended to add interesting heuristics.
58///
59/// Register allocators must override the selectOrSplit() method to implement
60/// live range splitting. They must also override enqueue/dequeue to provide an
61/// assignment order.
62class RegAllocBase {
63  LiveIntervalUnion::Allocator UnionAllocator;
64protected:
65  // Array of LiveIntervalUnions indexed by physical register.
66  class LiveUnionArray {
67    unsigned NumRegs;
68    LiveIntervalUnion *Array;
69  public:
70    LiveUnionArray(): NumRegs(0), Array(0) {}
71    ~LiveUnionArray() { clear(); }
72
73    unsigned numRegs() const { return NumRegs; }
74
75    void init(LiveIntervalUnion::Allocator &, unsigned NRegs);
76
77    void clear();
78
79    LiveIntervalUnion& operator[](unsigned PhysReg) {
80      assert(PhysReg <  NumRegs && "physReg out of bounds");
81      return Array[PhysReg];
82    }
83  };
84
85  const TargetRegisterInfo *TRI;
86  MachineRegisterInfo *MRI;
87  VirtRegMap *VRM;
88  LiveIntervals *LIS;
89  LiveUnionArray PhysReg2LiveUnion;
90
91  // Current queries, one per physreg. They must be reinitialized each time we
92  // query on a new live virtual register.
93  OwningArrayPtr<LiveIntervalUnion::Query> Queries;
94
95  RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0) {}
96
97  virtual ~RegAllocBase() {}
98
99  // A RegAlloc pass should call this before allocatePhysRegs.
100  void init(VirtRegMap &vrm, LiveIntervals &lis);
101
102  // Get an initialized query to check interferences between lvr and preg.  Note
103  // that Query::init must be called at least once for each physical register
104  // before querying a new live virtual register. This ties Queries and
105  // PhysReg2LiveUnion together.
106  LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
107    Queries[PhysReg].init(&VirtReg, &PhysReg2LiveUnion[PhysReg]);
108    return Queries[PhysReg];
109  }
110
111  // The top-level driver. The output is a VirtRegMap that us updated with
112  // physical register assignments.
113  //
114  // If an implementation wants to override the LiveInterval comparator, we
115  // should modify this interface to allow passing in an instance derived from
116  // LiveVirtRegQueue.
117  void allocatePhysRegs();
118
119  // Get a temporary reference to a Spiller instance.
120  virtual Spiller &spiller() = 0;
121
122  /// enqueue - Add VirtReg to the priority queue of unassigned registers.
123  virtual void enqueue(LiveInterval *LI) = 0;
124
125  /// dequeue - Return the next unassigned register, or NULL.
126  virtual LiveInterval *dequeue() = 0;
127
128  // A RegAlloc pass should override this to provide the allocation heuristics.
129  // Each call must guarantee forward progess by returning an available PhysReg
130  // or new set of split live virtual registers. It is up to the splitter to
131  // converge quickly toward fully spilled live ranges.
132  virtual unsigned selectOrSplit(LiveInterval &VirtReg,
133                                 SmallVectorImpl<LiveInterval*> &splitLVRs) = 0;
134
135  // A RegAlloc pass should call this when PassManager releases its memory.
136  virtual void releaseMemory();
137
138  // Helper for checking interference between a live virtual register and a
139  // physical register, including all its register aliases. If an interference
140  // exists, return the interfering register, which may be preg or an alias.
141  unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
142
143  /// assign - Assign VirtReg to PhysReg.
144  /// This should not be called from selectOrSplit for the current register.
145  void assign(LiveInterval &VirtReg, unsigned PhysReg);
146
147  /// unassign - Undo a previous assignment of VirtReg to PhysReg.
148  /// This can be invoked from selectOrSplit, but be careful to guarantee that
149  /// allocation is making progress.
150  void unassign(LiveInterval &VirtReg, unsigned PhysReg);
151
152  // Helper for spilling all live virtual registers currently unified under preg
153  // that interfere with the most recently queried lvr.  Return true if spilling
154  // was successful, and append any new spilled/split intervals to splitLVRs.
155  bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
156                          SmallVectorImpl<LiveInterval*> &SplitVRegs);
157
158  /// addMBBLiveIns - Add physreg liveins to basic blocks.
159  void addMBBLiveIns(MachineFunction *);
160
161#ifndef NDEBUG
162  // Verify each LiveIntervalUnion.
163  void verify();
164#endif
165
166  // Use this group name for NamedRegionTimer.
167  static const char *TimerGroupName;
168
169public:
170  /// VerifyEnabled - True when -verify-regalloc is given.
171  static bool VerifyEnabled;
172
173private:
174  void seedLiveRegs();
175
176  void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
177                SmallVectorImpl<LiveInterval*> &SplitVRegs);
178};
179
180} // end namespace llvm
181
182#endif // !defined(LLVM_CODEGEN_REGALLOCBASE)
183