RegAllocFast.cpp revision 27ce3b96e51887995f94d8c78a6c7e79bf7cdcdd
1//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This register allocator allocates registers to a basic block at a time, 11// attempting to keep values in registers and reusing registers as appropriate. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "RegisterClassInfo.h" 17#include "llvm/BasicBlock.h" 18#include "llvm/CodeGen/MachineFunctionPass.h" 19#include "llvm/CodeGen/MachineInstr.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/Passes.h" 24#include "llvm/CodeGen/RegAllocRegistry.h" 25#include "llvm/Target/TargetInstrInfo.h" 26#include "llvm/Target/TargetMachine.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/ErrorHandling.h" 30#include "llvm/Support/raw_ostream.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/IndexedMap.h" 33#include "llvm/ADT/SmallSet.h" 34#include "llvm/ADT/SmallVector.h" 35#include "llvm/ADT/Statistic.h" 36#include "llvm/ADT/STLExtras.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NumStores, "Number of stores added"); 41STATISTIC(NumLoads , "Number of loads added"); 42STATISTIC(NumCopies, "Number of copies coalesced"); 43 44static RegisterRegAlloc 45 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator); 46 47namespace { 48 class RAFast : public MachineFunctionPass { 49 public: 50 static char ID; 51 RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1), 52 isBulkSpilling(false) { 53 initializePHIEliminationPass(*PassRegistry::getPassRegistry()); 54 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); 55 } 56 private: 57 const TargetMachine *TM; 58 MachineFunction *MF; 59 MachineRegisterInfo *MRI; 60 const TargetRegisterInfo *TRI; 61 const TargetInstrInfo *TII; 62 RegisterClassInfo RegClassInfo; 63 64 // Basic block currently being allocated. 65 MachineBasicBlock *MBB; 66 67 // StackSlotForVirtReg - Maps virtual regs to the frame index where these 68 // values are spilled. 69 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg; 70 71 // Everything we know about a live virtual register. 72 struct LiveReg { 73 MachineInstr *LastUse; // Last instr to use reg. 74 unsigned PhysReg; // Currently held here. 75 unsigned short LastOpNum; // OpNum on LastUse. 76 bool Dirty; // Register needs spill. 77 78 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0), 79 Dirty(false) {} 80 }; 81 82 typedef DenseMap<unsigned, LiveReg> LiveRegMap; 83 typedef LiveRegMap::value_type LiveRegEntry; 84 85 // LiveVirtRegs - This map contains entries for each virtual register 86 // that is currently available in a physical register. 87 LiveRegMap LiveVirtRegs; 88 89 DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap; 90 91 // RegState - Track the state of a physical register. 92 enum RegState { 93 // A disabled register is not available for allocation, but an alias may 94 // be in use. A register can only be moved out of the disabled state if 95 // all aliases are disabled. 96 regDisabled, 97 98 // A free register is not currently in use and can be allocated 99 // immediately without checking aliases. 100 regFree, 101 102 // A reserved register has been assigned explicitly (e.g., setting up a 103 // call parameter), and it remains reserved until it is used. 104 regReserved 105 106 // A register state may also be a virtual register number, indication that 107 // the physical register is currently allocated to a virtual register. In 108 // that case, LiveVirtRegs contains the inverse mapping. 109 }; 110 111 // PhysRegState - One of the RegState enums, or a virtreg. 112 std::vector<unsigned> PhysRegState; 113 114 // UsedInInstr - BitVector of physregs that are used in the current 115 // instruction, and so cannot be allocated. 116 BitVector UsedInInstr; 117 118 // SkippedInstrs - Descriptors of instructions whose clobber list was 119 // ignored because all registers were spilled. It is still necessary to 120 // mark all the clobbered registers as used by the function. 121 SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs; 122 123 // isBulkSpilling - This flag is set when LiveRegMap will be cleared 124 // completely after spilling all live registers. LiveRegMap entries should 125 // not be erased. 126 bool isBulkSpilling; 127 128 enum { 129 spillClean = 1, 130 spillDirty = 100, 131 spillImpossible = ~0u 132 }; 133 public: 134 virtual const char *getPassName() const { 135 return "Fast Register Allocator"; 136 } 137 138 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 139 AU.setPreservesCFG(); 140 AU.addRequiredID(PHIEliminationID); 141 AU.addRequiredID(TwoAddressInstructionPassID); 142 MachineFunctionPass::getAnalysisUsage(AU); 143 } 144 145 private: 146 bool runOnMachineFunction(MachineFunction &Fn); 147 void AllocateBasicBlock(); 148 void handleThroughOperands(MachineInstr *MI, 149 SmallVectorImpl<unsigned> &VirtDead); 150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 151 bool isLastUseOfLocalReg(MachineOperand&); 152 153 void addKillFlag(const LiveReg&); 154 void killVirtReg(LiveRegMap::iterator); 155 void killVirtReg(unsigned VirtReg); 156 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator); 157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 158 159 void usePhysReg(MachineOperand&); 160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 161 unsigned calcSpillCost(unsigned PhysReg) const; 162 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg); 163 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint); 164 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum, 165 unsigned VirtReg, unsigned Hint); 166 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum, 167 unsigned VirtReg, unsigned Hint); 168 void spillAll(MachineInstr *MI); 169 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg); 170 }; 171 char RAFast::ID = 0; 172} 173 174/// getStackSpaceFor - This allocates space for the specified virtual register 175/// to be held on the stack. 176int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { 177 // Find the location Reg would belong... 178 int SS = StackSlotForVirtReg[VirtReg]; 179 if (SS != -1) 180 return SS; // Already has space allocated? 181 182 // Allocate a new stack object for this spill location... 183 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 184 RC->getAlignment()); 185 186 // Assign the slot. 187 StackSlotForVirtReg[VirtReg] = FrameIdx; 188 return FrameIdx; 189} 190 191/// isLastUseOfLocalReg - Return true if MO is the only remaining reference to 192/// its virtual register, and it is guaranteed to be a block-local register. 193/// 194bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) { 195 // Check for non-debug uses or defs following MO. 196 // This is the most likely way to fail - fast path it. 197 MachineOperand *Next = &MO; 198 while ((Next = Next->getNextOperandForReg())) 199 if (!Next->isDebug()) 200 return false; 201 202 // If the register has ever been spilled or reloaded, we conservatively assume 203 // it is a global register used in multiple blocks. 204 if (StackSlotForVirtReg[MO.getReg()] != -1) 205 return false; 206 207 // Check that the use/def chain has exactly one operand - MO. 208 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO; 209} 210 211/// addKillFlag - Set kill flags on last use of a virtual register. 212void RAFast::addKillFlag(const LiveReg &LR) { 213 if (!LR.LastUse) return; 214 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); 215 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { 216 if (MO.getReg() == LR.PhysReg) 217 MO.setIsKill(); 218 else 219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); 220 } 221} 222 223/// killVirtReg - Mark virtreg as no longer available. 224void RAFast::killVirtReg(LiveRegMap::iterator LRI) { 225 addKillFlag(LRI->second); 226 const LiveReg &LR = LRI->second; 227 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping"); 228 PhysRegState[LR.PhysReg] = regFree; 229 // Erase from LiveVirtRegs unless we're spilling in bulk. 230 if (!isBulkSpilling) 231 LiveVirtRegs.erase(LRI); 232} 233 234/// killVirtReg - Mark virtreg as no longer available. 235void RAFast::killVirtReg(unsigned VirtReg) { 236 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 237 "killVirtReg needs a virtual register"); 238 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg); 239 if (LRI != LiveVirtRegs.end()) 240 killVirtReg(LRI); 241} 242 243/// spillVirtReg - This method spills the value specified by VirtReg into the 244/// corresponding stack slot if needed. 245void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { 246 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 247 "Spilling a physical register is illegal!"); 248 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg); 249 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register"); 250 spillVirtReg(MI, LRI); 251} 252 253/// spillVirtReg - Do the actual work of spilling. 254void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, 255 LiveRegMap::iterator LRI) { 256 LiveReg &LR = LRI->second; 257 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping"); 258 259 if (LR.Dirty) { 260 // If this physreg is used by the instruction, we want to kill it on the 261 // instruction, not on the spill. 262 bool SpillKill = LR.LastUse != MI; 263 LR.Dirty = false; 264 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI) 265 << " in " << PrintReg(LR.PhysReg, TRI)); 266 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first); 267 int FI = getStackSpaceFor(LRI->first, RC); 268 DEBUG(dbgs() << " to stack slot #" << FI << "\n"); 269 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); 270 ++NumStores; // Update statistics 271 272 // If this register is used by DBG_VALUE then insert new DBG_VALUE to 273 // identify spilled location as the place to find corresponding variable's 274 // value. 275 SmallVector<MachineInstr *, 4> &LRIDbgValues = LiveDbgValueMap[LRI->first]; 276 for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) { 277 MachineInstr *DBG = LRIDbgValues[li]; 278 const MDNode *MDPtr = 279 DBG->getOperand(DBG->getNumOperands()-1).getMetadata(); 280 int64_t Offset = 0; 281 if (DBG->getOperand(1).isImm()) 282 Offset = DBG->getOperand(1).getImm(); 283 DebugLoc DL; 284 if (MI == MBB->end()) { 285 // If MI is at basic block end then use last instruction's location. 286 MachineBasicBlock::iterator EI = MI; 287 DL = (--EI)->getDebugLoc(); 288 } 289 else 290 DL = MI->getDebugLoc(); 291 if (MachineInstr *NewDV = 292 TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) { 293 MachineBasicBlock *MBB = DBG->getParent(); 294 MBB->insert(MI, NewDV); 295 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV); 296 } 297 } 298 // Now this register is spilled there is should not be any DBG_VALUE pointing 299 // to this register because they are all pointing to spilled value now. 300 LRIDbgValues.clear(); 301 if (SpillKill) 302 LR.LastUse = 0; // Don't kill register again 303 } 304 killVirtReg(LRI); 305} 306 307/// spillAll - Spill all dirty virtregs without killing them. 308void RAFast::spillAll(MachineInstr *MI) { 309 if (LiveVirtRegs.empty()) return; 310 isBulkSpilling = true; 311 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order 312 // of spilling here is deterministic, if arbitrary. 313 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end(); 314 i != e; ++i) 315 spillVirtReg(MI, i); 316 LiveVirtRegs.clear(); 317 isBulkSpilling = false; 318} 319 320/// usePhysReg - Handle the direct use of a physical register. 321/// Check that the register is not used by a virtreg. 322/// Kill the physreg, marking it free. 323/// This may add implicit kills to MO->getParent() and invalidate MO. 324void RAFast::usePhysReg(MachineOperand &MO) { 325 unsigned PhysReg = MO.getReg(); 326 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && 327 "Bad usePhysReg operand"); 328 329 switch (PhysRegState[PhysReg]) { 330 case regDisabled: 331 break; 332 case regReserved: 333 PhysRegState[PhysReg] = regFree; 334 // Fall through 335 case regFree: 336 UsedInInstr.set(PhysReg); 337 MO.setIsKill(); 338 return; 339 default: 340 // The physreg was allocated to a virtual register. That means the value we 341 // wanted has been clobbered. 342 llvm_unreachable("Instruction uses an allocated register"); 343 } 344 345 // Maybe a superregister is reserved? 346 for (const unsigned *AS = TRI->getAliasSet(PhysReg); 347 unsigned Alias = *AS; ++AS) { 348 switch (PhysRegState[Alias]) { 349 case regDisabled: 350 break; 351 case regReserved: 352 assert(TRI->isSuperRegister(PhysReg, Alias) && 353 "Instruction is not using a subregister of a reserved register"); 354 // Leave the superregister in the working set. 355 PhysRegState[Alias] = regFree; 356 UsedInInstr.set(Alias); 357 MO.getParent()->addRegisterKilled(Alias, TRI, true); 358 return; 359 case regFree: 360 if (TRI->isSuperRegister(PhysReg, Alias)) { 361 // Leave the superregister in the working set. 362 UsedInInstr.set(Alias); 363 MO.getParent()->addRegisterKilled(Alias, TRI, true); 364 return; 365 } 366 // Some other alias was in the working set - clear it. 367 PhysRegState[Alias] = regDisabled; 368 break; 369 default: 370 llvm_unreachable("Instruction uses an alias of an allocated register"); 371 } 372 } 373 374 // All aliases are disabled, bring register into working set. 375 PhysRegState[PhysReg] = regFree; 376 UsedInInstr.set(PhysReg); 377 MO.setIsKill(); 378} 379 380/// definePhysReg - Mark PhysReg as reserved or free after spilling any 381/// virtregs. This is very similar to defineVirtReg except the physreg is 382/// reserved instead of allocated. 383void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg, 384 RegState NewState) { 385 UsedInInstr.set(PhysReg); 386 switch (unsigned VirtReg = PhysRegState[PhysReg]) { 387 case regDisabled: 388 break; 389 default: 390 spillVirtReg(MI, VirtReg); 391 // Fall through. 392 case regFree: 393 case regReserved: 394 PhysRegState[PhysReg] = NewState; 395 return; 396 } 397 398 // This is a disabled register, disable all aliases. 399 PhysRegState[PhysReg] = NewState; 400 for (const unsigned *AS = TRI->getAliasSet(PhysReg); 401 unsigned Alias = *AS; ++AS) { 402 switch (unsigned VirtReg = PhysRegState[Alias]) { 403 case regDisabled: 404 break; 405 default: 406 spillVirtReg(MI, VirtReg); 407 // Fall through. 408 case regFree: 409 case regReserved: 410 PhysRegState[Alias] = regDisabled; 411 if (TRI->isSuperRegister(PhysReg, Alias)) 412 return; 413 break; 414 } 415 } 416} 417 418 419// calcSpillCost - Return the cost of spilling clearing out PhysReg and 420// aliases so it is free for allocation. 421// Returns 0 when PhysReg is free or disabled with all aliases disabled - it 422// can be allocated directly. 423// Returns spillImpossible when PhysReg or an alias can't be spilled. 424unsigned RAFast::calcSpillCost(unsigned PhysReg) const { 425 if (UsedInInstr.test(PhysReg)) { 426 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); 427 return spillImpossible; 428 } 429 switch (unsigned VirtReg = PhysRegState[PhysReg]) { 430 case regDisabled: 431 break; 432 case regFree: 433 return 0; 434 case regReserved: 435 DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " 436 << PrintReg(PhysReg, TRI) << " is reserved already.\n"); 437 return spillImpossible; 438 default: 439 return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean; 440 } 441 442 // This is a disabled register, add up cost of aliases. 443 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); 444 unsigned Cost = 0; 445 for (const unsigned *AS = TRI->getAliasSet(PhysReg); 446 unsigned Alias = *AS; ++AS) { 447 if (UsedInInstr.test(Alias)) 448 return spillImpossible; 449 switch (unsigned VirtReg = PhysRegState[Alias]) { 450 case regDisabled: 451 break; 452 case regFree: 453 ++Cost; 454 break; 455 case regReserved: 456 return spillImpossible; 457 default: 458 Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean; 459 break; 460 } 461 } 462 return Cost; 463} 464 465 466/// assignVirtToPhysReg - This method updates local state so that we know 467/// that PhysReg is the proper container for VirtReg now. The physical 468/// register must not be used for anything else when this is called. 469/// 470void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) { 471 DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to " 472 << PrintReg(PhysReg, TRI) << "\n"); 473 PhysRegState[PhysReg] = LRE.first; 474 assert(!LRE.second.PhysReg && "Already assigned a physreg"); 475 LRE.second.PhysReg = PhysReg; 476} 477 478/// allocVirtReg - Allocate a physical register for VirtReg. 479void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) { 480 const unsigned VirtReg = LRE.first; 481 482 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 483 "Can only allocate virtual registers"); 484 485 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 486 487 // Ignore invalid hints. 488 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || 489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint))) 490 Hint = 0; 491 492 // Take hint when possible. 493 if (Hint) { 494 // Ignore the hint if we would have to spill a dirty register. 495 unsigned Cost = calcSpillCost(Hint); 496 if (Cost < spillDirty) { 497 if (Cost) 498 definePhysReg(MI, Hint, regFree); 499 return assignVirtToPhysReg(LRE, Hint); 500 } 501 } 502 503 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC); 504 505 // First try to find a completely free register. 506 for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { 507 unsigned PhysReg = *I; 508 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) 509 return assignVirtToPhysReg(LRE, PhysReg); 510 } 511 512 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " 513 << RC->getName() << "\n"); 514 515 unsigned BestReg = 0, BestCost = spillImpossible; 516 for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { 517 unsigned Cost = calcSpillCost(*I); 518 DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n"); 519 DEBUG(dbgs() << "\tCost: " << Cost << "\n"); 520 DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); 521 // Cost is 0 when all aliases are already disabled. 522 if (Cost == 0) 523 return assignVirtToPhysReg(LRE, *I); 524 if (Cost < BestCost) 525 BestReg = *I, BestCost = Cost; 526 } 527 528 if (BestReg) { 529 definePhysReg(MI, BestReg, regFree); 530 return assignVirtToPhysReg(LRE, BestReg); 531 } 532 533 // Nothing we can do. 534 std::string msg; 535 raw_string_ostream Msg(msg); 536 Msg << "Ran out of registers during register allocation!"; 537 if (MI->isInlineAsm()) { 538 Msg << "\nPlease check your inline asm statement for " 539 << "invalid constraints:\n"; 540 MI->print(Msg, TM); 541 } 542 report_fatal_error(Msg.str()); 543} 544 545/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty. 546RAFast::LiveRegMap::iterator 547RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, 548 unsigned VirtReg, unsigned Hint) { 549 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 550 "Not a virtual register"); 551 LiveRegMap::iterator LRI; 552 bool New; 553 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg())); 554 LiveReg &LR = LRI->second; 555 if (New) { 556 // If there is no hint, peek at the only use of this register. 557 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) && 558 MRI->hasOneNonDBGUse(VirtReg)) { 559 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg); 560 // It's a copy, use the destination register as a hint. 561 if (UseMI.isCopyLike()) 562 Hint = UseMI.getOperand(0).getReg(); 563 } 564 allocVirtReg(MI, *LRI, Hint); 565 } else if (LR.LastUse) { 566 // Redefining a live register - kill at the last use, unless it is this 567 // instruction defining VirtReg multiple times. 568 if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse()) 569 addKillFlag(LR); 570 } 571 assert(LR.PhysReg && "Register not assigned"); 572 LR.LastUse = MI; 573 LR.LastOpNum = OpNum; 574 LR.Dirty = true; 575 UsedInInstr.set(LR.PhysReg); 576 return LRI; 577} 578 579/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it. 580RAFast::LiveRegMap::iterator 581RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, 582 unsigned VirtReg, unsigned Hint) { 583 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 584 "Not a virtual register"); 585 LiveRegMap::iterator LRI; 586 bool New; 587 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg())); 588 LiveReg &LR = LRI->second; 589 MachineOperand &MO = MI->getOperand(OpNum); 590 if (New) { 591 allocVirtReg(MI, *LRI, Hint); 592 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 593 int FrameIndex = getStackSpaceFor(VirtReg, RC); 594 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into " 595 << PrintReg(LR.PhysReg, TRI) << "\n"); 596 TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI); 597 ++NumLoads; 598 } else if (LR.Dirty) { 599 if (isLastUseOfLocalReg(MO)) { 600 DEBUG(dbgs() << "Killing last use: " << MO << "\n"); 601 if (MO.isUse()) 602 MO.setIsKill(); 603 else 604 MO.setIsDead(); 605 } else if (MO.isKill()) { 606 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n"); 607 MO.setIsKill(false); 608 } else if (MO.isDead()) { 609 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n"); 610 MO.setIsDead(false); 611 } 612 } else if (MO.isKill()) { 613 // We must remove kill flags from uses of reloaded registers because the 614 // register would be killed immediately, and there might be a second use: 615 // %foo = OR %x<kill>, %x 616 // This would cause a second reload of %x into a different register. 617 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n"); 618 MO.setIsKill(false); 619 } else if (MO.isDead()) { 620 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n"); 621 MO.setIsDead(false); 622 } 623 assert(LR.PhysReg && "Register not assigned"); 624 LR.LastUse = MI; 625 LR.LastOpNum = OpNum; 626 UsedInInstr.set(LR.PhysReg); 627 return LRI; 628} 629 630// setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering 631// subregs. This may invalidate any operand pointers. 632// Return true if the operand kills its register. 633bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) { 634 MachineOperand &MO = MI->getOperand(OpNum); 635 if (!MO.getSubReg()) { 636 MO.setReg(PhysReg); 637 return MO.isKill() || MO.isDead(); 638 } 639 640 // Handle subregister index. 641 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); 642 MO.setSubReg(0); 643 644 // A kill flag implies killing the full register. Add corresponding super 645 // register kill. 646 if (MO.isKill()) { 647 MI->addRegisterKilled(PhysReg, TRI, true); 648 return true; 649 } 650 return MO.isDead(); 651} 652 653// Handle special instruction operand like early clobbers and tied ops when 654// there are additional physreg defines. 655void RAFast::handleThroughOperands(MachineInstr *MI, 656 SmallVectorImpl<unsigned> &VirtDead) { 657 DEBUG(dbgs() << "Scanning for through registers:"); 658 SmallSet<unsigned, 8> ThroughRegs; 659 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 660 MachineOperand &MO = MI->getOperand(i); 661 if (!MO.isReg()) continue; 662 unsigned Reg = MO.getReg(); 663 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 664 continue; 665 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) || 666 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 667 if (ThroughRegs.insert(Reg)) 668 DEBUG(dbgs() << ' ' << PrintReg(Reg)); 669 } 670 } 671 672 // If any physreg defines collide with preallocated through registers, 673 // we must spill and reallocate. 674 DEBUG(dbgs() << "\nChecking for physdef collisions.\n"); 675 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 676 MachineOperand &MO = MI->getOperand(i); 677 if (!MO.isReg() || !MO.isDef()) continue; 678 unsigned Reg = MO.getReg(); 679 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 680 UsedInInstr.set(Reg); 681 if (ThroughRegs.count(PhysRegState[Reg])) 682 definePhysReg(MI, Reg, regFree); 683 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { 684 UsedInInstr.set(*AS); 685 if (ThroughRegs.count(PhysRegState[*AS])) 686 definePhysReg(MI, *AS, regFree); 687 } 688 } 689 690 SmallVector<unsigned, 8> PartialDefs; 691 DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n"); 692 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 693 MachineOperand &MO = MI->getOperand(i); 694 if (!MO.isReg()) continue; 695 unsigned Reg = MO.getReg(); 696 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 697 if (MO.isUse()) { 698 unsigned DefIdx = 0; 699 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; 700 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand " 701 << DefIdx << ".\n"); 702 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0); 703 unsigned PhysReg = LRI->second.PhysReg; 704 setPhysReg(MI, i, PhysReg); 705 // Note: we don't update the def operand yet. That would cause the normal 706 // def-scan to attempt spilling. 707 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { 708 DEBUG(dbgs() << "Partial redefine: " << MO << "\n"); 709 // Reload the register, but don't assign to the operand just yet. 710 // That would confuse the later phys-def processing pass. 711 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0); 712 PartialDefs.push_back(LRI->second.PhysReg); 713 } else if (MO.isEarlyClobber()) { 714 // Note: defineVirtReg may invalidate MO. 715 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0); 716 unsigned PhysReg = LRI->second.PhysReg; 717 if (setPhysReg(MI, i, PhysReg)) 718 VirtDead.push_back(Reg); 719 } 720 } 721 722 // Restore UsedInInstr to a state usable for allocating normal virtual uses. 723 UsedInInstr.reset(); 724 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 725 MachineOperand &MO = MI->getOperand(i); 726 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; 727 unsigned Reg = MO.getReg(); 728 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 729 DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI) 730 << " as used in instr\n"); 731 UsedInInstr.set(Reg); 732 } 733 734 // Also mark PartialDefs as used to avoid reallocation. 735 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i) 736 UsedInInstr.set(PartialDefs[i]); 737} 738 739void RAFast::AllocateBasicBlock() { 740 DEBUG(dbgs() << "\nAllocating " << *MBB); 741 742 // FIXME: This should probably be added by instruction selection instead? 743 // If the last instruction in the block is a return, make sure to mark it as 744 // using all of the live-out values in the function. Things marked both call 745 // and return are tail calls; do not do this for them. The tail callee need 746 // not take the same registers as input that it produces as output, and there 747 // are dependencies for its input registers elsewhere. 748 if (!MBB->empty() && MBB->back().getDesc().isReturn() && 749 !MBB->back().getDesc().isCall()) { 750 MachineInstr *Ret = &MBB->back(); 751 752 for (MachineRegisterInfo::liveout_iterator 753 I = MF->getRegInfo().liveout_begin(), 754 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 755 assert(TargetRegisterInfo::isPhysicalRegister(*I) && 756 "Cannot have a live-out virtual register."); 757 758 // Add live-out registers as implicit uses. 759 Ret->addRegisterKilled(*I, TRI, true); 760 } 761 } 762 763 PhysRegState.assign(TRI->getNumRegs(), regDisabled); 764 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?"); 765 766 MachineBasicBlock::iterator MII = MBB->begin(); 767 768 // Add live-in registers as live. 769 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 770 E = MBB->livein_end(); I != E; ++I) 771 if (RegClassInfo.isAllocatable(*I)) 772 definePhysReg(MII, *I, regReserved); 773 774 SmallVector<unsigned, 8> VirtDead; 775 SmallVector<MachineInstr*, 32> Coalesced; 776 777 // Otherwise, sequentially allocate each instruction in the MBB. 778 while (MII != MBB->end()) { 779 MachineInstr *MI = MII++; 780 const TargetInstrDesc &TID = MI->getDesc(); 781 DEBUG({ 782 dbgs() << "\n>> " << *MI << "Regs:"; 783 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { 784 if (PhysRegState[Reg] == regDisabled) continue; 785 dbgs() << " " << TRI->getName(Reg); 786 switch(PhysRegState[Reg]) { 787 case regFree: 788 break; 789 case regReserved: 790 dbgs() << "*"; 791 break; 792 default: 793 dbgs() << '=' << PrintReg(PhysRegState[Reg]); 794 if (LiveVirtRegs[PhysRegState[Reg]].Dirty) 795 dbgs() << "*"; 796 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg && 797 "Bad inverse map"); 798 break; 799 } 800 } 801 dbgs() << '\n'; 802 // Check that LiveVirtRegs is the inverse. 803 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), 804 e = LiveVirtRegs.end(); i != e; ++i) { 805 assert(TargetRegisterInfo::isVirtualRegister(i->first) && 806 "Bad map key"); 807 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) && 808 "Bad map value"); 809 assert(PhysRegState[i->second.PhysReg] == i->first && 810 "Bad inverse map"); 811 } 812 }); 813 814 // Debug values are not allowed to change codegen in any way. 815 if (MI->isDebugValue()) { 816 bool ScanDbgValue = true; 817 while (ScanDbgValue) { 818 ScanDbgValue = false; 819 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 820 MachineOperand &MO = MI->getOperand(i); 821 if (!MO.isReg()) continue; 822 unsigned Reg = MO.getReg(); 823 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 824 LiveDbgValueMap[Reg].push_back(MI); 825 LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg); 826 if (LRI != LiveVirtRegs.end()) 827 setPhysReg(MI, i, LRI->second.PhysReg); 828 else { 829 int SS = StackSlotForVirtReg[Reg]; 830 if (SS == -1) { 831 // We can't allocate a physreg for a DebugValue, sorry! 832 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); 833 MO.setReg(0); 834 } 835 else { 836 // Modify DBG_VALUE now that the value is in a spill slot. 837 int64_t Offset = MI->getOperand(1).getImm(); 838 const MDNode *MDPtr = 839 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 840 DebugLoc DL = MI->getDebugLoc(); 841 if (MachineInstr *NewDV = 842 TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) { 843 DEBUG(dbgs() << "Modifying debug info due to spill:" << 844 "\t" << *MI); 845 MachineBasicBlock *MBB = MI->getParent(); 846 MBB->insert(MBB->erase(MI), NewDV); 847 // Scan NewDV operands from the beginning. 848 MI = NewDV; 849 ScanDbgValue = true; 850 break; 851 } else { 852 // We can't allocate a physreg for a DebugValue; sorry! 853 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); 854 MO.setReg(0); 855 } 856 } 857 } 858 } 859 } 860 // Next instruction. 861 continue; 862 } 863 864 // If this is a copy, we may be able to coalesce. 865 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0; 866 if (MI->isCopy()) { 867 CopyDst = MI->getOperand(0).getReg(); 868 CopySrc = MI->getOperand(1).getReg(); 869 CopyDstSub = MI->getOperand(0).getSubReg(); 870 CopySrcSub = MI->getOperand(1).getSubReg(); 871 } 872 873 // Track registers used by instruction. 874 UsedInInstr.reset(); 875 876 // First scan. 877 // Mark physreg uses and early clobbers as used. 878 // Find the end of the virtreg operands 879 unsigned VirtOpEnd = 0; 880 bool hasTiedOps = false; 881 bool hasEarlyClobbers = false; 882 bool hasPartialRedefs = false; 883 bool hasPhysDefs = false; 884 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 885 MachineOperand &MO = MI->getOperand(i); 886 if (!MO.isReg()) continue; 887 unsigned Reg = MO.getReg(); 888 if (!Reg) continue; 889 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 890 VirtOpEnd = i+1; 891 if (MO.isUse()) { 892 hasTiedOps = hasTiedOps || 893 TID.getOperandConstraint(i, TOI::TIED_TO) != -1; 894 } else { 895 if (MO.isEarlyClobber()) 896 hasEarlyClobbers = true; 897 if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) 898 hasPartialRedefs = true; 899 } 900 continue; 901 } 902 if (!RegClassInfo.isAllocatable(Reg)) continue; 903 if (MO.isUse()) { 904 usePhysReg(MO); 905 } else if (MO.isEarlyClobber()) { 906 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? 907 regFree : regReserved); 908 hasEarlyClobbers = true; 909 } else 910 hasPhysDefs = true; 911 } 912 913 // The instruction may have virtual register operands that must be allocated 914 // the same register at use-time and def-time: early clobbers and tied 915 // operands. If there are also physical defs, these registers must avoid 916 // both physical defs and uses, making them more constrained than normal 917 // operands. 918 // Similarly, if there are multiple defs and tied operands, we must make 919 // sure the same register is allocated to uses and defs. 920 // We didn't detect inline asm tied operands above, so just make this extra 921 // pass for all inline asm. 922 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs || 923 (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) { 924 handleThroughOperands(MI, VirtDead); 925 // Don't attempt coalescing when we have funny stuff going on. 926 CopyDst = 0; 927 // Pretend we have early clobbers so the use operands get marked below. 928 // This is not necessary for the common case of a single tied use. 929 hasEarlyClobbers = true; 930 } 931 932 // Second scan. 933 // Allocate virtreg uses. 934 for (unsigned i = 0; i != VirtOpEnd; ++i) { 935 MachineOperand &MO = MI->getOperand(i); 936 if (!MO.isReg()) continue; 937 unsigned Reg = MO.getReg(); 938 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 939 if (MO.isUse()) { 940 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst); 941 unsigned PhysReg = LRI->second.PhysReg; 942 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0; 943 if (setPhysReg(MI, i, PhysReg)) 944 killVirtReg(LRI); 945 } 946 } 947 948 MRI->addPhysRegsUsed(UsedInInstr); 949 950 // Track registers defined by instruction - early clobbers and tied uses at 951 // this point. 952 UsedInInstr.reset(); 953 if (hasEarlyClobbers) { 954 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 955 MachineOperand &MO = MI->getOperand(i); 956 if (!MO.isReg()) continue; 957 unsigned Reg = MO.getReg(); 958 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 959 // Look for physreg defs and tied uses. 960 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue; 961 UsedInInstr.set(Reg); 962 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 963 UsedInInstr.set(*AS); 964 } 965 } 966 967 unsigned DefOpEnd = MI->getNumOperands(); 968 if (TID.isCall()) { 969 // Spill all virtregs before a call. This serves two purposes: 1. If an 970 // exception is thrown, the landing pad is going to expect to find 971 // registers in their spill slots, and 2. we don't have to wade through 972 // all the <imp-def> operands on the call instruction. 973 DefOpEnd = VirtOpEnd; 974 DEBUG(dbgs() << " Spilling remaining registers before call.\n"); 975 spillAll(MI); 976 977 // The imp-defs are skipped below, but we still need to mark those 978 // registers as used by the function. 979 SkippedInstrs.insert(&TID); 980 } 981 982 // Third scan. 983 // Allocate defs and collect dead defs. 984 for (unsigned i = 0; i != DefOpEnd; ++i) { 985 MachineOperand &MO = MI->getOperand(i); 986 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) 987 continue; 988 unsigned Reg = MO.getReg(); 989 990 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 991 if (!RegClassInfo.isAllocatable(Reg)) continue; 992 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? 993 regFree : regReserved); 994 continue; 995 } 996 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc); 997 unsigned PhysReg = LRI->second.PhysReg; 998 if (setPhysReg(MI, i, PhysReg)) { 999 VirtDead.push_back(Reg); 1000 CopyDst = 0; // cancel coalescing; 1001 } else 1002 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0; 1003 } 1004 1005 // Kill dead defs after the scan to ensure that multiple defs of the same 1006 // register are allocated identically. We didn't need to do this for uses 1007 // because we are crerating our own kill flags, and they are always at the 1008 // last use. 1009 for (unsigned i = 0, e = VirtDead.size(); i != e; ++i) 1010 killVirtReg(VirtDead[i]); 1011 VirtDead.clear(); 1012 1013 MRI->addPhysRegsUsed(UsedInInstr); 1014 1015 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) { 1016 DEBUG(dbgs() << "-- coalescing: " << *MI); 1017 Coalesced.push_back(MI); 1018 } else { 1019 DEBUG(dbgs() << "<< " << *MI); 1020 } 1021 } 1022 1023 // Spill all physical registers holding virtual registers now. 1024 DEBUG(dbgs() << "Spilling live registers at end of block.\n"); 1025 spillAll(MBB->getFirstTerminator()); 1026 1027 // Erase all the coalesced copies. We are delaying it until now because 1028 // LiveVirtRegs might refer to the instrs. 1029 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i) 1030 MBB->erase(Coalesced[i]); 1031 NumCopies += Coalesced.size(); 1032 1033 DEBUG(MBB->dump()); 1034} 1035 1036/// runOnMachineFunction - Register allocate the whole function 1037/// 1038bool RAFast::runOnMachineFunction(MachineFunction &Fn) { 1039 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n" 1040 << "********** Function: " 1041 << ((Value*)Fn.getFunction())->getName() << '\n'); 1042 MF = &Fn; 1043 MRI = &MF->getRegInfo(); 1044 TM = &Fn.getTarget(); 1045 TRI = TM->getRegisterInfo(); 1046 TII = TM->getInstrInfo(); 1047 RegClassInfo.runOnMachineFunction(Fn); 1048 UsedInInstr.resize(TRI->getNumRegs()); 1049 1050 // initialize the virtual->physical register map to have a 'null' 1051 // mapping for all virtual registers 1052 StackSlotForVirtReg.resize(MRI->getNumVirtRegs()); 1053 1054 // Loop over all of the basic blocks, eliminating virtual register references 1055 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end(); 1056 MBBi != MBBe; ++MBBi) { 1057 MBB = &*MBBi; 1058 AllocateBasicBlock(); 1059 } 1060 1061 // Make sure the set of used physregs is closed under subreg operations. 1062 MRI->closePhysRegsUsed(*TRI); 1063 1064 // Add the clobber lists for all the instructions we skipped earlier. 1065 for (SmallPtrSet<const TargetInstrDesc*, 4>::const_iterator 1066 I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I) 1067 if (const unsigned *Defs = (*I)->getImplicitDefs()) 1068 while (*Defs) 1069 MRI->setPhysRegUsed(*Defs++); 1070 1071 SkippedInstrs.clear(); 1072 StackSlotForVirtReg.clear(); 1073 LiveDbgValueMap.clear(); 1074 return true; 1075} 1076 1077FunctionPass *llvm::createFastRegisterAllocator() { 1078 return new RAFast(); 1079} 1080