RegAllocFast.cpp revision 396618b43a85e12d290a90b181c6af5d7c0c5f11 
1//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This register allocator allocates registers to a basic block at a time,
11// attempting to keep values in registers and reusing registers as appropriate.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "RegisterClassInfo.h"
17#include "llvm/BasicBlock.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/CodeGen/MachineInstr.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/Passes.h"
24#include "llvm/CodeGen/RegAllocRegistry.h"
25#include "llvm/Target/TargetInstrInfo.h"
26#include "llvm/Target/TargetMachine.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/raw_ostream.h"
31#include "llvm/ADT/DenseMap.h"
32#include "llvm/ADT/IndexedMap.h"
33#include "llvm/ADT/SmallSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/SparseSet.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/STLExtras.h"
38#include <algorithm>
39using namespace llvm;
40
41STATISTIC(NumStores, "Number of stores added");
42STATISTIC(NumLoads , "Number of loads added");
43STATISTIC(NumCopies, "Number of copies coalesced");
44
45static RegisterRegAlloc
46  fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
47
48namespace {
49  class RAFast : public MachineFunctionPass {
50  public:
51    static char ID;
52    RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1),
53               isBulkSpilling(false) {}
54  private:
55    const TargetMachine *TM;
56    MachineFunction *MF;
57    MachineRegisterInfo *MRI;
58    const TargetRegisterInfo *TRI;
59    const TargetInstrInfo *TII;
60    RegisterClassInfo RegClassInfo;
61
62    // Basic block currently being allocated.
63    MachineBasicBlock *MBB;
64
65    // StackSlotForVirtReg - Maps virtual regs to the frame index where these
66    // values are spilled.
67    IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
68
69    // Everything we know about a live virtual register.
70    struct LiveReg {
71      MachineInstr *LastUse;    // Last instr to use reg.
72      unsigned VirtReg;         // Virtual register number.
73      unsigned PhysReg;         // Currently held here.
74      unsigned short LastOpNum; // OpNum on LastUse.
75      bool Dirty;               // Register needs spill.
76
77      explicit LiveReg(unsigned v)
78        : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {}
79
80      unsigned getSparseSetIndex() const {
81        return TargetRegisterInfo::virtReg2Index(VirtReg);
82      }
83    };
84
85    typedef SparseSet<LiveReg> LiveRegMap;
86
87    // LiveVirtRegs - This map contains entries for each virtual register
88    // that is currently available in a physical register.
89    LiveRegMap LiveVirtRegs;
90
91    DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
92
93    // RegState - Track the state of a physical register.
94    enum RegState {
95      // A disabled register is not available for allocation, but an alias may
96      // be in use. A register can only be moved out of the disabled state if
97      // all aliases are disabled.
98      regDisabled,
99
100      // A free register is not currently in use and can be allocated
101      // immediately without checking aliases.
102      regFree,
103
104      // A reserved register has been assigned explicitly (e.g., setting up a
105      // call parameter), and it remains reserved until it is used.
106      regReserved
107
108      // A register state may also be a virtual register number, indication that
109      // the physical register is currently allocated to a virtual register. In
110      // that case, LiveVirtRegs contains the inverse mapping.
111    };
112
113    // PhysRegState - One of the RegState enums, or a virtreg.
114    std::vector<unsigned> PhysRegState;
115
116    // UsedInInstr - BitVector of physregs that are used in the current
117    // instruction, and so cannot be allocated.
118    BitVector UsedInInstr;
119
120    // SkippedInstrs - Descriptors of instructions whose clobber list was
121    // ignored because all registers were spilled. It is still necessary to
122    // mark all the clobbered registers as used by the function.
123    SmallPtrSet<const MCInstrDesc*, 4> SkippedInstrs;
124
125    // isBulkSpilling - This flag is set when LiveRegMap will be cleared
126    // completely after spilling all live registers. LiveRegMap entries should
127    // not be erased.
128    bool isBulkSpilling;
129
130    enum {
131      spillClean = 1,
132      spillDirty = 100,
133      spillImpossible = ~0u
134    };
135  public:
136    virtual const char *getPassName() const {
137      return "Fast Register Allocator";
138    }
139
140    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
141      AU.setPreservesCFG();
142      MachineFunctionPass::getAnalysisUsage(AU);
143    }
144
145  private:
146    bool runOnMachineFunction(MachineFunction &Fn);
147    void AllocateBasicBlock();
148    void handleThroughOperands(MachineInstr *MI,
149                               SmallVectorImpl<unsigned> &VirtDead);
150    int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
151    bool isLastUseOfLocalReg(MachineOperand&);
152
153    void addKillFlag(const LiveReg&);
154    void killVirtReg(LiveRegMap::iterator);
155    void killVirtReg(unsigned VirtReg);
156    void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
157    void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
158
159    void usePhysReg(MachineOperand&);
160    void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
161    unsigned calcSpillCost(unsigned PhysReg) const;
162    void assignVirtToPhysReg(LiveReg&, unsigned PhysReg);
163    LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
164      return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
165    }
166    LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const {
167      return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
168    }
169    LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
170    LiveRegMap::iterator allocVirtReg(MachineInstr *MI, LiveRegMap::iterator,
171                                      unsigned Hint);
172    LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
173                                       unsigned VirtReg, unsigned Hint);
174    LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
175                                       unsigned VirtReg, unsigned Hint);
176    void spillAll(MachineInstr *MI);
177    bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
178    void addRetOperands(MachineBasicBlock *MBB);
179  };
180  char RAFast::ID = 0;
181}
182
183/// getStackSpaceFor - This allocates space for the specified virtual register
184/// to be held on the stack.
185int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
186  // Find the location Reg would belong...
187  int SS = StackSlotForVirtReg[VirtReg];
188  if (SS != -1)
189    return SS;          // Already has space allocated?
190
191  // Allocate a new stack object for this spill location...
192  int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
193                                                            RC->getAlignment());
194
195  // Assign the slot.
196  StackSlotForVirtReg[VirtReg] = FrameIdx;
197  return FrameIdx;
198}
199
200/// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
201/// its virtual register, and it is guaranteed to be a block-local register.
202///
203bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
204  // Check for non-debug uses or defs following MO.
205  // This is the most likely way to fail - fast path it.
206  MachineOperand *Next = &MO;
207  while ((Next = Next->getNextOperandForReg()))
208    if (!Next->isDebug())
209      return false;
210
211  // If the register has ever been spilled or reloaded, we conservatively assume
212  // it is a global register used in multiple blocks.
213  if (StackSlotForVirtReg[MO.getReg()] != -1)
214    return false;
215
216  // Check that the use/def chain has exactly one operand - MO.
217  return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
218}
219
220/// addKillFlag - Set kill flags on last use of a virtual register.
221void RAFast::addKillFlag(const LiveReg &LR) {
222  if (!LR.LastUse) return;
223  MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
224  if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
225    if (MO.getReg() == LR.PhysReg)
226      MO.setIsKill();
227    else
228      LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
229  }
230}
231
232/// killVirtReg - Mark virtreg as no longer available.
233void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
234  addKillFlag(*LRI);
235  assert(PhysRegState[LRI->PhysReg] == LRI->VirtReg &&
236         "Broken RegState mapping");
237  PhysRegState[LRI->PhysReg] = regFree;
238  // Erase from LiveVirtRegs unless we're spilling in bulk.
239  if (!isBulkSpilling)
240    LiveVirtRegs.erase(LRI);
241}
242
243/// killVirtReg - Mark virtreg as no longer available.
244void RAFast::killVirtReg(unsigned VirtReg) {
245  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
246         "killVirtReg needs a virtual register");
247  LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
248  if (LRI != LiveVirtRegs.end())
249    killVirtReg(LRI);
250}
251
252/// spillVirtReg - This method spills the value specified by VirtReg into the
253/// corresponding stack slot if needed.
254void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
255  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
256         "Spilling a physical register is illegal!");
257  LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
258  assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
259  spillVirtReg(MI, LRI);
260}
261
262/// spillVirtReg - Do the actual work of spilling.
263void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
264                          LiveRegMap::iterator LRI) {
265  LiveReg &LR = *LRI;
266  assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping");
267
268  if (LR.Dirty) {
269    // If this physreg is used by the instruction, we want to kill it on the
270    // instruction, not on the spill.
271    bool SpillKill = LR.LastUse != MI;
272    LR.Dirty = false;
273    DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
274                 << " in " << PrintReg(LR.PhysReg, TRI));
275    const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
276    int FI = getStackSpaceFor(LRI->VirtReg, RC);
277    DEBUG(dbgs() << " to stack slot #" << FI << "\n");
278    TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
279    ++NumStores;   // Update statistics
280
281    // If this register is used by DBG_VALUE then insert new DBG_VALUE to
282    // identify spilled location as the place to find corresponding variable's
283    // value.
284    SmallVector<MachineInstr *, 4> &LRIDbgValues =
285      LiveDbgValueMap[LRI->VirtReg];
286    for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
287      MachineInstr *DBG = LRIDbgValues[li];
288      const MDNode *MDPtr =
289        DBG->getOperand(DBG->getNumOperands()-1).getMetadata();
290      int64_t Offset = 0;
291      if (DBG->getOperand(1).isImm())
292        Offset = DBG->getOperand(1).getImm();
293      DebugLoc DL;
294      if (MI == MBB->end()) {
295        // If MI is at basic block end then use last instruction's location.
296        MachineBasicBlock::iterator EI = MI;
297        DL = (--EI)->getDebugLoc();
298      }
299      else
300        DL = MI->getDebugLoc();
301      if (MachineInstr *NewDV =
302          TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) {
303        MachineBasicBlock *MBB = DBG->getParent();
304        MBB->insert(MI, NewDV);
305        DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
306      }
307    }
308    // Now this register is spilled there is should not be any DBG_VALUE
309    // pointing to this register because they are all pointing to spilled value
310    // now.
311    LRIDbgValues.clear();
312    if (SpillKill)
313      LR.LastUse = 0; // Don't kill register again
314  }
315  killVirtReg(LRI);
316}
317
318/// spillAll - Spill all dirty virtregs without killing them.
319void RAFast::spillAll(MachineInstr *MI) {
320  if (LiveVirtRegs.empty()) return;
321  isBulkSpilling = true;
322  // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
323  // of spilling here is deterministic, if arbitrary.
324  for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
325       i != e; ++i)
326    spillVirtReg(MI, i);
327  LiveVirtRegs.clear();
328  isBulkSpilling = false;
329}
330
331/// usePhysReg - Handle the direct use of a physical register.
332/// Check that the register is not used by a virtreg.
333/// Kill the physreg, marking it free.
334/// This may add implicit kills to MO->getParent() and invalidate MO.
335void RAFast::usePhysReg(MachineOperand &MO) {
336  unsigned PhysReg = MO.getReg();
337  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
338         "Bad usePhysReg operand");
339
340  switch (PhysRegState[PhysReg]) {
341  case regDisabled:
342    break;
343  case regReserved:
344    PhysRegState[PhysReg] = regFree;
345    // Fall through
346  case regFree:
347    UsedInInstr.set(PhysReg);
348    MO.setIsKill();
349    return;
350  default:
351    // The physreg was allocated to a virtual register. That means the value we
352    // wanted has been clobbered.
353    llvm_unreachable("Instruction uses an allocated register");
354  }
355
356  // Maybe a superregister is reserved?
357  for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
358    unsigned Alias = *AI;
359    switch (PhysRegState[Alias]) {
360    case regDisabled:
361      break;
362    case regReserved:
363      assert(TRI->isSuperRegister(PhysReg, Alias) &&
364             "Instruction is not using a subregister of a reserved register");
365      // Leave the superregister in the working set.
366      PhysRegState[Alias] = regFree;
367      UsedInInstr.set(Alias);
368      MO.getParent()->addRegisterKilled(Alias, TRI, true);
369      return;
370    case regFree:
371      if (TRI->isSuperRegister(PhysReg, Alias)) {
372        // Leave the superregister in the working set.
373        UsedInInstr.set(Alias);
374        MO.getParent()->addRegisterKilled(Alias, TRI, true);
375        return;
376      }
377      // Some other alias was in the working set - clear it.
378      PhysRegState[Alias] = regDisabled;
379      break;
380    default:
381      llvm_unreachable("Instruction uses an alias of an allocated register");
382    }
383  }
384
385  // All aliases are disabled, bring register into working set.
386  PhysRegState[PhysReg] = regFree;
387  UsedInInstr.set(PhysReg);
388  MO.setIsKill();
389}
390
391/// definePhysReg - Mark PhysReg as reserved or free after spilling any
392/// virtregs. This is very similar to defineVirtReg except the physreg is
393/// reserved instead of allocated.
394void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
395                           RegState NewState) {
396  UsedInInstr.set(PhysReg);
397  switch (unsigned VirtReg = PhysRegState[PhysReg]) {
398  case regDisabled:
399    break;
400  default:
401    spillVirtReg(MI, VirtReg);
402    // Fall through.
403  case regFree:
404  case regReserved:
405    PhysRegState[PhysReg] = NewState;
406    return;
407  }
408
409  // This is a disabled register, disable all aliases.
410  PhysRegState[PhysReg] = NewState;
411  for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
412    unsigned Alias = *AI;
413    switch (unsigned VirtReg = PhysRegState[Alias]) {
414    case regDisabled:
415      break;
416    default:
417      spillVirtReg(MI, VirtReg);
418      // Fall through.
419    case regFree:
420    case regReserved:
421      PhysRegState[Alias] = regDisabled;
422      if (TRI->isSuperRegister(PhysReg, Alias))
423        return;
424      break;
425    }
426  }
427}
428
429
430// calcSpillCost - Return the cost of spilling clearing out PhysReg and
431// aliases so it is free for allocation.
432// Returns 0 when PhysReg is free or disabled with all aliases disabled - it
433// can be allocated directly.
434// Returns spillImpossible when PhysReg or an alias can't be spilled.
435unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
436  if (UsedInInstr.test(PhysReg)) {
437    DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
438    return spillImpossible;
439  }
440  switch (unsigned VirtReg = PhysRegState[PhysReg]) {
441  case regDisabled:
442    break;
443  case regFree:
444    return 0;
445  case regReserved:
446    DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
447                 << PrintReg(PhysReg, TRI) << " is reserved already.\n");
448    return spillImpossible;
449  default: {
450    LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
451    assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
452    return I->Dirty ? spillDirty : spillClean;
453  }
454  }
455
456  // This is a disabled register, add up cost of aliases.
457  DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
458  unsigned Cost = 0;
459  for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
460    unsigned Alias = *AI;
461    if (UsedInInstr.test(Alias))
462      return spillImpossible;
463    switch (unsigned VirtReg = PhysRegState[Alias]) {
464    case regDisabled:
465      break;
466    case regFree:
467      ++Cost;
468      break;
469    case regReserved:
470      return spillImpossible;
471    default: {
472      LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
473      assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
474      Cost += I->Dirty ? spillDirty : spillClean;
475      break;
476    }
477    }
478  }
479  return Cost;
480}
481
482
483/// assignVirtToPhysReg - This method updates local state so that we know
484/// that PhysReg is the proper container for VirtReg now.  The physical
485/// register must not be used for anything else when this is called.
486///
487void RAFast::assignVirtToPhysReg(LiveReg &LR, unsigned PhysReg) {
488  DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
489               << PrintReg(PhysReg, TRI) << "\n");
490  PhysRegState[PhysReg] = LR.VirtReg;
491  assert(!LR.PhysReg && "Already assigned a physreg");
492  LR.PhysReg = PhysReg;
493}
494
495RAFast::LiveRegMap::iterator
496RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
497  LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
498  assert(LRI != LiveVirtRegs.end() && "VirtReg disappeared");
499  assignVirtToPhysReg(*LRI, PhysReg);
500  return LRI;
501}
502
503/// allocVirtReg - Allocate a physical register for VirtReg.
504RAFast::LiveRegMap::iterator RAFast::allocVirtReg(MachineInstr *MI,
505                                                  LiveRegMap::iterator LRI,
506                                                  unsigned Hint) {
507  const unsigned VirtReg = LRI->VirtReg;
508
509  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
510         "Can only allocate virtual registers");
511
512  const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
513
514  // Ignore invalid hints.
515  if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
516               !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
517    Hint = 0;
518
519  // Take hint when possible.
520  if (Hint) {
521    // Ignore the hint if we would have to spill a dirty register.
522    unsigned Cost = calcSpillCost(Hint);
523    if (Cost < spillDirty) {
524      if (Cost)
525        definePhysReg(MI, Hint, regFree);
526      // definePhysReg may kill virtual registers and modify LiveVirtRegs.
527      // That invalidates LRI, so run a new lookup for VirtReg.
528      return assignVirtToPhysReg(VirtReg, Hint);
529    }
530  }
531
532  ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
533
534  // First try to find a completely free register.
535  for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
536    unsigned PhysReg = *I;
537    if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) {
538      assignVirtToPhysReg(*LRI, PhysReg);
539      return LRI;
540    }
541  }
542
543  DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
544               << RC->getName() << "\n");
545
546  unsigned BestReg = 0, BestCost = spillImpossible;
547  for (ArrayRef<unsigned>::iterator I = AO.begin(), E = AO.end(); I != E; ++I) {
548    unsigned Cost = calcSpillCost(*I);
549    DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n");
550    DEBUG(dbgs() << "\tCost: " << Cost << "\n");
551    DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
552    // Cost is 0 when all aliases are already disabled.
553    if (Cost == 0) {
554      assignVirtToPhysReg(*LRI, *I);
555      return LRI;
556    }
557    if (Cost < BestCost)
558      BestReg = *I, BestCost = Cost;
559  }
560
561  if (BestReg) {
562    definePhysReg(MI, BestReg, regFree);
563    // definePhysReg may kill virtual registers and modify LiveVirtRegs.
564    // That invalidates LRI, so run a new lookup for VirtReg.
565    return assignVirtToPhysReg(VirtReg, BestReg);
566  }
567
568  // Nothing we can do. Report an error and keep going with a bad allocation.
569  MI->emitError("ran out of registers during register allocation");
570  definePhysReg(MI, *AO.begin(), regFree);
571  return assignVirtToPhysReg(VirtReg, *AO.begin());
572}
573
574/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
575RAFast::LiveRegMap::iterator
576RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
577                      unsigned VirtReg, unsigned Hint) {
578  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
579         "Not a virtual register");
580  LiveRegMap::iterator LRI;
581  bool New;
582  tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
583  if (New) {
584    // If there is no hint, peek at the only use of this register.
585    if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
586        MRI->hasOneNonDBGUse(VirtReg)) {
587      const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
588      // It's a copy, use the destination register as a hint.
589      if (UseMI.isCopyLike())
590        Hint = UseMI.getOperand(0).getReg();
591    }
592    LRI = allocVirtReg(MI, LRI, Hint);
593  } else if (LRI->LastUse) {
594    // Redefining a live register - kill at the last use, unless it is this
595    // instruction defining VirtReg multiple times.
596    if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
597      addKillFlag(*LRI);
598  }
599  assert(LRI->PhysReg && "Register not assigned");
600  LRI->LastUse = MI;
601  LRI->LastOpNum = OpNum;
602  LRI->Dirty = true;
603  UsedInInstr.set(LRI->PhysReg);
604  return LRI;
605}
606
607/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
608RAFast::LiveRegMap::iterator
609RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
610                      unsigned VirtReg, unsigned Hint) {
611  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
612         "Not a virtual register");
613  LiveRegMap::iterator LRI;
614  bool New;
615  tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
616  MachineOperand &MO = MI->getOperand(OpNum);
617  if (New) {
618    LRI = allocVirtReg(MI, LRI, Hint);
619    const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
620    int FrameIndex = getStackSpaceFor(VirtReg, RC);
621    DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
622                 << PrintReg(LRI->PhysReg, TRI) << "\n");
623    TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
624    ++NumLoads;
625  } else if (LRI->Dirty) {
626    if (isLastUseOfLocalReg(MO)) {
627      DEBUG(dbgs() << "Killing last use: " << MO << "\n");
628      if (MO.isUse())
629        MO.setIsKill();
630      else
631        MO.setIsDead();
632    } else if (MO.isKill()) {
633      DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
634      MO.setIsKill(false);
635    } else if (MO.isDead()) {
636      DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
637      MO.setIsDead(false);
638    }
639  } else if (MO.isKill()) {
640    // We must remove kill flags from uses of reloaded registers because the
641    // register would be killed immediately, and there might be a second use:
642    //   %foo = OR %x<kill>, %x
643    // This would cause a second reload of %x into a different register.
644    DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
645    MO.setIsKill(false);
646  } else if (MO.isDead()) {
647    DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
648    MO.setIsDead(false);
649  }
650  assert(LRI->PhysReg && "Register not assigned");
651  LRI->LastUse = MI;
652  LRI->LastOpNum = OpNum;
653  UsedInInstr.set(LRI->PhysReg);
654  return LRI;
655}
656
657// setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
658// subregs. This may invalidate any operand pointers.
659// Return true if the operand kills its register.
660bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
661  MachineOperand &MO = MI->getOperand(OpNum);
662  bool Dead = MO.isDead();
663  if (!MO.getSubReg()) {
664    MO.setReg(PhysReg);
665    return MO.isKill() || Dead;
666  }
667
668  // Handle subregister index.
669  MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
670  MO.setSubReg(0);
671
672  // A kill flag implies killing the full register. Add corresponding super
673  // register kill.
674  if (MO.isKill()) {
675    MI->addRegisterKilled(PhysReg, TRI, true);
676    return true;
677  }
678
679  // A <def,read-undef> of a sub-register requires an implicit def of the full
680  // register.
681  if (MO.isDef() && MO.isUndef())
682    MI->addRegisterDefined(PhysReg, TRI);
683
684  return Dead;
685}
686
687// Handle special instruction operand like early clobbers and tied ops when
688// there are additional physreg defines.
689void RAFast::handleThroughOperands(MachineInstr *MI,
690                                   SmallVectorImpl<unsigned> &VirtDead) {
691  DEBUG(dbgs() << "Scanning for through registers:");
692  SmallSet<unsigned, 8> ThroughRegs;
693  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
694    MachineOperand &MO = MI->getOperand(i);
695    if (!MO.isReg()) continue;
696    unsigned Reg = MO.getReg();
697    if (!TargetRegisterInfo::isVirtualRegister(Reg))
698      continue;
699    if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
700        (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
701      if (ThroughRegs.insert(Reg))
702        DEBUG(dbgs() << ' ' << PrintReg(Reg));
703    }
704  }
705
706  // If any physreg defines collide with preallocated through registers,
707  // we must spill and reallocate.
708  DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
709  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
710    MachineOperand &MO = MI->getOperand(i);
711    if (!MO.isReg() || !MO.isDef()) continue;
712    unsigned Reg = MO.getReg();
713    if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
714    for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
715      UsedInInstr.set(*AI);
716      if (ThroughRegs.count(PhysRegState[*AI]))
717        definePhysReg(MI, *AI, regFree);
718    }
719  }
720
721  SmallVector<unsigned, 8> PartialDefs;
722  DEBUG(dbgs() << "Allocating tied uses.\n");
723  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
724    MachineOperand &MO = MI->getOperand(i);
725    if (!MO.isReg()) continue;
726    unsigned Reg = MO.getReg();
727    if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
728    if (MO.isUse()) {
729      unsigned DefIdx = 0;
730      if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
731      DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
732        << DefIdx << ".\n");
733      LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
734      unsigned PhysReg = LRI->PhysReg;
735      setPhysReg(MI, i, PhysReg);
736      // Note: we don't update the def operand yet. That would cause the normal
737      // def-scan to attempt spilling.
738    } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
739      DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
740      // Reload the register, but don't assign to the operand just yet.
741      // That would confuse the later phys-def processing pass.
742      LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
743      PartialDefs.push_back(LRI->PhysReg);
744    }
745  }
746
747  DEBUG(dbgs() << "Allocating early clobbers.\n");
748  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
749    MachineOperand &MO = MI->getOperand(i);
750    if (!MO.isReg()) continue;
751    unsigned Reg = MO.getReg();
752    if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
753    if (!MO.isEarlyClobber())
754      continue;
755    // Note: defineVirtReg may invalidate MO.
756    LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
757    unsigned PhysReg = LRI->PhysReg;
758    if (setPhysReg(MI, i, PhysReg))
759      VirtDead.push_back(Reg);
760  }
761
762  // Restore UsedInInstr to a state usable for allocating normal virtual uses.
763  UsedInInstr.reset();
764  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
765    MachineOperand &MO = MI->getOperand(i);
766    if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
767    unsigned Reg = MO.getReg();
768    if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
769    DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)
770                 << " as used in instr\n");
771    UsedInInstr.set(Reg);
772  }
773
774  // Also mark PartialDefs as used to avoid reallocation.
775  for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
776    UsedInInstr.set(PartialDefs[i]);
777}
778
779/// addRetOperand - ensure that a return instruction has an operand for each
780/// value live out of the function.
781///
782/// Things marked both call and return are tail calls; do not do this for them.
783/// The tail callee need not take the same registers as input that it produces
784/// as output, and there are dependencies for its input registers elsewhere.
785///
786/// FIXME: This should be done as part of instruction selection, and this helper
787/// should be deleted. Until then, we use custom logic here to create the proper
788/// operand under all circumstances. We can't use addRegisterKilled because that
789/// doesn't make sense for undefined values. We can't simply avoid calling it
790/// for undefined values, because we must ensure that the operand always exists.
791void RAFast::addRetOperands(MachineBasicBlock *MBB) {
792  if (MBB->empty() || !MBB->back().isReturn() || MBB->back().isCall())
793    return;
794
795  MachineInstr *MI = &MBB->back();
796
797  for (MachineRegisterInfo::liveout_iterator
798         I = MBB->getParent()->getRegInfo().liveout_begin(),
799         E = MBB->getParent()->getRegInfo().liveout_end(); I != E; ++I) {
800    unsigned Reg = *I;
801    assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
802           "Cannot have a live-out virtual register.");
803
804    bool hasDef = PhysRegState[Reg] == regReserved;
805
806    // Check if this register already has an operand.
807    bool Found = false;
808    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
809      MachineOperand &MO = MI->getOperand(i);
810      if (!MO.isReg() || !MO.isUse())
811        continue;
812
813      unsigned OperReg = MO.getReg();
814      if (!TargetRegisterInfo::isPhysicalRegister(OperReg))
815        continue;
816
817      if (OperReg == Reg || TRI->isSuperRegister(OperReg, Reg)) {
818        // If the ret already has an operand for this physreg or a superset,
819        // don't duplicate it. Set the kill flag if the value is defined.
820        if (hasDef && !MO.isKill())
821          MO.setIsKill();
822        Found = true;
823        break;
824      }
825    }
826    if (!Found)
827      MI->addOperand(MachineOperand::CreateReg(Reg,
828                                               false /*IsDef*/,
829                                               true  /*IsImp*/,
830                                               hasDef/*IsKill*/));
831  }
832}
833
834void RAFast::AllocateBasicBlock() {
835  DEBUG(dbgs() << "\nAllocating " << *MBB);
836
837  PhysRegState.assign(TRI->getNumRegs(), regDisabled);
838  assert(LiveVirtRegs.empty() && "Mapping not cleared from last block?");
839
840  MachineBasicBlock::iterator MII = MBB->begin();
841
842  // Add live-in registers as live.
843  for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
844         E = MBB->livein_end(); I != E; ++I)
845    if (RegClassInfo.isAllocatable(*I))
846      definePhysReg(MII, *I, regReserved);
847
848  SmallVector<unsigned, 8> VirtDead;
849  SmallVector<MachineInstr*, 32> Coalesced;
850
851  // Otherwise, sequentially allocate each instruction in the MBB.
852  while (MII != MBB->end()) {
853    MachineInstr *MI = MII++;
854    const MCInstrDesc &MCID = MI->getDesc();
855    DEBUG({
856        dbgs() << "\n>> " << *MI << "Regs:";
857        for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
858          if (PhysRegState[Reg] == regDisabled) continue;
859          dbgs() << " " << TRI->getName(Reg);
860          switch(PhysRegState[Reg]) {
861          case regFree:
862            break;
863          case regReserved:
864            dbgs() << "*";
865            break;
866          default: {
867            dbgs() << '=' << PrintReg(PhysRegState[Reg]);
868            LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
869            assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
870            if (I->Dirty)
871              dbgs() << "*";
872            assert(I->PhysReg == Reg && "Bad inverse map");
873            break;
874          }
875          }
876        }
877        dbgs() << '\n';
878        // Check that LiveVirtRegs is the inverse.
879        for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
880             e = LiveVirtRegs.end(); i != e; ++i) {
881           assert(TargetRegisterInfo::isVirtualRegister(i->VirtReg) &&
882                  "Bad map key");
883           assert(TargetRegisterInfo::isPhysicalRegister(i->PhysReg) &&
884                  "Bad map value");
885           assert(PhysRegState[i->PhysReg] == i->VirtReg && "Bad inverse map");
886        }
887      });
888
889    // Debug values are not allowed to change codegen in any way.
890    if (MI->isDebugValue()) {
891      bool ScanDbgValue = true;
892      while (ScanDbgValue) {
893        ScanDbgValue = false;
894        for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
895          MachineOperand &MO = MI->getOperand(i);
896          if (!MO.isReg()) continue;
897          unsigned Reg = MO.getReg();
898          if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
899          LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
900          if (LRI != LiveVirtRegs.end())
901            setPhysReg(MI, i, LRI->PhysReg);
902          else {
903            int SS = StackSlotForVirtReg[Reg];
904            if (SS == -1) {
905              // We can't allocate a physreg for a DebugValue, sorry!
906              DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
907              MO.setReg(0);
908            }
909            else {
910              // Modify DBG_VALUE now that the value is in a spill slot.
911              int64_t Offset = MI->getOperand(1).getImm();
912              const MDNode *MDPtr =
913                MI->getOperand(MI->getNumOperands()-1).getMetadata();
914              DebugLoc DL = MI->getDebugLoc();
915              if (MachineInstr *NewDV =
916                  TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
917                DEBUG(dbgs() << "Modifying debug info due to spill:" <<
918                      "\t" << *MI);
919                MachineBasicBlock *MBB = MI->getParent();
920                MBB->insert(MBB->erase(MI), NewDV);
921                // Scan NewDV operands from the beginning.
922                MI = NewDV;
923                ScanDbgValue = true;
924                break;
925              } else {
926                // We can't allocate a physreg for a DebugValue; sorry!
927                DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE");
928                MO.setReg(0);
929              }
930            }
931          }
932          LiveDbgValueMap[Reg].push_back(MI);
933        }
934      }
935      // Next instruction.
936      continue;
937    }
938
939    // If this is a copy, we may be able to coalesce.
940    unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
941    if (MI->isCopy()) {
942      CopyDst = MI->getOperand(0).getReg();
943      CopySrc = MI->getOperand(1).getReg();
944      CopyDstSub = MI->getOperand(0).getSubReg();
945      CopySrcSub = MI->getOperand(1).getSubReg();
946    }
947
948    // Track registers used by instruction.
949    UsedInInstr.reset();
950
951    // First scan.
952    // Mark physreg uses and early clobbers as used.
953    // Find the end of the virtreg operands
954    unsigned VirtOpEnd = 0;
955    bool hasTiedOps = false;
956    bool hasEarlyClobbers = false;
957    bool hasPartialRedefs = false;
958    bool hasPhysDefs = false;
959    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
960      MachineOperand &MO = MI->getOperand(i);
961      if (!MO.isReg()) continue;
962      unsigned Reg = MO.getReg();
963      if (!Reg) continue;
964      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
965        VirtOpEnd = i+1;
966        if (MO.isUse()) {
967          hasTiedOps = hasTiedOps ||
968                              MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1;
969        } else {
970          if (MO.isEarlyClobber())
971            hasEarlyClobbers = true;
972          if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
973            hasPartialRedefs = true;
974        }
975        continue;
976      }
977      if (!RegClassInfo.isAllocatable(Reg)) continue;
978      if (MO.isUse()) {
979        usePhysReg(MO);
980      } else if (MO.isEarlyClobber()) {
981        definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
982                               regFree : regReserved);
983        hasEarlyClobbers = true;
984      } else
985        hasPhysDefs = true;
986    }
987
988    // The instruction may have virtual register operands that must be allocated
989    // the same register at use-time and def-time: early clobbers and tied
990    // operands. If there are also physical defs, these registers must avoid
991    // both physical defs and uses, making them more constrained than normal
992    // operands.
993    // Similarly, if there are multiple defs and tied operands, we must make
994    // sure the same register is allocated to uses and defs.
995    // We didn't detect inline asm tied operands above, so just make this extra
996    // pass for all inline asm.
997    if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
998        (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) {
999      handleThroughOperands(MI, VirtDead);
1000      // Don't attempt coalescing when we have funny stuff going on.
1001      CopyDst = 0;
1002      // Pretend we have early clobbers so the use operands get marked below.
1003      // This is not necessary for the common case of a single tied use.
1004      hasEarlyClobbers = true;
1005    }
1006
1007    // Second scan.
1008    // Allocate virtreg uses.
1009    for (unsigned i = 0; i != VirtOpEnd; ++i) {
1010      MachineOperand &MO = MI->getOperand(i);
1011      if (!MO.isReg()) continue;
1012      unsigned Reg = MO.getReg();
1013      if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
1014      if (MO.isUse()) {
1015        LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
1016        unsigned PhysReg = LRI->PhysReg;
1017        CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
1018        if (setPhysReg(MI, i, PhysReg))
1019          killVirtReg(LRI);
1020      }
1021    }
1022
1023    MRI->addPhysRegsUsed(UsedInInstr);
1024
1025    // Track registers defined by instruction - early clobbers and tied uses at
1026    // this point.
1027    UsedInInstr.reset();
1028    if (hasEarlyClobbers) {
1029      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1030        MachineOperand &MO = MI->getOperand(i);
1031        if (!MO.isReg()) continue;
1032        unsigned Reg = MO.getReg();
1033        if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1034        // Look for physreg defs and tied uses.
1035        if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue;
1036        for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
1037          UsedInInstr.set(*AI);
1038      }
1039    }
1040
1041    unsigned DefOpEnd = MI->getNumOperands();
1042    if (MI->isCall()) {
1043      // Spill all virtregs before a call. This serves two purposes: 1. If an
1044      // exception is thrown, the landing pad is going to expect to find
1045      // registers in their spill slots, and 2. we don't have to wade through
1046      // all the <imp-def> operands on the call instruction.
1047      DefOpEnd = VirtOpEnd;
1048      DEBUG(dbgs() << "  Spilling remaining registers before call.\n");
1049      spillAll(MI);
1050
1051      // The imp-defs are skipped below, but we still need to mark those
1052      // registers as used by the function.
1053      SkippedInstrs.insert(&MCID);
1054    }
1055
1056    // Third scan.
1057    // Allocate defs and collect dead defs.
1058    for (unsigned i = 0; i != DefOpEnd; ++i) {
1059      MachineOperand &MO = MI->getOperand(i);
1060      if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1061        continue;
1062      unsigned Reg = MO.getReg();
1063
1064      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1065        if (!RegClassInfo.isAllocatable(Reg)) continue;
1066        definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
1067                               regFree : regReserved);
1068        continue;
1069      }
1070      LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
1071      unsigned PhysReg = LRI->PhysReg;
1072      if (setPhysReg(MI, i, PhysReg)) {
1073        VirtDead.push_back(Reg);
1074        CopyDst = 0; // cancel coalescing;
1075      } else
1076        CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
1077    }
1078
1079    // Kill dead defs after the scan to ensure that multiple defs of the same
1080    // register are allocated identically. We didn't need to do this for uses
1081    // because we are crerating our own kill flags, and they are always at the
1082    // last use.
1083    for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
1084      killVirtReg(VirtDead[i]);
1085    VirtDead.clear();
1086
1087    MRI->addPhysRegsUsed(UsedInInstr);
1088
1089    if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
1090      DEBUG(dbgs() << "-- coalescing: " << *MI);
1091      Coalesced.push_back(MI);
1092    } else {
1093      DEBUG(dbgs() << "<< " << *MI);
1094    }
1095  }
1096
1097  // Spill all physical registers holding virtual registers now.
1098  DEBUG(dbgs() << "Spilling live registers at end of block.\n");
1099  spillAll(MBB->getFirstTerminator());
1100
1101  // Erase all the coalesced copies. We are delaying it until now because
1102  // LiveVirtRegs might refer to the instrs.
1103  for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
1104    MBB->erase(Coalesced[i]);
1105  NumCopies += Coalesced.size();
1106
1107  // addRetOperands must run after we've seen all defs in this block.
1108  addRetOperands(MBB);
1109
1110  DEBUG(MBB->dump());
1111}
1112
1113/// runOnMachineFunction - Register allocate the whole function
1114///
1115bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
1116  DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
1117               << "********** Function: "
1118               << ((Value*)Fn.getFunction())->getName() << '\n');
1119  MF = &Fn;
1120  MRI = &MF->getRegInfo();
1121  TM = &Fn.getTarget();
1122  TRI = TM->getRegisterInfo();
1123  TII = TM->getInstrInfo();
1124  MRI->freezeReservedRegs(Fn);
1125  RegClassInfo.runOnMachineFunction(Fn);
1126  UsedInInstr.resize(TRI->getNumRegs());
1127
1128  assert(!MRI->isSSA() && "regalloc requires leaving SSA");
1129
1130  // initialize the virtual->physical register map to have a 'null'
1131  // mapping for all virtual registers
1132  StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
1133  LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
1134
1135  // Loop over all of the basic blocks, eliminating virtual register references
1136  for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
1137       MBBi != MBBe; ++MBBi) {
1138    MBB = &*MBBi;
1139    AllocateBasicBlock();
1140  }
1141
1142  // Add the clobber lists for all the instructions we skipped earlier.
1143  for (SmallPtrSet<const MCInstrDesc*, 4>::const_iterator
1144       I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
1145    if (const uint16_t *Defs = (*I)->getImplicitDefs())
1146      while (*Defs)
1147        MRI->setPhysRegUsed(*Defs++);
1148
1149  // All machine operands and other references to virtual registers have been
1150  // replaced. Remove the virtual registers.
1151  MRI->clearVirtRegs();
1152
1153  SkippedInstrs.clear();
1154  StackSlotForVirtReg.clear();
1155  LiveDbgValueMap.clear();
1156  return true;
1157}
1158
1159FunctionPass *llvm::createFastRegisterAllocator() {
1160  return new RAFast();
1161}
1162