RegAllocFast.cpp revision d574bb5a6ee6cbe4d2387e4fa7f7f5ab099ea05f
1//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This register allocator allocates registers to a basic block at a time, 11// attempting to keep values in registers and reusing registers as appropriate. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "llvm/BasicBlock.h" 17#include "llvm/CodeGen/MachineFunctionPass.h" 18#include "llvm/CodeGen/MachineInstr.h" 19#include "llvm/CodeGen/MachineInstrBuilder.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineRegisterInfo.h" 22#include "llvm/CodeGen/Passes.h" 23#include "llvm/CodeGen/RegAllocRegistry.h" 24#include "llvm/Target/TargetInstrInfo.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Support/CommandLine.h" 27#include "llvm/Support/Debug.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/raw_ostream.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/IndexedMap.h" 32#include "llvm/ADT/SmallSet.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/ADT/STLExtras.h" 36#include <algorithm> 37using namespace llvm; 38 39STATISTIC(NumStores, "Number of stores added"); 40STATISTIC(NumLoads , "Number of loads added"); 41STATISTIC(NumCopies, "Number of copies coalesced"); 42 43static RegisterRegAlloc 44 fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator); 45 46namespace { 47 class RAFast : public MachineFunctionPass { 48 public: 49 static char ID; 50 RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1), 51 isBulkSpilling(false) { 52 initializePHIEliminationPass(*PassRegistry::getPassRegistry()); 53 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); 54 } 55 private: 56 const TargetMachine *TM; 57 MachineFunction *MF; 58 MachineRegisterInfo *MRI; 59 const TargetRegisterInfo *TRI; 60 const TargetInstrInfo *TII; 61 62 // Basic block currently being allocated. 63 MachineBasicBlock *MBB; 64 65 // StackSlotForVirtReg - Maps virtual regs to the frame index where these 66 // values are spilled. 67 IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg; 68 69 // Everything we know about a live virtual register. 70 struct LiveReg { 71 MachineInstr *LastUse; // Last instr to use reg. 72 unsigned PhysReg; // Currently held here. 73 unsigned short LastOpNum; // OpNum on LastUse. 74 bool Dirty; // Register needs spill. 75 76 LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0), 77 Dirty(false) {} 78 }; 79 80 typedef DenseMap<unsigned, LiveReg> LiveRegMap; 81 typedef LiveRegMap::value_type LiveRegEntry; 82 83 // LiveVirtRegs - This map contains entries for each virtual register 84 // that is currently available in a physical register. 85 LiveRegMap LiveVirtRegs; 86 87 DenseMap<unsigned, MachineInstr *> LiveDbgValueMap; 88 89 // RegState - Track the state of a physical register. 90 enum RegState { 91 // A disabled register is not available for allocation, but an alias may 92 // be in use. A register can only be moved out of the disabled state if 93 // all aliases are disabled. 94 regDisabled, 95 96 // A free register is not currently in use and can be allocated 97 // immediately without checking aliases. 98 regFree, 99 100 // A reserved register has been assigned expolicitly (e.g., setting up a 101 // call parameter), and it remains reserved until it is used. 102 regReserved 103 104 // A register state may also be a virtual register number, indication that 105 // the physical register is currently allocated to a virtual register. In 106 // that case, LiveVirtRegs contains the inverse mapping. 107 }; 108 109 // PhysRegState - One of the RegState enums, or a virtreg. 110 std::vector<unsigned> PhysRegState; 111 112 // UsedInInstr - BitVector of physregs that are used in the current 113 // instruction, and so cannot be allocated. 114 BitVector UsedInInstr; 115 116 // Allocatable - vector of allocatable physical registers. 117 BitVector Allocatable; 118 119 // SkippedInstrs - Descriptors of instructions whose clobber list was 120 // ignored because all registers were spilled. It is still necessary to 121 // mark all the clobbered registers as used by the function. 122 SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs; 123 124 // isBulkSpilling - This flag is set when LiveRegMap will be cleared 125 // completely after spilling all live registers. LiveRegMap entries should 126 // not be erased. 127 bool isBulkSpilling; 128 129 enum { 130 spillClean = 1, 131 spillDirty = 100, 132 spillImpossible = ~0u 133 }; 134 public: 135 virtual const char *getPassName() const { 136 return "Fast Register Allocator"; 137 } 138 139 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 140 AU.setPreservesCFG(); 141 AU.addRequiredID(PHIEliminationID); 142 AU.addRequiredID(TwoAddressInstructionPassID); 143 MachineFunctionPass::getAnalysisUsage(AU); 144 } 145 146 private: 147 bool runOnMachineFunction(MachineFunction &Fn); 148 void AllocateBasicBlock(); 149 void handleThroughOperands(MachineInstr *MI, 150 SmallVectorImpl<unsigned> &VirtDead); 151 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); 152 bool isLastUseOfLocalReg(MachineOperand&); 153 154 void addKillFlag(const LiveReg&); 155 void killVirtReg(LiveRegMap::iterator); 156 void killVirtReg(unsigned VirtReg); 157 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator); 158 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 159 160 void usePhysReg(MachineOperand&); 161 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 162 unsigned calcSpillCost(unsigned PhysReg) const; 163 void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg); 164 void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint); 165 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum, 166 unsigned VirtReg, unsigned Hint); 167 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum, 168 unsigned VirtReg, unsigned Hint); 169 void spillAll(MachineInstr *MI); 170 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg); 171 }; 172 char RAFast::ID = 0; 173} 174 175/// getStackSpaceFor - This allocates space for the specified virtual register 176/// to be held on the stack. 177int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { 178 // Find the location Reg would belong... 179 int SS = StackSlotForVirtReg[VirtReg]; 180 if (SS != -1) 181 return SS; // Already has space allocated? 182 183 // Allocate a new stack object for this spill location... 184 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 185 RC->getAlignment()); 186 187 // Assign the slot. 188 StackSlotForVirtReg[VirtReg] = FrameIdx; 189 return FrameIdx; 190} 191 192/// isLastUseOfLocalReg - Return true if MO is the only remaining reference to 193/// its virtual register, and it is guaranteed to be a block-local register. 194/// 195bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) { 196 // Check for non-debug uses or defs following MO. 197 // This is the most likely way to fail - fast path it. 198 MachineOperand *Next = &MO; 199 while ((Next = Next->getNextOperandForReg())) 200 if (!Next->isDebug()) 201 return false; 202 203 // If the register has ever been spilled or reloaded, we conservatively assume 204 // it is a global register used in multiple blocks. 205 if (StackSlotForVirtReg[MO.getReg()] != -1) 206 return false; 207 208 // Check that the use/def chain has exactly one operand - MO. 209 return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO; 210} 211 212/// addKillFlag - Set kill flags on last use of a virtual register. 213void RAFast::addKillFlag(const LiveReg &LR) { 214 if (!LR.LastUse) return; 215 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); 216 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { 217 if (MO.getReg() == LR.PhysReg) 218 MO.setIsKill(); 219 else 220 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); 221 } 222} 223 224/// killVirtReg - Mark virtreg as no longer available. 225void RAFast::killVirtReg(LiveRegMap::iterator LRI) { 226 addKillFlag(LRI->second); 227 const LiveReg &LR = LRI->second; 228 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping"); 229 PhysRegState[LR.PhysReg] = regFree; 230 // Erase from LiveVirtRegs unless we're spilling in bulk. 231 if (!isBulkSpilling) 232 LiveVirtRegs.erase(LRI); 233} 234 235/// killVirtReg - Mark virtreg as no longer available. 236void RAFast::killVirtReg(unsigned VirtReg) { 237 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 238 "killVirtReg needs a virtual register"); 239 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg); 240 if (LRI != LiveVirtRegs.end()) 241 killVirtReg(LRI); 242} 243 244/// spillVirtReg - This method spills the value specified by VirtReg into the 245/// corresponding stack slot if needed. 246void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { 247 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 248 "Spilling a physical register is illegal!"); 249 LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg); 250 assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register"); 251 spillVirtReg(MI, LRI); 252} 253 254/// spillVirtReg - Do the actual work of spilling. 255void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, 256 LiveRegMap::iterator LRI) { 257 LiveReg &LR = LRI->second; 258 assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping"); 259 260 if (LR.Dirty) { 261 // If this physreg is used by the instruction, we want to kill it on the 262 // instruction, not on the spill. 263 bool SpillKill = LR.LastUse != MI; 264 LR.Dirty = false; 265 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI) 266 << " in " << PrintReg(LR.PhysReg, TRI)); 267 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first); 268 int FI = getStackSpaceFor(LRI->first, RC); 269 DEBUG(dbgs() << " to stack slot #" << FI << "\n"); 270 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); 271 ++NumStores; // Update statistics 272 273 // If this register is used by DBG_VALUE then insert new DBG_VALUE to 274 // identify spilled location as the place to find corresponding variable's 275 // value. 276 if (MachineInstr *DBG = LiveDbgValueMap.lookup(LRI->first)) { 277 const MDNode *MDPtr = 278 DBG->getOperand(DBG->getNumOperands()-1).getMetadata(); 279 int64_t Offset = 0; 280 if (DBG->getOperand(1).isImm()) 281 Offset = DBG->getOperand(1).getImm(); 282 DebugLoc DL; 283 if (MI == MBB->end()) { 284 // If MI is at basic block end then use last instruction's location. 285 MachineBasicBlock::iterator EI = MI; 286 DL = (--EI)->getDebugLoc(); 287 } 288 else 289 DL = MI->getDebugLoc(); 290 if (MachineInstr *NewDV = 291 TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) { 292 MachineBasicBlock *MBB = DBG->getParent(); 293 MBB->insert(MI, NewDV); 294 DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV); 295 LiveDbgValueMap[LRI->first] = NewDV; 296 } 297 } 298 if (SpillKill) 299 LR.LastUse = 0; // Don't kill register again 300 } 301 killVirtReg(LRI); 302} 303 304/// spillAll - Spill all dirty virtregs without killing them. 305void RAFast::spillAll(MachineInstr *MI) { 306 if (LiveVirtRegs.empty()) return; 307 isBulkSpilling = true; 308 // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order 309 // of spilling here is deterministic, if arbitrary. 310 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end(); 311 i != e; ++i) 312 spillVirtReg(MI, i); 313 LiveVirtRegs.clear(); 314 isBulkSpilling = false; 315} 316 317/// usePhysReg - Handle the direct use of a physical register. 318/// Check that the register is not used by a virtreg. 319/// Kill the physreg, marking it free. 320/// This may add implicit kills to MO->getParent() and invalidate MO. 321void RAFast::usePhysReg(MachineOperand &MO) { 322 unsigned PhysReg = MO.getReg(); 323 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && 324 "Bad usePhysReg operand"); 325 326 switch (PhysRegState[PhysReg]) { 327 case regDisabled: 328 break; 329 case regReserved: 330 PhysRegState[PhysReg] = regFree; 331 // Fall through 332 case regFree: 333 UsedInInstr.set(PhysReg); 334 MO.setIsKill(); 335 return; 336 default: 337 // The physreg was allocated to a virtual register. That means the value we 338 // wanted has been clobbered. 339 llvm_unreachable("Instruction uses an allocated register"); 340 } 341 342 // Maybe a superregister is reserved? 343 for (const unsigned *AS = TRI->getAliasSet(PhysReg); 344 unsigned Alias = *AS; ++AS) { 345 switch (PhysRegState[Alias]) { 346 case regDisabled: 347 break; 348 case regReserved: 349 assert(TRI->isSuperRegister(PhysReg, Alias) && 350 "Instruction is not using a subregister of a reserved register"); 351 // Leave the superregister in the working set. 352 PhysRegState[Alias] = regFree; 353 UsedInInstr.set(Alias); 354 MO.getParent()->addRegisterKilled(Alias, TRI, true); 355 return; 356 case regFree: 357 if (TRI->isSuperRegister(PhysReg, Alias)) { 358 // Leave the superregister in the working set. 359 UsedInInstr.set(Alias); 360 MO.getParent()->addRegisterKilled(Alias, TRI, true); 361 return; 362 } 363 // Some other alias was in the working set - clear it. 364 PhysRegState[Alias] = regDisabled; 365 break; 366 default: 367 llvm_unreachable("Instruction uses an alias of an allocated register"); 368 } 369 } 370 371 // All aliases are disabled, bring register into working set. 372 PhysRegState[PhysReg] = regFree; 373 UsedInInstr.set(PhysReg); 374 MO.setIsKill(); 375} 376 377/// definePhysReg - Mark PhysReg as reserved or free after spilling any 378/// virtregs. This is very similar to defineVirtReg except the physreg is 379/// reserved instead of allocated. 380void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg, 381 RegState NewState) { 382 UsedInInstr.set(PhysReg); 383 switch (unsigned VirtReg = PhysRegState[PhysReg]) { 384 case regDisabled: 385 break; 386 default: 387 spillVirtReg(MI, VirtReg); 388 // Fall through. 389 case regFree: 390 case regReserved: 391 PhysRegState[PhysReg] = NewState; 392 return; 393 } 394 395 // This is a disabled register, disable all aliases. 396 PhysRegState[PhysReg] = NewState; 397 for (const unsigned *AS = TRI->getAliasSet(PhysReg); 398 unsigned Alias = *AS; ++AS) { 399 switch (unsigned VirtReg = PhysRegState[Alias]) { 400 case regDisabled: 401 break; 402 default: 403 spillVirtReg(MI, VirtReg); 404 // Fall through. 405 case regFree: 406 case regReserved: 407 PhysRegState[Alias] = regDisabled; 408 if (TRI->isSuperRegister(PhysReg, Alias)) 409 return; 410 break; 411 } 412 } 413} 414 415 416// calcSpillCost - Return the cost of spilling clearing out PhysReg and 417// aliases so it is free for allocation. 418// Returns 0 when PhysReg is free or disabled with all aliases disabled - it 419// can be allocated directly. 420// Returns spillImpossible when PhysReg or an alias can't be spilled. 421unsigned RAFast::calcSpillCost(unsigned PhysReg) const { 422 if (UsedInInstr.test(PhysReg)) { 423 DEBUG(dbgs() << "PhysReg: " << PhysReg << " is already used in instr.\n"); 424 return spillImpossible; 425 } 426 switch (unsigned VirtReg = PhysRegState[PhysReg]) { 427 case regDisabled: 428 break; 429 case regFree: 430 return 0; 431 case regReserved: 432 DEBUG(dbgs() << "VirtReg: " << VirtReg << " corresponding to PhysReg: " 433 << PhysReg << " is reserved already.\n"); 434 return spillImpossible; 435 default: 436 return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean; 437 } 438 439 // This is a disabled register, add up cost of aliases. 440 DEBUG(dbgs() << "\tRegister: " << PhysReg << " is disabled.\n"); 441 unsigned Cost = 0; 442 for (const unsigned *AS = TRI->getAliasSet(PhysReg); 443 unsigned Alias = *AS; ++AS) { 444 if (UsedInInstr.test(Alias)) 445 return spillImpossible; 446 switch (unsigned VirtReg = PhysRegState[Alias]) { 447 case regDisabled: 448 break; 449 case regFree: 450 ++Cost; 451 break; 452 case regReserved: 453 return spillImpossible; 454 default: 455 Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean; 456 break; 457 } 458 } 459 return Cost; 460} 461 462 463/// assignVirtToPhysReg - This method updates local state so that we know 464/// that PhysReg is the proper container for VirtReg now. The physical 465/// register must not be used for anything else when this is called. 466/// 467void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) { 468 DEBUG(dbgs() << "Assigning " << PrintReg(LRE.first, TRI) << " to " 469 << PrintReg(PhysReg, TRI) << "\n"); 470 PhysRegState[PhysReg] = LRE.first; 471 assert(!LRE.second.PhysReg && "Already assigned a physreg"); 472 LRE.second.PhysReg = PhysReg; 473} 474 475/// allocVirtReg - Allocate a physical register for VirtReg. 476void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) { 477 const unsigned VirtReg = LRE.first; 478 479 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 480 "Can only allocate virtual registers"); 481 482 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 483 484 // Ignore invalid hints. 485 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || 486 !RC->contains(Hint) || !Allocatable.test(Hint))) 487 Hint = 0; 488 489 // Take hint when possible. 490 if (Hint) { 491 switch(calcSpillCost(Hint)) { 492 default: 493 definePhysReg(MI, Hint, regFree); 494 // Fall through. 495 case 0: 496 return assignVirtToPhysReg(LRE, Hint); 497 case spillImpossible: 498 break; 499 } 500 } 501 502 TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF); 503 TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF); 504 505 // First try to find a completely free register. 506 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { 507 unsigned PhysReg = *I; 508 if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) && 509 Allocatable.test(PhysReg)) 510 return assignVirtToPhysReg(LRE, PhysReg); 511 } 512 513 DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from " 514 << RC->getName() << "\n"); 515 516 unsigned BestReg = 0, BestCost = spillImpossible; 517 for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { 518 if (!Allocatable.test(*I)) { 519 DEBUG(dbgs() << "\tRegister " << *I << " is not allocatable.\n"); 520 continue; 521 } 522 unsigned Cost = calcSpillCost(*I); 523 DEBUG(dbgs() << "\tRegister: " << *I << "\n"); 524 DEBUG(dbgs() << "\tCost: " << Cost << "\n"); 525 DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); 526 // Cost is 0 when all aliases are already disabled. 527 if (Cost == 0) 528 return assignVirtToPhysReg(LRE, *I); 529 if (Cost < BestCost) 530 BestReg = *I, BestCost = Cost; 531 } 532 533 if (BestReg) { 534 definePhysReg(MI, BestReg, regFree); 535 return assignVirtToPhysReg(LRE, BestReg); 536 } 537 538 // Nothing we can do. 539 std::string msg; 540 raw_string_ostream Msg(msg); 541 Msg << "Ran out of registers during register allocation!"; 542 if (MI->isInlineAsm()) { 543 Msg << "\nPlease check your inline asm statement for " 544 << "invalid constraints:\n"; 545 MI->print(Msg, TM); 546 } 547 report_fatal_error(Msg.str()); 548} 549 550/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty. 551RAFast::LiveRegMap::iterator 552RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, 553 unsigned VirtReg, unsigned Hint) { 554 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 555 "Not a virtual register"); 556 LiveRegMap::iterator LRI; 557 bool New; 558 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg())); 559 LiveReg &LR = LRI->second; 560 if (New) { 561 // If there is no hint, peek at the only use of this register. 562 if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) && 563 MRI->hasOneNonDBGUse(VirtReg)) { 564 const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg); 565 // It's a copy, use the destination register as a hint. 566 if (UseMI.isCopyLike()) 567 Hint = UseMI.getOperand(0).getReg(); 568 } 569 allocVirtReg(MI, *LRI, Hint); 570 } else if (LR.LastUse) { 571 // Redefining a live register - kill at the last use, unless it is this 572 // instruction defining VirtReg multiple times. 573 if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse()) 574 addKillFlag(LR); 575 } 576 assert(LR.PhysReg && "Register not assigned"); 577 LR.LastUse = MI; 578 LR.LastOpNum = OpNum; 579 LR.Dirty = true; 580 UsedInInstr.set(LR.PhysReg); 581 return LRI; 582} 583 584/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it. 585RAFast::LiveRegMap::iterator 586RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, 587 unsigned VirtReg, unsigned Hint) { 588 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && 589 "Not a virtual register"); 590 LiveRegMap::iterator LRI; 591 bool New; 592 tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg())); 593 LiveReg &LR = LRI->second; 594 MachineOperand &MO = MI->getOperand(OpNum); 595 if (New) { 596 allocVirtReg(MI, *LRI, Hint); 597 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); 598 int FrameIndex = getStackSpaceFor(VirtReg, RC); 599 DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into " 600 << PrintReg(LR.PhysReg, TRI) << "\n"); 601 TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI); 602 ++NumLoads; 603 } else if (LR.Dirty) { 604 if (isLastUseOfLocalReg(MO)) { 605 DEBUG(dbgs() << "Killing last use: " << MO << "\n"); 606 if (MO.isUse()) 607 MO.setIsKill(); 608 else 609 MO.setIsDead(); 610 } else if (MO.isKill()) { 611 DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n"); 612 MO.setIsKill(false); 613 } else if (MO.isDead()) { 614 DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n"); 615 MO.setIsDead(false); 616 } 617 } else if (MO.isKill()) { 618 // We must remove kill flags from uses of reloaded registers because the 619 // register would be killed immediately, and there might be a second use: 620 // %foo = OR %x<kill>, %x 621 // This would cause a second reload of %x into a different register. 622 DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n"); 623 MO.setIsKill(false); 624 } else if (MO.isDead()) { 625 DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n"); 626 MO.setIsDead(false); 627 } 628 assert(LR.PhysReg && "Register not assigned"); 629 LR.LastUse = MI; 630 LR.LastOpNum = OpNum; 631 UsedInInstr.set(LR.PhysReg); 632 return LRI; 633} 634 635// setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering 636// subregs. This may invalidate any operand pointers. 637// Return true if the operand kills its register. 638bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) { 639 MachineOperand &MO = MI->getOperand(OpNum); 640 if (!MO.getSubReg()) { 641 MO.setReg(PhysReg); 642 return MO.isKill() || MO.isDead(); 643 } 644 645 // Handle subregister index. 646 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); 647 MO.setSubReg(0); 648 649 // A kill flag implies killing the full register. Add corresponding super 650 // register kill. 651 if (MO.isKill()) { 652 MI->addRegisterKilled(PhysReg, TRI, true); 653 return true; 654 } 655 return MO.isDead(); 656} 657 658// Handle special instruction operand like early clobbers and tied ops when 659// there are additional physreg defines. 660void RAFast::handleThroughOperands(MachineInstr *MI, 661 SmallVectorImpl<unsigned> &VirtDead) { 662 DEBUG(dbgs() << "Scanning for through registers:"); 663 SmallSet<unsigned, 8> ThroughRegs; 664 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 665 MachineOperand &MO = MI->getOperand(i); 666 if (!MO.isReg()) continue; 667 unsigned Reg = MO.getReg(); 668 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 669 continue; 670 if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) || 671 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { 672 if (ThroughRegs.insert(Reg)) 673 DEBUG(dbgs() << ' ' << PrintReg(Reg)); 674 } 675 } 676 677 // If any physreg defines collide with preallocated through registers, 678 // we must spill and reallocate. 679 DEBUG(dbgs() << "\nChecking for physdef collisions.\n"); 680 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 681 MachineOperand &MO = MI->getOperand(i); 682 if (!MO.isReg() || !MO.isDef()) continue; 683 unsigned Reg = MO.getReg(); 684 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 685 UsedInInstr.set(Reg); 686 if (ThroughRegs.count(PhysRegState[Reg])) 687 definePhysReg(MI, Reg, regFree); 688 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { 689 UsedInInstr.set(*AS); 690 if (ThroughRegs.count(PhysRegState[*AS])) 691 definePhysReg(MI, *AS, regFree); 692 } 693 } 694 695 SmallVector<unsigned, 8> PartialDefs; 696 DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n"); 697 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 698 MachineOperand &MO = MI->getOperand(i); 699 if (!MO.isReg()) continue; 700 unsigned Reg = MO.getReg(); 701 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 702 if (MO.isUse()) { 703 unsigned DefIdx = 0; 704 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; 705 DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand " 706 << DefIdx << ".\n"); 707 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0); 708 unsigned PhysReg = LRI->second.PhysReg; 709 setPhysReg(MI, i, PhysReg); 710 // Note: we don't update the def operand yet. That would cause the normal 711 // def-scan to attempt spilling. 712 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { 713 DEBUG(dbgs() << "Partial redefine: " << MO << "\n"); 714 // Reload the register, but don't assign to the operand just yet. 715 // That would confuse the later phys-def processing pass. 716 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0); 717 PartialDefs.push_back(LRI->second.PhysReg); 718 } else if (MO.isEarlyClobber()) { 719 // Note: defineVirtReg may invalidate MO. 720 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0); 721 unsigned PhysReg = LRI->second.PhysReg; 722 if (setPhysReg(MI, i, PhysReg)) 723 VirtDead.push_back(Reg); 724 } 725 } 726 727 // Restore UsedInInstr to a state usable for allocating normal virtual uses. 728 UsedInInstr.reset(); 729 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 730 MachineOperand &MO = MI->getOperand(i); 731 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; 732 unsigned Reg = MO.getReg(); 733 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 734 DEBUG(dbgs() << "\tSetting reg " << Reg << " as used in instr\n"); 735 UsedInInstr.set(Reg); 736 } 737 738 // Also mark PartialDefs as used to avoid reallocation. 739 for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i) 740 UsedInInstr.set(PartialDefs[i]); 741} 742 743void RAFast::AllocateBasicBlock() { 744 DEBUG(dbgs() << "\nAllocating " << *MBB); 745 746 // FIXME: This should probably be added by instruction selection instead? 747 // If the last instruction in the block is a return, make sure to mark it as 748 // using all of the live-out values in the function. Things marked both call 749 // and return are tail calls; do not do this for them. The tail callee need 750 // not take the same registers as input that it produces as output, and there 751 // are dependencies for its input registers elsewhere. 752 if (!MBB->empty() && MBB->back().getDesc().isReturn() && 753 !MBB->back().getDesc().isCall()) { 754 MachineInstr *Ret = &MBB->back(); 755 756 for (MachineRegisterInfo::liveout_iterator 757 I = MF->getRegInfo().liveout_begin(), 758 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 759 assert(TargetRegisterInfo::isPhysicalRegister(*I) && 760 "Cannot have a live-out virtual register."); 761 762 // Add live-out registers as implicit uses. 763 Ret->addRegisterKilled(*I, TRI, true); 764 } 765 } 766 767 PhysRegState.assign(TRI->getNumRegs(), regDisabled); 768 assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?"); 769 770 MachineBasicBlock::iterator MII = MBB->begin(); 771 772 // Add live-in registers as live. 773 for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), 774 E = MBB->livein_end(); I != E; ++I) 775 if (Allocatable.test(*I)) 776 definePhysReg(MII, *I, regReserved); 777 778 SmallVector<unsigned, 8> VirtDead; 779 SmallVector<MachineInstr*, 32> Coalesced; 780 781 // Otherwise, sequentially allocate each instruction in the MBB. 782 while (MII != MBB->end()) { 783 MachineInstr *MI = MII++; 784 const TargetInstrDesc &TID = MI->getDesc(); 785 DEBUG({ 786 dbgs() << "\n>> " << *MI << "Regs:"; 787 for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { 788 if (PhysRegState[Reg] == regDisabled) continue; 789 dbgs() << " " << TRI->getName(Reg); 790 switch(PhysRegState[Reg]) { 791 case regFree: 792 break; 793 case regReserved: 794 dbgs() << "*"; 795 break; 796 default: 797 dbgs() << '=' << PrintReg(PhysRegState[Reg]); 798 if (LiveVirtRegs[PhysRegState[Reg]].Dirty) 799 dbgs() << "*"; 800 assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg && 801 "Bad inverse map"); 802 break; 803 } 804 } 805 dbgs() << '\n'; 806 // Check that LiveVirtRegs is the inverse. 807 for (LiveRegMap::iterator i = LiveVirtRegs.begin(), 808 e = LiveVirtRegs.end(); i != e; ++i) { 809 assert(TargetRegisterInfo::isVirtualRegister(i->first) && 810 "Bad map key"); 811 assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) && 812 "Bad map value"); 813 assert(PhysRegState[i->second.PhysReg] == i->first && 814 "Bad inverse map"); 815 } 816 }); 817 818 // Debug values are not allowed to change codegen in any way. 819 if (MI->isDebugValue()) { 820 bool ScanDbgValue = true; 821 while (ScanDbgValue) { 822 ScanDbgValue = false; 823 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 824 MachineOperand &MO = MI->getOperand(i); 825 if (!MO.isReg()) continue; 826 unsigned Reg = MO.getReg(); 827 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 828 LiveDbgValueMap[Reg] = MI; 829 LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg); 830 if (LRI != LiveVirtRegs.end()) 831 setPhysReg(MI, i, LRI->second.PhysReg); 832 else { 833 int SS = StackSlotForVirtReg[Reg]; 834 if (SS == -1) { 835 // We can't allocate a physreg for a DebugValue, sorry! 836 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); 837 MO.setReg(0); 838 } 839 else { 840 // Modify DBG_VALUE now that the value is in a spill slot. 841 int64_t Offset = MI->getOperand(1).getImm(); 842 const MDNode *MDPtr = 843 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 844 DebugLoc DL = MI->getDebugLoc(); 845 if (MachineInstr *NewDV = 846 TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) { 847 DEBUG(dbgs() << "Modifying debug info due to spill:" << 848 "\t" << *MI); 849 MachineBasicBlock *MBB = MI->getParent(); 850 MBB->insert(MBB->erase(MI), NewDV); 851 // Scan NewDV operands from the beginning. 852 MI = NewDV; 853 ScanDbgValue = true; 854 break; 855 } else { 856 // We can't allocate a physreg for a DebugValue; sorry! 857 DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); 858 MO.setReg(0); 859 } 860 } 861 } 862 } 863 } 864 // Next instruction. 865 continue; 866 } 867 868 // If this is a copy, we may be able to coalesce. 869 unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0; 870 if (MI->isCopy()) { 871 CopyDst = MI->getOperand(0).getReg(); 872 CopySrc = MI->getOperand(1).getReg(); 873 CopyDstSub = MI->getOperand(0).getSubReg(); 874 CopySrcSub = MI->getOperand(1).getSubReg(); 875 } 876 877 // Track registers used by instruction. 878 UsedInInstr.reset(); 879 880 // First scan. 881 // Mark physreg uses and early clobbers as used. 882 // Find the end of the virtreg operands 883 unsigned VirtOpEnd = 0; 884 bool hasTiedOps = false; 885 bool hasEarlyClobbers = false; 886 bool hasPartialRedefs = false; 887 bool hasPhysDefs = false; 888 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 889 MachineOperand &MO = MI->getOperand(i); 890 if (!MO.isReg()) continue; 891 unsigned Reg = MO.getReg(); 892 if (!Reg) continue; 893 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 894 VirtOpEnd = i+1; 895 if (MO.isUse()) { 896 hasTiedOps = hasTiedOps || 897 TID.getOperandConstraint(i, TOI::TIED_TO) != -1; 898 } else { 899 if (MO.isEarlyClobber()) 900 hasEarlyClobbers = true; 901 if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) 902 hasPartialRedefs = true; 903 } 904 continue; 905 } 906 if (!Allocatable.test(Reg)) continue; 907 if (MO.isUse()) { 908 usePhysReg(MO); 909 } else if (MO.isEarlyClobber()) { 910 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? 911 regFree : regReserved); 912 hasEarlyClobbers = true; 913 } else 914 hasPhysDefs = true; 915 } 916 917 // The instruction may have virtual register operands that must be allocated 918 // the same register at use-time and def-time: early clobbers and tied 919 // operands. If there are also physical defs, these registers must avoid 920 // both physical defs and uses, making them more constrained than normal 921 // operands. 922 // Similarly, if there are multiple defs and tied operands, we must make 923 // sure the same register is allocated to uses and defs. 924 // We didn't detect inline asm tied operands above, so just make this extra 925 // pass for all inline asm. 926 if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs || 927 (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) { 928 handleThroughOperands(MI, VirtDead); 929 // Don't attempt coalescing when we have funny stuff going on. 930 CopyDst = 0; 931 // Pretend we have early clobbers so the use operands get marked below. 932 // This is not necessary for the common case of a single tied use. 933 hasEarlyClobbers = true; 934 } 935 936 // Second scan. 937 // Allocate virtreg uses. 938 for (unsigned i = 0; i != VirtOpEnd; ++i) { 939 MachineOperand &MO = MI->getOperand(i); 940 if (!MO.isReg()) continue; 941 unsigned Reg = MO.getReg(); 942 if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue; 943 if (MO.isUse()) { 944 LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst); 945 unsigned PhysReg = LRI->second.PhysReg; 946 CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0; 947 if (setPhysReg(MI, i, PhysReg)) 948 killVirtReg(LRI); 949 } 950 } 951 952 MRI->addPhysRegsUsed(UsedInInstr); 953 954 // Track registers defined by instruction - early clobbers and tied uses at 955 // this point. 956 UsedInInstr.reset(); 957 if (hasEarlyClobbers) { 958 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 959 MachineOperand &MO = MI->getOperand(i); 960 if (!MO.isReg()) continue; 961 unsigned Reg = MO.getReg(); 962 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 963 // Look for physreg defs and tied uses. 964 if (!MO.isDef() && !MI->isRegTiedToDefOperand(i)) continue; 965 UsedInInstr.set(Reg); 966 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) 967 UsedInInstr.set(*AS); 968 } 969 } 970 971 unsigned DefOpEnd = MI->getNumOperands(); 972 if (TID.isCall()) { 973 // Spill all virtregs before a call. This serves two purposes: 1. If an 974 // exception is thrown, the landing pad is going to expect to find 975 // registers in their spill slots, and 2. we don't have to wade through 976 // all the <imp-def> operands on the call instruction. 977 DefOpEnd = VirtOpEnd; 978 DEBUG(dbgs() << " Spilling remaining registers before call.\n"); 979 spillAll(MI); 980 981 // The imp-defs are skipped below, but we still need to mark those 982 // registers as used by the function. 983 SkippedInstrs.insert(&TID); 984 } 985 986 // Third scan. 987 // Allocate defs and collect dead defs. 988 for (unsigned i = 0; i != DefOpEnd; ++i) { 989 MachineOperand &MO = MI->getOperand(i); 990 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) 991 continue; 992 unsigned Reg = MO.getReg(); 993 994 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 995 if (!Allocatable.test(Reg)) continue; 996 definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? 997 regFree : regReserved); 998 continue; 999 } 1000 LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc); 1001 unsigned PhysReg = LRI->second.PhysReg; 1002 if (setPhysReg(MI, i, PhysReg)) { 1003 VirtDead.push_back(Reg); 1004 CopyDst = 0; // cancel coalescing; 1005 } else 1006 CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0; 1007 } 1008 1009 // Kill dead defs after the scan to ensure that multiple defs of the same 1010 // register are allocated identically. We didn't need to do this for uses 1011 // because we are crerating our own kill flags, and they are always at the 1012 // last use. 1013 for (unsigned i = 0, e = VirtDead.size(); i != e; ++i) 1014 killVirtReg(VirtDead[i]); 1015 VirtDead.clear(); 1016 1017 MRI->addPhysRegsUsed(UsedInInstr); 1018 1019 if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) { 1020 DEBUG(dbgs() << "-- coalescing: " << *MI); 1021 Coalesced.push_back(MI); 1022 } else { 1023 DEBUG(dbgs() << "<< " << *MI); 1024 } 1025 } 1026 1027 // Spill all physical registers holding virtual registers now. 1028 DEBUG(dbgs() << "Spilling live registers at end of block.\n"); 1029 spillAll(MBB->getFirstTerminator()); 1030 1031 // Erase all the coalesced copies. We are delaying it until now because 1032 // LiveVirtRegs might refer to the instrs. 1033 for (unsigned i = 0, e = Coalesced.size(); i != e; ++i) 1034 MBB->erase(Coalesced[i]); 1035 NumCopies += Coalesced.size(); 1036 1037 DEBUG(MBB->dump()); 1038} 1039 1040/// runOnMachineFunction - Register allocate the whole function 1041/// 1042bool RAFast::runOnMachineFunction(MachineFunction &Fn) { 1043 DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n" 1044 << "********** Function: " 1045 << ((Value*)Fn.getFunction())->getName() << '\n'); 1046 MF = &Fn; 1047 MRI = &MF->getRegInfo(); 1048 TM = &Fn.getTarget(); 1049 TRI = TM->getRegisterInfo(); 1050 TII = TM->getInstrInfo(); 1051 1052 UsedInInstr.resize(TRI->getNumRegs()); 1053 Allocatable = TRI->getAllocatableSet(*MF); 1054 1055 // initialize the virtual->physical register map to have a 'null' 1056 // mapping for all virtual registers 1057 StackSlotForVirtReg.resize(MRI->getNumVirtRegs()); 1058 1059 // Loop over all of the basic blocks, eliminating virtual register references 1060 for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end(); 1061 MBBi != MBBe; ++MBBi) { 1062 MBB = &*MBBi; 1063 AllocateBasicBlock(); 1064 } 1065 1066 // Make sure the set of used physregs is closed under subreg operations. 1067 MRI->closePhysRegsUsed(*TRI); 1068 1069 // Add the clobber lists for all the instructions we skipped earlier. 1070 for (SmallPtrSet<const TargetInstrDesc*, 4>::const_iterator 1071 I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I) 1072 if (const unsigned *Defs = (*I)->getImplicitDefs()) 1073 while (*Defs) 1074 MRI->setPhysRegUsed(*Defs++); 1075 1076 SkippedInstrs.clear(); 1077 StackSlotForVirtReg.clear(); 1078 LiveDbgValueMap.clear(); 1079 return true; 1080} 1081 1082FunctionPass *llvm::createFastRegisterAllocator() { 1083 return new RAFast(); 1084} 1085