RegAllocFast.cpp revision e29098d3fe7ae7599c1a0087625ce2e1de6aba9f 
1//===-- RegAllocFast.cpp - A fast register allocator for debug code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This register allocator allocates registers to a basic block at a time,
11// attempting to keep values in registers and reusing registers as appropriate.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "llvm/BasicBlock.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18#include "llvm/CodeGen/MachineInstr.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/CodeGen/Passes.h"
22#include "llvm/CodeGen/RegAllocRegistry.h"
23#include "llvm/Target/TargetInstrInfo.h"
24#include "llvm/Target/TargetMachine.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/DenseMap.h"
30#include "llvm/ADT/IndexedMap.h"
31#include "llvm/ADT/SmallSet.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/ADT/STLExtras.h"
35#include <algorithm>
36using namespace llvm;
37
38STATISTIC(NumStores, "Number of stores added");
39STATISTIC(NumLoads , "Number of loads added");
40STATISTIC(NumCopies, "Number of copies coalesced");
41
42static RegisterRegAlloc
43  fastRegAlloc("fast", "fast register allocator", createFastRegisterAllocator);
44
45namespace {
46  class RAFast : public MachineFunctionPass {
47  public:
48    static char ID;
49    RAFast() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1),
50               isBulkSpilling(false) {}
51  private:
52    const TargetMachine *TM;
53    MachineFunction *MF;
54    MachineRegisterInfo *MRI;
55    const TargetRegisterInfo *TRI;
56    const TargetInstrInfo *TII;
57
58    // Basic block currently being allocated.
59    MachineBasicBlock *MBB;
60
61    // StackSlotForVirtReg - Maps virtual regs to the frame index where these
62    // values are spilled.
63    IndexedMap<int, VirtReg2IndexFunctor> StackSlotForVirtReg;
64
65    // Everything we know about a live virtual register.
66    struct LiveReg {
67      MachineInstr *LastUse;    // Last instr to use reg.
68      unsigned PhysReg;         // Currently held here.
69      unsigned short LastOpNum; // OpNum on LastUse.
70      bool Dirty;               // Register needs spill.
71
72      LiveReg(unsigned p=0) : LastUse(0), PhysReg(p), LastOpNum(0),
73                              Dirty(false) {}
74    };
75
76    typedef DenseMap<unsigned, LiveReg> LiveRegMap;
77    typedef LiveRegMap::value_type LiveRegEntry;
78
79    // LiveVirtRegs - This map contains entries for each virtual register
80    // that is currently available in a physical register.
81    LiveRegMap LiveVirtRegs;
82
83    // RegState - Track the state of a physical register.
84    enum RegState {
85      // A disabled register is not available for allocation, but an alias may
86      // be in use. A register can only be moved out of the disabled state if
87      // all aliases are disabled.
88      regDisabled,
89
90      // A free register is not currently in use and can be allocated
91      // immediately without checking aliases.
92      regFree,
93
94      // A reserved register has been assigned expolicitly (e.g., setting up a
95      // call parameter), and it remains reserved until it is used.
96      regReserved
97
98      // A register state may also be a virtual register number, indication that
99      // the physical register is currently allocated to a virtual register. In
100      // that case, LiveVirtRegs contains the inverse mapping.
101    };
102
103    // PhysRegState - One of the RegState enums, or a virtreg.
104    std::vector<unsigned> PhysRegState;
105
106    // UsedInInstr - BitVector of physregs that are used in the current
107    // instruction, and so cannot be allocated.
108    BitVector UsedInInstr;
109
110    // Allocatable - vector of allocatable physical registers.
111    BitVector Allocatable;
112
113    // SkippedInstrs - Descriptors of instructions whose clobber list was ignored
114    // because all registers were spilled. It is still necessary to mark all the
115    // clobbered registers as used by the function.
116    SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs;
117
118    // isBulkSpilling - This flag is set when LiveRegMap will be cleared
119    // completely after spilling all live registers. LiveRegMap entries should
120    // not be erased.
121    bool isBulkSpilling;
122
123    enum {
124      spillClean = 1,
125      spillDirty = 100,
126      spillImpossible = ~0u
127    };
128  public:
129    virtual const char *getPassName() const {
130      return "Fast Register Allocator";
131    }
132
133    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
134      AU.setPreservesCFG();
135      AU.addRequiredID(PHIEliminationID);
136      AU.addRequiredID(TwoAddressInstructionPassID);
137      MachineFunctionPass::getAnalysisUsage(AU);
138    }
139
140  private:
141    bool runOnMachineFunction(MachineFunction &Fn);
142    void AllocateBasicBlock();
143    void handleThroughOperands(MachineInstr *MI,
144                               SmallVectorImpl<unsigned> &VirtDead);
145    int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
146    bool isLastUseOfLocalReg(MachineOperand&);
147
148    void addKillFlag(const LiveReg&);
149    void killVirtReg(LiveRegMap::iterator);
150    void killVirtReg(unsigned VirtReg);
151    void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator);
152    void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
153
154    void usePhysReg(MachineOperand&);
155    void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState);
156    unsigned calcSpillCost(unsigned PhysReg) const;
157    void assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg);
158    void allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint);
159    LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
160                                       unsigned VirtReg, unsigned Hint);
161    LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
162                                       unsigned VirtReg, unsigned Hint);
163    void spillAll(MachineInstr *MI);
164    bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
165  };
166  char RAFast::ID = 0;
167}
168
169/// getStackSpaceFor - This allocates space for the specified virtual register
170/// to be held on the stack.
171int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
172  // Find the location Reg would belong...
173  int SS = StackSlotForVirtReg[VirtReg];
174  if (SS != -1)
175    return SS;          // Already has space allocated?
176
177  // Allocate a new stack object for this spill location...
178  int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
179                                                            RC->getAlignment());
180
181  // Assign the slot.
182  StackSlotForVirtReg[VirtReg] = FrameIdx;
183  return FrameIdx;
184}
185
186/// isLastUseOfLocalReg - Return true if MO is the only remaining reference to
187/// its virtual register, and it is guaranteed to be a block-local register.
188///
189bool RAFast::isLastUseOfLocalReg(MachineOperand &MO) {
190  // Check for non-debug uses or defs following MO.
191  // This is the most likely way to fail - fast path it.
192  MachineOperand *Next = &MO;
193  while ((Next = Next->getNextOperandForReg()))
194    if (!Next->isDebug())
195      return false;
196
197  // If the register has ever been spilled or reloaded, we conservatively assume
198  // it is a global register used in multiple blocks.
199  if (StackSlotForVirtReg[MO.getReg()] != -1)
200    return false;
201
202  // Check that the use/def chain has exactly one operand - MO.
203  return &MRI->reg_nodbg_begin(MO.getReg()).getOperand() == &MO;
204}
205
206/// addKillFlag - Set kill flags on last use of a virtual register.
207void RAFast::addKillFlag(const LiveReg &LR) {
208  if (!LR.LastUse) return;
209  MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
210  if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
211    if (MO.getReg() == LR.PhysReg)
212      MO.setIsKill();
213    else
214      LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
215  }
216}
217
218/// killVirtReg - Mark virtreg as no longer available.
219void RAFast::killVirtReg(LiveRegMap::iterator LRI) {
220  addKillFlag(LRI->second);
221  const LiveReg &LR = LRI->second;
222  assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
223  PhysRegState[LR.PhysReg] = regFree;
224  // Erase from LiveVirtRegs unless we're spilling in bulk.
225  if (!isBulkSpilling)
226    LiveVirtRegs.erase(LRI);
227}
228
229/// killVirtReg - Mark virtreg as no longer available.
230void RAFast::killVirtReg(unsigned VirtReg) {
231  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
232         "killVirtReg needs a virtual register");
233  LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
234  if (LRI != LiveVirtRegs.end())
235    killVirtReg(LRI);
236}
237
238/// spillVirtReg - This method spills the value specified by VirtReg into the
239/// corresponding stack slot if needed. If isKill is set, the register is also
240/// killed.
241void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) {
242  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
243         "Spilling a physical register is illegal!");
244  LiveRegMap::iterator LRI = LiveVirtRegs.find(VirtReg);
245  assert(LRI != LiveVirtRegs.end() && "Spilling unmapped virtual register");
246  spillVirtReg(MI, LRI);
247}
248
249/// spillVirtReg - Do the actual work of spilling.
250void RAFast::spillVirtReg(MachineBasicBlock::iterator MI,
251                          LiveRegMap::iterator LRI) {
252  LiveReg &LR = LRI->second;
253  assert(PhysRegState[LR.PhysReg] == LRI->first && "Broken RegState mapping");
254
255  if (LR.Dirty) {
256    // If this physreg is used by the instruction, we want to kill it on the
257    // instruction, not on the spill.
258    bool SpillKill = LR.LastUse != MI;
259    LR.Dirty = false;
260    DEBUG(dbgs() << "Spilling %reg" << LRI->first
261                 << " in " << TRI->getName(LR.PhysReg));
262    const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
263    int FI = getStackSpaceFor(LRI->first, RC);
264    DEBUG(dbgs() << " to stack slot #" << FI << "\n");
265    TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
266    ++NumStores;   // Update statistics
267
268    if (SpillKill)
269      LR.LastUse = 0; // Don't kill register again
270  }
271  killVirtReg(LRI);
272}
273
274/// spillAll - Spill all dirty virtregs without killing them.
275void RAFast::spillAll(MachineInstr *MI) {
276  if (LiveVirtRegs.empty()) return;
277  isBulkSpilling = true;
278  // The LiveRegMap is keyed by an unsigned (the virtreg number), so the order
279  // of spilling here is deterministic, if arbitrary.
280  for (LiveRegMap::iterator i = LiveVirtRegs.begin(), e = LiveVirtRegs.end();
281       i != e; ++i)
282    spillVirtReg(MI, i);
283  LiveVirtRegs.clear();
284  isBulkSpilling = false;
285}
286
287/// usePhysReg - Handle the direct use of a physical register.
288/// Check that the register is not used by a virtreg.
289/// Kill the physreg, marking it free.
290/// This may add implicit kills to MO->getParent() and invalidate MO.
291void RAFast::usePhysReg(MachineOperand &MO) {
292  unsigned PhysReg = MO.getReg();
293  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) &&
294         "Bad usePhysReg operand");
295
296  switch (PhysRegState[PhysReg]) {
297  case regDisabled:
298    break;
299  case regReserved:
300    PhysRegState[PhysReg] = regFree;
301    // Fall through
302  case regFree:
303    UsedInInstr.set(PhysReg);
304    MO.setIsKill();
305    return;
306  default:
307    // The physreg was allocated to a virtual register. That means to value we
308    // wanted has been clobbered.
309    llvm_unreachable("Instruction uses an allocated register");
310  }
311
312  // Maybe a superregister is reserved?
313  for (const unsigned *AS = TRI->getAliasSet(PhysReg);
314       unsigned Alias = *AS; ++AS) {
315    switch (PhysRegState[Alias]) {
316    case regDisabled:
317      break;
318    case regReserved:
319      assert(TRI->isSuperRegister(PhysReg, Alias) &&
320             "Instruction is not using a subregister of a reserved register");
321      // Leave the superregister in the working set.
322      PhysRegState[Alias] = regFree;
323      UsedInInstr.set(Alias);
324      MO.getParent()->addRegisterKilled(Alias, TRI, true);
325      return;
326    case regFree:
327      if (TRI->isSuperRegister(PhysReg, Alias)) {
328        // Leave the superregister in the working set.
329        UsedInInstr.set(Alias);
330        MO.getParent()->addRegisterKilled(Alias, TRI, true);
331        return;
332      }
333      // Some other alias was in the working set - clear it.
334      PhysRegState[Alias] = regDisabled;
335      break;
336    default:
337      llvm_unreachable("Instruction uses an alias of an allocated register");
338    }
339  }
340
341  // All aliases are disabled, bring register into working set.
342  PhysRegState[PhysReg] = regFree;
343  UsedInInstr.set(PhysReg);
344  MO.setIsKill();
345}
346
347/// definePhysReg - Mark PhysReg as reserved or free after spilling any
348/// virtregs. This is very similar to defineVirtReg except the physreg is
349/// reserved instead of allocated.
350void RAFast::definePhysReg(MachineInstr *MI, unsigned PhysReg,
351                           RegState NewState) {
352  UsedInInstr.set(PhysReg);
353  switch (unsigned VirtReg = PhysRegState[PhysReg]) {
354  case regDisabled:
355    break;
356  default:
357    spillVirtReg(MI, VirtReg);
358    // Fall through.
359  case regFree:
360  case regReserved:
361    PhysRegState[PhysReg] = NewState;
362    return;
363  }
364
365  // This is a disabled register, disable all aliases.
366  PhysRegState[PhysReg] = NewState;
367  for (const unsigned *AS = TRI->getAliasSet(PhysReg);
368       unsigned Alias = *AS; ++AS) {
369    UsedInInstr.set(Alias);
370    switch (unsigned VirtReg = PhysRegState[Alias]) {
371    case regDisabled:
372      break;
373    default:
374      spillVirtReg(MI, VirtReg);
375      // Fall through.
376    case regFree:
377    case regReserved:
378      PhysRegState[Alias] = regDisabled;
379      if (TRI->isSuperRegister(PhysReg, Alias))
380        return;
381      break;
382    }
383  }
384}
385
386
387// calcSpillCost - Return the cost of spilling clearing out PhysReg and
388// aliases so it is free for allocation.
389// Returns 0 when PhysReg is free or disabled with all aliases disabled - it
390// can be allocated directly.
391// Returns spillImpossible when PhysReg or an alias can't be spilled.
392unsigned RAFast::calcSpillCost(unsigned PhysReg) const {
393  if (UsedInInstr.test(PhysReg))
394    return spillImpossible;
395  switch (unsigned VirtReg = PhysRegState[PhysReg]) {
396  case regDisabled:
397    break;
398  case regFree:
399    return 0;
400  case regReserved:
401    return spillImpossible;
402  default:
403    return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
404  }
405
406  // This is a disabled register, add up const of aliases.
407  unsigned Cost = 0;
408  for (const unsigned *AS = TRI->getAliasSet(PhysReg);
409       unsigned Alias = *AS; ++AS) {
410    if (UsedInInstr.test(Alias))
411      return spillImpossible;
412    switch (unsigned VirtReg = PhysRegState[Alias]) {
413    case regDisabled:
414      break;
415    case regFree:
416      ++Cost;
417      break;
418    case regReserved:
419      return spillImpossible;
420    default:
421      Cost += LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean;
422      break;
423    }
424  }
425  return Cost;
426}
427
428
429/// assignVirtToPhysReg - This method updates local state so that we know
430/// that PhysReg is the proper container for VirtReg now.  The physical
431/// register must not be used for anything else when this is called.
432///
433void RAFast::assignVirtToPhysReg(LiveRegEntry &LRE, unsigned PhysReg) {
434  DEBUG(dbgs() << "Assigning %reg" << LRE.first << " to "
435               << TRI->getName(PhysReg) << "\n");
436  PhysRegState[PhysReg] = LRE.first;
437  assert(!LRE.second.PhysReg && "Already assigned a physreg");
438  LRE.second.PhysReg = PhysReg;
439}
440
441/// allocVirtReg - Allocate a physical register for VirtReg.
442void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) {
443  const unsigned VirtReg = LRE.first;
444
445  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
446         "Can only allocate virtual registers");
447
448  const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
449
450  // Ignore invalid hints.
451  if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
452               !RC->contains(Hint) || !Allocatable.test(Hint)))
453    Hint = 0;
454
455  // Take hint when possible.
456  if (Hint) {
457    switch(calcSpillCost(Hint)) {
458    default:
459      definePhysReg(MI, Hint, regFree);
460      // Fall through.
461    case 0:
462      return assignVirtToPhysReg(LRE, Hint);
463    case spillImpossible:
464      break;
465    }
466  }
467
468  TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
469  TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
470
471  // First try to find a completely free register.
472  for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
473    unsigned PhysReg = *I;
474    if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg))
475      return assignVirtToPhysReg(LRE, PhysReg);
476  }
477
478  DEBUG(dbgs() << "Allocating %reg" << VirtReg << " from " << RC->getName()
479               << "\n");
480
481  unsigned BestReg = 0, BestCost = spillImpossible;
482  for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
483    unsigned Cost = calcSpillCost(*I);
484    // Cost is 0 when all aliases are already disabled.
485    if (Cost == 0)
486      return assignVirtToPhysReg(LRE, *I);
487    if (Cost < BestCost)
488      BestReg = *I, BestCost = Cost;
489  }
490
491  if (BestReg) {
492    definePhysReg(MI, BestReg, regFree);
493    return assignVirtToPhysReg(LRE, BestReg);
494  }
495
496  // Nothing we can do.
497  std::string msg;
498  raw_string_ostream Msg(msg);
499  Msg << "Ran out of registers during register allocation!";
500  if (MI->isInlineAsm()) {
501    Msg << "\nPlease check your inline asm statement for "
502        << "invalid constraints:\n";
503    MI->print(Msg, TM);
504  }
505  report_fatal_error(Msg.str());
506}
507
508/// defineVirtReg - Allocate a register for VirtReg and mark it as dirty.
509RAFast::LiveRegMap::iterator
510RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
511                      unsigned VirtReg, unsigned Hint) {
512  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
513         "Not a virtual register");
514  LiveRegMap::iterator LRI;
515  bool New;
516  tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
517  LiveReg &LR = LRI->second;
518  if (New) {
519    // If there is no hint, peek at the only use of this register.
520    if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
521        MRI->hasOneNonDBGUse(VirtReg)) {
522      const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
523      // It's a copy, use the destination register as a hint.
524      if (UseMI.isCopyLike())
525        Hint = UseMI.getOperand(0).getReg();
526    }
527    allocVirtReg(MI, *LRI, Hint);
528  } else if (LR.LastUse) {
529    // Redefining a live register - kill at the last use, unless it is this
530    // instruction defining VirtReg multiple times.
531    if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
532      addKillFlag(LR);
533  }
534  assert(LR.PhysReg && "Register not assigned");
535  LR.LastUse = MI;
536  LR.LastOpNum = OpNum;
537  LR.Dirty = true;
538  UsedInInstr.set(LR.PhysReg);
539  return LRI;
540}
541
542/// reloadVirtReg - Make sure VirtReg is available in a physreg and return it.
543RAFast::LiveRegMap::iterator
544RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum,
545                      unsigned VirtReg, unsigned Hint) {
546  assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
547         "Not a virtual register");
548  LiveRegMap::iterator LRI;
549  bool New;
550  tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
551  LiveReg &LR = LRI->second;
552  MachineOperand &MO = MI->getOperand(OpNum);
553  if (New) {
554    allocVirtReg(MI, *LRI, Hint);
555    const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
556    int FrameIndex = getStackSpaceFor(VirtReg, RC);
557    DEBUG(dbgs() << "Reloading %reg" << VirtReg << " into "
558                 << TRI->getName(LR.PhysReg) << "\n");
559    TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FrameIndex, RC, TRI);
560    ++NumLoads;
561  } else if (LR.Dirty) {
562    if (isLastUseOfLocalReg(MO)) {
563      DEBUG(dbgs() << "Killing last use: " << MO << "\n");
564      if (MO.isUse())
565        MO.setIsKill();
566      else
567        MO.setIsDead();
568    } else if (MO.isKill()) {
569      DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
570      MO.setIsKill(false);
571    } else if (MO.isDead()) {
572      DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
573      MO.setIsDead(false);
574    }
575  } else if (MO.isKill()) {
576    // We must remove kill flags from uses of reloaded registers because the
577    // register would be killed immediately, and there might be a second use:
578    //   %foo = OR %x<kill>, %x
579    // This would cause a second reload of %x into a different register.
580    DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
581    MO.setIsKill(false);
582  } else if (MO.isDead()) {
583    DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
584    MO.setIsDead(false);
585  }
586  assert(LR.PhysReg && "Register not assigned");
587  LR.LastUse = MI;
588  LR.LastOpNum = OpNum;
589  UsedInInstr.set(LR.PhysReg);
590  return LRI;
591}
592
593// setPhysReg - Change operand OpNum in MI the refer the PhysReg, considering
594// subregs. This may invalidate any operand pointers.
595// Return true if the operand kills its register.
596bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) {
597  MachineOperand &MO = MI->getOperand(OpNum);
598  if (!MO.getSubReg()) {
599    MO.setReg(PhysReg);
600    return MO.isKill() || MO.isDead();
601  }
602
603  // Handle subregister index.
604  MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
605  MO.setSubReg(0);
606
607  // A kill flag implies killing the full register. Add corresponding super
608  // register kill.
609  if (MO.isKill()) {
610    MI->addRegisterKilled(PhysReg, TRI, true);
611    return true;
612  }
613  return MO.isDead();
614}
615
616// Handle special instruction operand like early clobbers and tied ops when
617// there are additional physreg defines.
618void RAFast::handleThroughOperands(MachineInstr *MI,
619                                   SmallVectorImpl<unsigned> &VirtDead) {
620  DEBUG(dbgs() << "Scanning for through registers:");
621  SmallSet<unsigned, 8> ThroughRegs;
622  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
623    MachineOperand &MO = MI->getOperand(i);
624    if (!MO.isReg()) continue;
625    unsigned Reg = MO.getReg();
626    if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
627    if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
628        (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
629      if (ThroughRegs.insert(Reg))
630        DEBUG(dbgs() << " %reg" << Reg);
631    }
632  }
633
634  // If any physreg defines collide with preallocated through registers,
635  // we must spill and reallocate.
636  DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
637  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
638    MachineOperand &MO = MI->getOperand(i);
639    if (!MO.isReg() || !MO.isDef()) continue;
640    unsigned Reg = MO.getReg();
641    if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
642    UsedInInstr.set(Reg);
643    if (ThroughRegs.count(PhysRegState[Reg]))
644      definePhysReg(MI, Reg, regFree);
645    for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
646      UsedInInstr.set(*AS);
647      if (ThroughRegs.count(PhysRegState[*AS]))
648        definePhysReg(MI, *AS, regFree);
649    }
650  }
651
652  SmallVector<unsigned, 8> PartialDefs;
653  DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n");
654  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
655    MachineOperand &MO = MI->getOperand(i);
656    if (!MO.isReg()) continue;
657    unsigned Reg = MO.getReg();
658    if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
659    if (MO.isUse()) {
660      unsigned DefIdx = 0;
661      if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
662      DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
663        << DefIdx << ".\n");
664      LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
665      unsigned PhysReg = LRI->second.PhysReg;
666      setPhysReg(MI, i, PhysReg);
667      // Note: we don't update the def operand yet. That would cause the normal
668      // def-scan to attempt spilling.
669    } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
670      DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
671      // Reload the register, but don't assign to the operand just yet.
672      // That would confuse the later phys-def processing pass.
673      LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
674      PartialDefs.push_back(LRI->second.PhysReg);
675    } else if (MO.isEarlyClobber()) {
676      // Note: defineVirtReg may invalidate MO.
677      LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
678      unsigned PhysReg = LRI->second.PhysReg;
679      if (setPhysReg(MI, i, PhysReg))
680        VirtDead.push_back(Reg);
681    }
682  }
683
684  // Restore UsedInInstr to a state usable for allocating normal virtual uses.
685  UsedInInstr.reset();
686  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
687    MachineOperand &MO = MI->getOperand(i);
688    if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
689    unsigned Reg = MO.getReg();
690    if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
691    UsedInInstr.set(Reg);
692    for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
693      UsedInInstr.set(*AS);
694  }
695
696  // Also mark PartialDefs as used to avoid reallocation.
697  for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
698    UsedInInstr.set(PartialDefs[i]);
699}
700
701void RAFast::AllocateBasicBlock() {
702  DEBUG(dbgs() << "\nAllocating " << *MBB);
703
704  PhysRegState.assign(TRI->getNumRegs(), regDisabled);
705  assert(LiveVirtRegs.empty() && "Mapping not cleared form last block?");
706
707  MachineBasicBlock::iterator MII = MBB->begin();
708
709  // Add live-in registers as live.
710  for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
711         E = MBB->livein_end(); I != E; ++I)
712    definePhysReg(MII, *I, regReserved);
713
714  SmallVector<unsigned, 8> VirtDead;
715  SmallVector<MachineInstr*, 32> Coalesced;
716
717  // Otherwise, sequentially allocate each instruction in the MBB.
718  while (MII != MBB->end()) {
719    MachineInstr *MI = MII++;
720    const TargetInstrDesc &TID = MI->getDesc();
721    DEBUG({
722        dbgs() << "\n>> " << *MI << "Regs:";
723        for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
724          if (PhysRegState[Reg] == regDisabled) continue;
725          dbgs() << " " << TRI->getName(Reg);
726          switch(PhysRegState[Reg]) {
727          case regFree:
728            break;
729          case regReserved:
730            dbgs() << "*";
731            break;
732          default:
733            dbgs() << "=%reg" << PhysRegState[Reg];
734            if (LiveVirtRegs[PhysRegState[Reg]].Dirty)
735              dbgs() << "*";
736            assert(LiveVirtRegs[PhysRegState[Reg]].PhysReg == Reg &&
737                   "Bad inverse map");
738            break;
739          }
740        }
741        dbgs() << '\n';
742        // Check that LiveVirtRegs is the inverse.
743        for (LiveRegMap::iterator i = LiveVirtRegs.begin(),
744             e = LiveVirtRegs.end(); i != e; ++i) {
745           assert(TargetRegisterInfo::isVirtualRegister(i->first) &&
746                  "Bad map key");
747           assert(TargetRegisterInfo::isPhysicalRegister(i->second.PhysReg) &&
748                  "Bad map value");
749           assert(PhysRegState[i->second.PhysReg] == i->first &&
750                  "Bad inverse map");
751        }
752      });
753
754    // Debug values are not allowed to change codegen in any way.
755    if (MI->isDebugValue()) {
756      bool ScanDbgValue = true;
757      while (ScanDbgValue) {
758        ScanDbgValue = false;
759        for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
760          MachineOperand &MO = MI->getOperand(i);
761          if (!MO.isReg()) continue;
762          unsigned Reg = MO.getReg();
763          if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
764          LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
765          if (LRI != LiveVirtRegs.end())
766            setPhysReg(MI, i, LRI->second.PhysReg);
767          else {
768            int SS = StackSlotForVirtReg[Reg];
769            if (SS == -1)
770              MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
771            else {
772              // Modify DBG_VALUE now that the value is in a spill slot.
773              uint64_t Offset = MI->getOperand(1).getImm();
774              const MDNode *MDPtr =
775                MI->getOperand(MI->getNumOperands()-1).getMetadata();
776              DebugLoc DL = MI->getDebugLoc();
777              if (MachineInstr *NewDV =
778                  TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) {
779                DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
780                MachineBasicBlock *MBB = MI->getParent();
781                MBB->insert(MBB->erase(MI), NewDV);
782                // Scan NewDV operands from the beginning.
783                MI = NewDV;
784                ScanDbgValue = true;
785                break;
786              } else
787                MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry!
788            }
789          }
790        }
791      }
792      // Next instruction.
793      continue;
794    }
795
796    // If this is a copy, we may be able to coalesce.
797    unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
798    if (MI->isCopy()) {
799      CopyDst = MI->getOperand(0).getReg();
800      CopySrc = MI->getOperand(1).getReg();
801      CopyDstSub = MI->getOperand(0).getSubReg();
802      CopySrcSub = MI->getOperand(1).getSubReg();
803    }
804
805    // Track registers used by instruction.
806    UsedInInstr.reset();
807
808    // First scan.
809    // Mark physreg uses and early clobbers as used.
810    // Find the end of the virtreg operands
811    unsigned VirtOpEnd = 0;
812    bool hasTiedOps = false;
813    bool hasEarlyClobbers = false;
814    bool hasPartialRedefs = false;
815    bool hasPhysDefs = false;
816    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
817      MachineOperand &MO = MI->getOperand(i);
818      if (!MO.isReg()) continue;
819      unsigned Reg = MO.getReg();
820      if (!Reg) continue;
821      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
822        VirtOpEnd = i+1;
823        if (MO.isUse()) {
824          hasTiedOps = hasTiedOps ||
825                                TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
826        } else {
827          if (MO.isEarlyClobber())
828            hasEarlyClobbers = true;
829          if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
830            hasPartialRedefs = true;
831        }
832        continue;
833      }
834      if (!Allocatable.test(Reg)) continue;
835      if (MO.isUse()) {
836        usePhysReg(MO);
837      } else if (MO.isEarlyClobber()) {
838        definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
839                               regFree : regReserved);
840        hasEarlyClobbers = true;
841      } else
842        hasPhysDefs = true;
843    }
844
845    // The instruction may have virtual register operands that must be allocated
846    // the same register at use-time and def-time: early clobbers and tied
847    // operands. If there are also physical defs, these registers must avoid
848    // both physical defs and uses, making them more constrained than normal
849    // operands.
850    // We didn't detect inline asm tied operands above, so just make this extra
851    // pass for all inline asm.
852    if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
853        (hasTiedOps && hasPhysDefs)) {
854      handleThroughOperands(MI, VirtDead);
855      // Don't attempt coalescing when we have funny stuff going on.
856      CopyDst = 0;
857    }
858
859    // Second scan.
860    // Allocate virtreg uses.
861    for (unsigned i = 0; i != VirtOpEnd; ++i) {
862      MachineOperand &MO = MI->getOperand(i);
863      if (!MO.isReg()) continue;
864      unsigned Reg = MO.getReg();
865      if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
866      if (MO.isUse()) {
867        LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, CopyDst);
868        unsigned PhysReg = LRI->second.PhysReg;
869        CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
870        if (setPhysReg(MI, i, PhysReg))
871          killVirtReg(LRI);
872      }
873    }
874
875    MRI->addPhysRegsUsed(UsedInInstr);
876
877    // Track registers defined by instruction - early clobbers at this point.
878    UsedInInstr.reset();
879    if (hasEarlyClobbers) {
880      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
881        MachineOperand &MO = MI->getOperand(i);
882        if (!MO.isReg() || !MO.isDef()) continue;
883        unsigned Reg = MO.getReg();
884        if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
885        UsedInInstr.set(Reg);
886        for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
887          UsedInInstr.set(*AS);
888      }
889    }
890
891    unsigned DefOpEnd = MI->getNumOperands();
892    if (TID.isCall()) {
893      // Spill all virtregs before a call. This serves two purposes: 1. If an
894      // exception is thrown, the landing pad is going to expect to find registers
895      // in their spill slots, and 2. we don't have to wade through all the
896      // <imp-def> operands on the call instruction.
897      DefOpEnd = VirtOpEnd;
898      DEBUG(dbgs() << "  Spilling remaining registers before call.\n");
899      spillAll(MI);
900
901      // The imp-defs are skipped below, but we still need to mark those
902      // registers as used by the function.
903      SkippedInstrs.insert(&TID);
904    }
905
906    // Third scan.
907    // Allocate defs and collect dead defs.
908    for (unsigned i = 0; i != DefOpEnd; ++i) {
909      MachineOperand &MO = MI->getOperand(i);
910      if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
911        continue;
912      unsigned Reg = MO.getReg();
913
914      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
915        if (!Allocatable.test(Reg)) continue;
916        definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
917                               regFree : regReserved);
918        continue;
919      }
920      LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, CopySrc);
921      unsigned PhysReg = LRI->second.PhysReg;
922      if (setPhysReg(MI, i, PhysReg)) {
923        VirtDead.push_back(Reg);
924        CopyDst = 0; // cancel coalescing;
925      } else
926        CopyDst = (CopyDst == Reg || CopyDst == PhysReg) ? PhysReg : 0;
927    }
928
929    // Kill dead defs after the scan to ensure that multiple defs of the same
930    // register are allocated identically. We didn't need to do this for uses
931    // because we are crerating our own kill flags, and they are always at the
932    // last use.
933    for (unsigned i = 0, e = VirtDead.size(); i != e; ++i)
934      killVirtReg(VirtDead[i]);
935    VirtDead.clear();
936
937    MRI->addPhysRegsUsed(UsedInInstr);
938
939    if (CopyDst && CopyDst == CopySrc && CopyDstSub == CopySrcSub) {
940      DEBUG(dbgs() << "-- coalescing: " << *MI);
941      Coalesced.push_back(MI);
942    } else {
943      DEBUG(dbgs() << "<< " << *MI);
944    }
945  }
946
947  // Spill all physical registers holding virtual registers now.
948  DEBUG(dbgs() << "Spilling live registers at end of block.\n");
949  spillAll(MBB->getFirstTerminator());
950
951  // Erase all the coalesced copies. We are delaying it until now because
952  // LiveVirtRegs might refer to the instrs.
953  for (unsigned i = 0, e = Coalesced.size(); i != e; ++i)
954    MBB->erase(Coalesced[i]);
955  NumCopies += Coalesced.size();
956
957  DEBUG(MBB->dump());
958}
959
960/// runOnMachineFunction - Register allocate the whole function
961///
962bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
963  DEBUG(dbgs() << "********** FAST REGISTER ALLOCATION **********\n"
964               << "********** Function: "
965               << ((Value*)Fn.getFunction())->getName() << '\n');
966  MF = &Fn;
967  MRI = &MF->getRegInfo();
968  TM = &Fn.getTarget();
969  TRI = TM->getRegisterInfo();
970  TII = TM->getInstrInfo();
971
972  UsedInInstr.resize(TRI->getNumRegs());
973  Allocatable = TRI->getAllocatableSet(*MF);
974
975  // initialize the virtual->physical register map to have a 'null'
976  // mapping for all virtual registers
977  unsigned LastVirtReg = MRI->getLastVirtReg();
978  StackSlotForVirtReg.grow(LastVirtReg);
979
980  // Loop over all of the basic blocks, eliminating virtual register references
981  for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
982       MBBi != MBBe; ++MBBi) {
983    MBB = &*MBBi;
984    AllocateBasicBlock();
985  }
986
987  // Make sure the set of used physregs is closed under subreg operations.
988  MRI->closePhysRegsUsed(*TRI);
989
990  // Add the clobber lists for all the instructions we skipped earlier.
991  for (SmallPtrSet<const TargetInstrDesc*, 4>::const_iterator
992       I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I)
993    if (const unsigned *Defs = (*I)->getImplicitDefs())
994      while (*Defs)
995        MRI->setPhysRegUsed(*Defs++);
996
997  SkippedInstrs.clear();
998  StackSlotForVirtReg.clear();
999  return true;
1000}
1001
1002FunctionPass *llvm::createFastRegisterAllocator() {
1003  return new RAFast();
1004}
1005