RegAllocGreedy.cpp revision 5a4308bca86728767ea5d9e5df8d8e3351e33c9a
1//===-- RegAllocGreedy.cpp - greedy register allocator --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the RAGreedy function pass for register allocation in 11// optimized builds. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "AllocationOrder.h" 17#include "LiveIntervalUnion.h" 18#include "RegAllocBase.h" 19#include "Spiller.h" 20#include "VirtRegMap.h" 21#include "VirtRegRewriter.h" 22#include "llvm/Analysis/AliasAnalysis.h" 23#include "llvm/Function.h" 24#include "llvm/PassAnalysisSupport.h" 25#include "llvm/CodeGen/CalcSpillWeights.h" 26#include "llvm/CodeGen/LiveIntervalAnalysis.h" 27#include "llvm/CodeGen/LiveStackAnalysis.h" 28#include "llvm/CodeGen/MachineFunctionPass.h" 29#include "llvm/CodeGen/MachineLoopInfo.h" 30#include "llvm/CodeGen/MachineRegisterInfo.h" 31#include "llvm/CodeGen/Passes.h" 32#include "llvm/CodeGen/RegAllocRegistry.h" 33#include "llvm/CodeGen/RegisterCoalescer.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38 39using namespace llvm; 40 41static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", 42 createGreedyRegisterAllocator); 43 44namespace { 45class RAGreedy : public MachineFunctionPass, public RegAllocBase { 46 // context 47 MachineFunction *MF; 48 const TargetMachine *TM; 49 MachineRegisterInfo *MRI; 50 51 BitVector ReservedRegs; 52 53 // analyses 54 LiveStacks *LS; 55 56 // state 57 std::auto_ptr<Spiller> SpillerInstance; 58 59public: 60 RAGreedy(); 61 62 /// Return the pass name. 63 virtual const char* getPassName() const { 64 return "Basic Register Allocator"; 65 } 66 67 /// RAGreedy analysis usage. 68 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 69 70 virtual void releaseMemory(); 71 72 virtual Spiller &spiller() { return *SpillerInstance; } 73 74 virtual float getPriority(LiveInterval *LI); 75 76 virtual unsigned selectOrSplit(LiveInterval &VirtReg, 77 SmallVectorImpl<LiveInterval*> &SplitVRegs); 78 79 /// Perform register allocation. 80 virtual bool runOnMachineFunction(MachineFunction &mf); 81 82 static char ID; 83 84private: 85 bool checkUncachedInterference(LiveInterval &, unsigned); 86 bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg); 87 bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg); 88}; 89} // end anonymous namespace 90 91char RAGreedy::ID = 0; 92 93FunctionPass* llvm::createGreedyRegisterAllocator() { 94 return new RAGreedy(); 95} 96 97RAGreedy::RAGreedy(): MachineFunctionPass(ID) { 98 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 99 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 100 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry()); 101 initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry()); 102 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); 103 initializeLiveStacksPass(*PassRegistry::getPassRegistry()); 104 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); 105 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); 106 initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); 107} 108 109void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const { 110 AU.setPreservesCFG(); 111 AU.addRequired<AliasAnalysis>(); 112 AU.addPreserved<AliasAnalysis>(); 113 AU.addRequired<LiveIntervals>(); 114 AU.addPreserved<SlotIndexes>(); 115 if (StrongPHIElim) 116 AU.addRequiredID(StrongPHIEliminationID); 117 AU.addRequiredTransitive<RegisterCoalescer>(); 118 AU.addRequired<CalculateSpillWeights>(); 119 AU.addRequired<LiveStacks>(); 120 AU.addPreserved<LiveStacks>(); 121 AU.addRequiredID(MachineDominatorsID); 122 AU.addPreservedID(MachineDominatorsID); 123 AU.addRequired<MachineLoopInfo>(); 124 AU.addPreserved<MachineLoopInfo>(); 125 AU.addRequired<VirtRegMap>(); 126 AU.addPreserved<VirtRegMap>(); 127 MachineFunctionPass::getAnalysisUsage(AU); 128} 129 130void RAGreedy::releaseMemory() { 131 SpillerInstance.reset(0); 132 RegAllocBase::releaseMemory(); 133} 134 135float RAGreedy::getPriority(LiveInterval *LI) { 136 float Priority = LI->weight; 137 138 // Prioritize hinted registers so they are allocated first. 139 std::pair<unsigned, unsigned> Hint; 140 if (Hint.first || Hint.second) { 141 // The hint can be target specific, a virtual register, or a physreg. 142 Priority *= 2; 143 144 // Prefer physreg hints above anything else. 145 if (Hint.first == 0 && TargetRegisterInfo::isPhysicalRegister(Hint.second)) 146 Priority *= 2; 147 } 148 return Priority; 149} 150 151// Check interference without using the cache. 152bool RAGreedy::checkUncachedInterference(LiveInterval &VirtReg, 153 unsigned PhysReg) { 154 LiveIntervalUnion::Query subQ(&VirtReg, &PhysReg2LiveUnion[PhysReg]); 155 if (subQ.checkInterference()) 156 return true; 157 for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) { 158 subQ.init(&VirtReg, &PhysReg2LiveUnion[*AliasI]); 159 if (subQ.checkInterference()) 160 return true; 161 } 162 return false; 163} 164 165// Attempt to reassign this virtual register to a different physical register. 166// 167// FIXME: we are not yet caching these "second-level" interferences discovered 168// in the sub-queries. These interferences can change with each call to 169// selectOrSplit. However, we could implement a "may-interfere" cache that 170// could be conservatively dirtied when we reassign or split. 171// 172// FIXME: This may result in a lot of alias queries. We could summarize alias 173// live intervals in their parent register's live union, but it's messy. 174bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg, 175 unsigned OldPhysReg) { 176 assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) && 177 "inconsistent phys reg assigment"); 178 179 AllocationOrder Order(InterferingVReg.reg, *VRM, ReservedRegs); 180 while (unsigned PhysReg = Order.next()) { 181 if (PhysReg == OldPhysReg) 182 continue; 183 184 if (checkUncachedInterference(InterferingVReg, PhysReg)) 185 continue; 186 187 DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " << 188 TRI->getName(OldPhysReg) << " to " << TRI->getName(PhysReg) << '\n'); 189 190 // Reassign the interfering virtual reg to this physical reg. 191 PhysReg2LiveUnion[OldPhysReg].extract(InterferingVReg); 192 VRM->clearVirt(InterferingVReg.reg); 193 VRM->assignVirt2Phys(InterferingVReg.reg, PhysReg); 194 PhysReg2LiveUnion[PhysReg].unify(InterferingVReg); 195 196 return true; 197 } 198 return false; 199} 200 201// Collect all virtual regs currently assigned to PhysReg that interfere with 202// VirtReg. 203// 204// Currently, for simplicity, we only attempt to reassign a single interference 205// within the same register class. 206bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) { 207 LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg); 208 209 // Limit the interference search to one interference. 210 Q.collectInterferingVRegs(1); 211 assert(Q.interferingVRegs().size() == 1 && 212 "expected at least one interference"); 213 214 // Do not attempt reassignment unless we find only a single interference. 215 if (!Q.seenAllInterferences()) 216 return false; 217 218 // Don't allow any interferences on aliases. 219 for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) { 220 if (query(VirtReg, *AliasI).checkInterference()) 221 return false; 222 } 223 224 return reassignVReg(*Q.interferingVRegs()[0], PhysReg); 225} 226 227unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, 228 SmallVectorImpl<LiveInterval*> &SplitVRegs) { 229 // Populate a list of physical register spill candidates. 230 SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands; 231 232 // Check for an available register in this class. 233 DEBUG({ 234 const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg); 235 dbgs() << "RegClass: " << TRC->getName() << ' '); 236 }); 237 238 AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs); 239 while (unsigned PhysReg = Order.next()) { 240 // Check interference and as a side effect, intialize queries for this 241 // VirtReg and its aliases. 242 unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg); 243 if (InterfReg == 0) { 244 // Found an available register. 245 return PhysReg; 246 } 247 assert(!VirtReg.empty() && "Empty VirtReg has interference"); 248 LiveInterval *InterferingVirtReg = 249 Queries[InterfReg].firstInterference().liveUnionPos().value(); 250 251 // The current VirtReg must either be spillable, or one of its interferences 252 // must have less spill weight. 253 if (InterferingVirtReg->weight < VirtReg.weight ) { 254 // For simplicity, only consider reassigning registers in the same class. 255 if (InterfReg == PhysReg) 256 ReassignCands.push_back(PhysReg); 257 else 258 PhysRegSpillCands.push_back(PhysReg); 259 } 260 } 261 262 // Try to reassign interfering physical register. Priority among 263 // PhysRegSpillCands does not matter yet, because the reassigned virtual 264 // registers will still be assigned to physical registers. 265 for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(), 266 PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { 267 if (reassignInterferences(VirtReg, *PhysRegI)) 268 // Reassignment successfull. The caller may allocate now to this PhysReg. 269 return *PhysRegI; 270 } 271 272 PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(), 273 ReassignCands.end()); 274 275 // Try to spill another interfering reg with less spill weight. 276 // 277 // FIXME: do this in two steps: (1) check for unspillable interferences while 278 // accumulating spill weight; (2) spill the interferences with lowest 279 // aggregate spill weight. 280 for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(), 281 PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { 282 283 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue; 284 285 assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 && 286 "Interference after spill."); 287 // Tell the caller to allocate to this newly freed physical register. 288 return *PhysRegI; 289 } 290 291 // No other spill candidates were found, so spill the current VirtReg. 292 DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); 293 SmallVector<LiveInterval*, 1> pendingSpills; 294 295 spiller().spill(&VirtReg, SplitVRegs, pendingSpills); 296 297 // The live virtual register requesting allocation was spilled, so tell 298 // the caller not to allocate anything during this round. 299 return 0; 300} 301 302bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { 303 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n" 304 << "********** Function: " 305 << ((Value*)mf.getFunction())->getName() << '\n'); 306 307 MF = &mf; 308 TM = &mf.getTarget(); 309 MRI = &mf.getRegInfo(); 310 311 const TargetRegisterInfo *TRI = TM->getRegisterInfo(); 312 RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(), 313 getAnalysis<LiveIntervals>()); 314 315 ReservedRegs = TRI->getReservedRegs(*MF); 316 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); 317 allocatePhysRegs(); 318 addMBBLiveIns(MF); 319 320 // Run rewriter 321 std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter()); 322 rewriter->runOnMachineFunction(*MF, *VRM, LIS); 323 324 // The pass output is in VirtRegMap. Release all the transient data. 325 releaseMemory(); 326 327 return true; 328} 329