RegAllocGreedy.cpp revision 9384111e90cb840e7eb867098f19910cf4c4a11d
1//===-- RegAllocGreedy.cpp - greedy register allocator --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the RAGreedy function pass for register allocation in 11// optimized builds. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "regalloc" 16#include "AllocationOrder.h" 17#include "InterferenceCache.h" 18#include "LiveDebugVariables.h" 19#include "LiveRangeEdit.h" 20#include "RegAllocBase.h" 21#include "Spiller.h" 22#include "SpillPlacement.h" 23#include "SplitKit.h" 24#include "VirtRegMap.h" 25#include "llvm/ADT/Statistic.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Function.h" 28#include "llvm/PassAnalysisSupport.h" 29#include "llvm/CodeGen/CalcSpillWeights.h" 30#include "llvm/CodeGen/EdgeBundles.h" 31#include "llvm/CodeGen/LiveIntervalAnalysis.h" 32#include "llvm/CodeGen/LiveStackAnalysis.h" 33#include "llvm/CodeGen/MachineDominators.h" 34#include "llvm/CodeGen/MachineFunctionPass.h" 35#include "llvm/CodeGen/MachineLoopInfo.h" 36#include "llvm/CodeGen/MachineRegisterInfo.h" 37#include "llvm/CodeGen/Passes.h" 38#include "llvm/CodeGen/RegAllocRegistry.h" 39#include "llvm/Target/TargetOptions.h" 40#include "llvm/Support/CommandLine.h" 41#include "llvm/Support/Debug.h" 42#include "llvm/Support/ErrorHandling.h" 43#include "llvm/Support/raw_ostream.h" 44#include "llvm/Support/Timer.h" 45 46#include <queue> 47 48using namespace llvm; 49 50STATISTIC(NumGlobalSplits, "Number of split global live ranges"); 51STATISTIC(NumLocalSplits, "Number of split local live ranges"); 52STATISTIC(NumEvicted, "Number of interferences evicted"); 53 54static cl::opt<SplitEditor::ComplementSpillMode> 55SplitSpillMode("split-spill-mode", cl::Hidden, 56 cl::desc("Spill mode for splitting live ranges"), 57 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"), 58 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"), 59 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed"), 60 clEnumValEnd), 61 cl::init(SplitEditor::SM_Partition)); 62 63static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", 64 createGreedyRegisterAllocator); 65 66namespace { 67class RAGreedy : public MachineFunctionPass, 68 public RegAllocBase, 69 private LiveRangeEdit::Delegate { 70 71 // context 72 MachineFunction *MF; 73 74 // analyses 75 SlotIndexes *Indexes; 76 LiveStacks *LS; 77 MachineDominatorTree *DomTree; 78 MachineLoopInfo *Loops; 79 EdgeBundles *Bundles; 80 SpillPlacement *SpillPlacer; 81 LiveDebugVariables *DebugVars; 82 83 // state 84 std::auto_ptr<Spiller> SpillerInstance; 85 std::priority_queue<std::pair<unsigned, unsigned> > Queue; 86 unsigned NextCascade; 87 88 // Live ranges pass through a number of stages as we try to allocate them. 89 // Some of the stages may also create new live ranges: 90 // 91 // - Region splitting. 92 // - Per-block splitting. 93 // - Local splitting. 94 // - Spilling. 95 // 96 // Ranges produced by one of the stages skip the previous stages when they are 97 // dequeued. This improves performance because we can skip interference checks 98 // that are unlikely to give any results. It also guarantees that the live 99 // range splitting algorithm terminates, something that is otherwise hard to 100 // ensure. 101 enum LiveRangeStage { 102 /// Newly created live range that has never been queued. 103 RS_New, 104 105 /// Only attempt assignment and eviction. Then requeue as RS_Split. 106 RS_Assign, 107 108 /// Attempt live range splitting if assignment is impossible. 109 RS_Split, 110 111 /// Attempt more aggressive live range splitting that is guaranteed to make 112 /// progress. This is used for split products that may not be making 113 /// progress. 114 RS_Split2, 115 116 /// Live range will be spilled. No more splitting will be attempted. 117 RS_Spill, 118 119 /// There is nothing more we can do to this live range. Abort compilation 120 /// if it can't be assigned. 121 RS_Done 122 }; 123 124 static const char *const StageName[]; 125 126 // RegInfo - Keep additional information about each live range. 127 struct RegInfo { 128 LiveRangeStage Stage; 129 130 // Cascade - Eviction loop prevention. See canEvictInterference(). 131 unsigned Cascade; 132 133 RegInfo() : Stage(RS_New), Cascade(0) {} 134 }; 135 136 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo; 137 138 LiveRangeStage getStage(const LiveInterval &VirtReg) const { 139 return ExtraRegInfo[VirtReg.reg].Stage; 140 } 141 142 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { 143 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 144 ExtraRegInfo[VirtReg.reg].Stage = Stage; 145 } 146 147 template<typename Iterator> 148 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) { 149 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 150 for (;Begin != End; ++Begin) { 151 unsigned Reg = (*Begin)->reg; 152 if (ExtraRegInfo[Reg].Stage == RS_New) 153 ExtraRegInfo[Reg].Stage = NewStage; 154 } 155 } 156 157 /// Cost of evicting interference. 158 struct EvictionCost { 159 unsigned BrokenHints; ///< Total number of broken hints. 160 float MaxWeight; ///< Maximum spill weight evicted. 161 162 EvictionCost(unsigned B = 0) : BrokenHints(B), MaxWeight(0) {} 163 164 bool operator<(const EvictionCost &O) const { 165 if (BrokenHints != O.BrokenHints) 166 return BrokenHints < O.BrokenHints; 167 return MaxWeight < O.MaxWeight; 168 } 169 }; 170 171 // splitting state. 172 std::auto_ptr<SplitAnalysis> SA; 173 std::auto_ptr<SplitEditor> SE; 174 175 /// Cached per-block interference maps 176 InterferenceCache IntfCache; 177 178 /// All basic blocks where the current register has uses. 179 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints; 180 181 /// Global live range splitting candidate info. 182 struct GlobalSplitCandidate { 183 // Register intended for assignment, or 0. 184 unsigned PhysReg; 185 186 // SplitKit interval index for this candidate. 187 unsigned IntvIdx; 188 189 // Interference for PhysReg. 190 InterferenceCache::Cursor Intf; 191 192 // Bundles where this candidate should be live. 193 BitVector LiveBundles; 194 SmallVector<unsigned, 8> ActiveBlocks; 195 196 void reset(InterferenceCache &Cache, unsigned Reg) { 197 PhysReg = Reg; 198 IntvIdx = 0; 199 Intf.setPhysReg(Cache, Reg); 200 LiveBundles.clear(); 201 ActiveBlocks.clear(); 202 } 203 204 // Set B[i] = C for every live bundle where B[i] was NoCand. 205 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) { 206 unsigned Count = 0; 207 for (int i = LiveBundles.find_first(); i >= 0; 208 i = LiveBundles.find_next(i)) 209 if (B[i] == NoCand) { 210 B[i] = C; 211 Count++; 212 } 213 return Count; 214 } 215 }; 216 217 /// Candidate info for for each PhysReg in AllocationOrder. 218 /// This vector never shrinks, but grows to the size of the largest register 219 /// class. 220 SmallVector<GlobalSplitCandidate, 32> GlobalCand; 221 222 enum { NoCand = ~0u }; 223 224 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to 225 /// NoCand which indicates the stack interval. 226 SmallVector<unsigned, 32> BundleCand; 227 228public: 229 RAGreedy(); 230 231 /// Return the pass name. 232 virtual const char* getPassName() const { 233 return "Greedy Register Allocator"; 234 } 235 236 /// RAGreedy analysis usage. 237 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 238 virtual void releaseMemory(); 239 virtual Spiller &spiller() { return *SpillerInstance; } 240 virtual void enqueue(LiveInterval *LI); 241 virtual LiveInterval *dequeue(); 242 virtual unsigned selectOrSplit(LiveInterval&, 243 SmallVectorImpl<LiveInterval*>&); 244 245 /// Perform register allocation. 246 virtual bool runOnMachineFunction(MachineFunction &mf); 247 248 static char ID; 249 250private: 251 bool LRE_CanEraseVirtReg(unsigned); 252 void LRE_WillShrinkVirtReg(unsigned); 253 void LRE_DidCloneVirtReg(unsigned, unsigned); 254 255 float calcSpillCost(); 256 bool addSplitConstraints(InterferenceCache::Cursor, float&); 257 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>); 258 void growRegion(GlobalSplitCandidate &Cand); 259 float calcGlobalSplitCost(GlobalSplitCandidate&); 260 bool calcCompactRegion(GlobalSplitCandidate&); 261 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>); 262 void calcGapWeights(unsigned, SmallVectorImpl<float>&); 263 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool); 264 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&); 265 void evictInterference(LiveInterval&, unsigned, 266 SmallVectorImpl<LiveInterval*>&); 267 268 unsigned tryAssign(LiveInterval&, AllocationOrder&, 269 SmallVectorImpl<LiveInterval*>&); 270 unsigned tryEvict(LiveInterval&, AllocationOrder&, 271 SmallVectorImpl<LiveInterval*>&, unsigned = ~0u); 272 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&, 273 SmallVectorImpl<LiveInterval*>&); 274 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&, 275 SmallVectorImpl<LiveInterval*>&); 276 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&, 277 SmallVectorImpl<LiveInterval*>&); 278 unsigned trySplit(LiveInterval&, AllocationOrder&, 279 SmallVectorImpl<LiveInterval*>&); 280}; 281} // end anonymous namespace 282 283char RAGreedy::ID = 0; 284 285#ifndef NDEBUG 286const char *const RAGreedy::StageName[] = { 287 "RS_New", 288 "RS_Assign", 289 "RS_Split", 290 "RS_Split2", 291 "RS_Spill", 292 "RS_Done" 293}; 294#endif 295 296// Hysteresis to use when comparing floats. 297// This helps stabilize decisions based on float comparisons. 298const float Hysteresis = 0.98f; 299 300 301FunctionPass* llvm::createGreedyRegisterAllocator() { 302 return new RAGreedy(); 303} 304 305RAGreedy::RAGreedy(): MachineFunctionPass(ID) { 306 initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry()); 307 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 308 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); 309 initializeSlotIndexesPass(*PassRegistry::getPassRegistry()); 310 initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry()); 311 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry()); 312 initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); 313 initializeLiveStacksPass(*PassRegistry::getPassRegistry()); 314 initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); 315 initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); 316 initializeVirtRegMapPass(*PassRegistry::getPassRegistry()); 317 initializeEdgeBundlesPass(*PassRegistry::getPassRegistry()); 318 initializeSpillPlacementPass(*PassRegistry::getPassRegistry()); 319} 320 321void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const { 322 AU.setPreservesCFG(); 323 AU.addRequired<AliasAnalysis>(); 324 AU.addPreserved<AliasAnalysis>(); 325 AU.addRequired<LiveIntervals>(); 326 AU.addRequired<SlotIndexes>(); 327 AU.addPreserved<SlotIndexes>(); 328 AU.addRequired<LiveDebugVariables>(); 329 AU.addPreserved<LiveDebugVariables>(); 330 if (StrongPHIElim) 331 AU.addRequiredID(StrongPHIEliminationID); 332 AU.addRequiredTransitiveID(RegisterCoalescerPassID); 333 AU.addRequired<CalculateSpillWeights>(); 334 AU.addRequired<LiveStacks>(); 335 AU.addPreserved<LiveStacks>(); 336 AU.addRequired<MachineDominatorTree>(); 337 AU.addPreserved<MachineDominatorTree>(); 338 AU.addRequired<MachineLoopInfo>(); 339 AU.addPreserved<MachineLoopInfo>(); 340 AU.addRequired<VirtRegMap>(); 341 AU.addPreserved<VirtRegMap>(); 342 AU.addRequired<EdgeBundles>(); 343 AU.addRequired<SpillPlacement>(); 344 MachineFunctionPass::getAnalysisUsage(AU); 345} 346 347 348//===----------------------------------------------------------------------===// 349// LiveRangeEdit delegate methods 350//===----------------------------------------------------------------------===// 351 352bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { 353 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { 354 unassign(LIS->getInterval(VirtReg), PhysReg); 355 return true; 356 } 357 // Unassigned virtreg is probably in the priority queue. 358 // RegAllocBase will erase it after dequeueing. 359 return false; 360} 361 362void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { 363 unsigned PhysReg = VRM->getPhys(VirtReg); 364 if (!PhysReg) 365 return; 366 367 // Register is assigned, put it back on the queue for reassignment. 368 LiveInterval &LI = LIS->getInterval(VirtReg); 369 unassign(LI, PhysReg); 370 enqueue(&LI); 371} 372 373void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) { 374 // Cloning a register we haven't even heard about yet? Just ignore it. 375 if (!ExtraRegInfo.inBounds(Old)) 376 return; 377 378 // LRE may clone a virtual register because dead code elimination causes it to 379 // be split into connected components. The new components are much smaller 380 // than the original, so they should get a new chance at being assigned. 381 // same stage as the parent. 382 ExtraRegInfo[Old].Stage = RS_Assign; 383 ExtraRegInfo.grow(New); 384 ExtraRegInfo[New] = ExtraRegInfo[Old]; 385} 386 387void RAGreedy::releaseMemory() { 388 SpillerInstance.reset(0); 389 ExtraRegInfo.clear(); 390 GlobalCand.clear(); 391 RegAllocBase::releaseMemory(); 392} 393 394void RAGreedy::enqueue(LiveInterval *LI) { 395 // Prioritize live ranges by size, assigning larger ranges first. 396 // The queue holds (size, reg) pairs. 397 const unsigned Size = LI->getSize(); 398 const unsigned Reg = LI->reg; 399 assert(TargetRegisterInfo::isVirtualRegister(Reg) && 400 "Can only enqueue virtual registers"); 401 unsigned Prio; 402 403 ExtraRegInfo.grow(Reg); 404 if (ExtraRegInfo[Reg].Stage == RS_New) 405 ExtraRegInfo[Reg].Stage = RS_Assign; 406 407 if (ExtraRegInfo[Reg].Stage == RS_Split) { 408 // Unsplit ranges that couldn't be allocated immediately are deferred until 409 // everything else has been allocated. 410 Prio = Size; 411 } else { 412 // Everything is allocated in long->short order. Long ranges that don't fit 413 // should be spilled (or split) ASAP so they don't create interference. 414 Prio = (1u << 31) + Size; 415 416 // Boost ranges that have a physical register hint. 417 if (TargetRegisterInfo::isPhysicalRegister(VRM->getRegAllocPref(Reg))) 418 Prio |= (1u << 30); 419 } 420 421 Queue.push(std::make_pair(Prio, Reg)); 422} 423 424LiveInterval *RAGreedy::dequeue() { 425 if (Queue.empty()) 426 return 0; 427 LiveInterval *LI = &LIS->getInterval(Queue.top().second); 428 Queue.pop(); 429 return LI; 430} 431 432 433//===----------------------------------------------------------------------===// 434// Direct Assignment 435//===----------------------------------------------------------------------===// 436 437/// tryAssign - Try to assign VirtReg to an available register. 438unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, 439 AllocationOrder &Order, 440 SmallVectorImpl<LiveInterval*> &NewVRegs) { 441 Order.rewind(); 442 unsigned PhysReg; 443 while ((PhysReg = Order.next())) 444 if (!checkPhysRegInterference(VirtReg, PhysReg)) 445 break; 446 if (!PhysReg || Order.isHint(PhysReg)) 447 return PhysReg; 448 449 // PhysReg is available, but there may be a better choice. 450 451 // If we missed a simple hint, try to cheaply evict interference from the 452 // preferred register. 453 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg)) 454 if (Order.isHint(Hint)) { 455 DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n'); 456 EvictionCost MaxCost(1); 457 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) { 458 evictInterference(VirtReg, Hint, NewVRegs); 459 return Hint; 460 } 461 } 462 463 // Try to evict interference from a cheaper alternative. 464 unsigned Cost = TRI->getCostPerUse(PhysReg); 465 466 // Most registers have 0 additional cost. 467 if (!Cost) 468 return PhysReg; 469 470 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost 471 << '\n'); 472 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost); 473 return CheapReg ? CheapReg : PhysReg; 474} 475 476 477//===----------------------------------------------------------------------===// 478// Interference eviction 479//===----------------------------------------------------------------------===// 480 481/// shouldEvict - determine if A should evict the assigned live range B. The 482/// eviction policy defined by this function together with the allocation order 483/// defined by enqueue() decides which registers ultimately end up being split 484/// and spilled. 485/// 486/// Cascade numbers are used to prevent infinite loops if this function is a 487/// cyclic relation. 488/// 489/// @param A The live range to be assigned. 490/// @param IsHint True when A is about to be assigned to its preferred 491/// register. 492/// @param B The live range to be evicted. 493/// @param BreaksHint True when B is already assigned to its preferred register. 494bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint, 495 LiveInterval &B, bool BreaksHint) { 496 bool CanSplit = getStage(B) < RS_Spill; 497 498 // Be fairly aggressive about following hints as long as the evictee can be 499 // split. 500 if (CanSplit && IsHint && !BreaksHint) 501 return true; 502 503 return A.weight > B.weight; 504} 505 506/// canEvictInterference - Return true if all interferences between VirtReg and 507/// PhysReg can be evicted. When OnlyCheap is set, don't do anything 508/// 509/// @param VirtReg Live range that is about to be assigned. 510/// @param PhysReg Desired register for assignment. 511/// @prarm IsHint True when PhysReg is VirtReg's preferred register. 512/// @param MaxCost Only look for cheaper candidates and update with new cost 513/// when returning true. 514/// @returns True when interference can be evicted cheaper than MaxCost. 515bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, 516 bool IsHint, EvictionCost &MaxCost) { 517 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never 518 // involved in an eviction before. If a cascade number was assigned, deny 519 // evicting anything with the same or a newer cascade number. This prevents 520 // infinite eviction loops. 521 // 522 // This works out so a register without a cascade number is allowed to evict 523 // anything, and it can be evicted by anything. 524 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; 525 if (!Cascade) 526 Cascade = NextCascade; 527 528 EvictionCost Cost; 529 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { 530 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); 531 // If there is 10 or more interferences, chances are one is heavier. 532 if (Q.collectInterferingVRegs(10) >= 10) 533 return false; 534 535 // Check if any interfering live range is heavier than MaxWeight. 536 for (unsigned i = Q.interferingVRegs().size(); i; --i) { 537 LiveInterval *Intf = Q.interferingVRegs()[i - 1]; 538 if (TargetRegisterInfo::isPhysicalRegister(Intf->reg)) 539 return false; 540 // Never evict spill products. They cannot split or spill. 541 if (getStage(*Intf) == RS_Done) 542 return false; 543 // Once a live range becomes small enough, it is urgent that we find a 544 // register for it. This is indicated by an infinite spill weight. These 545 // urgent live ranges get to evict almost anything. 546 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable(); 547 // Only evict older cascades or live ranges without a cascade. 548 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade; 549 if (Cascade <= IntfCascade) { 550 if (!Urgent) 551 return false; 552 // We permit breaking cascades for urgent evictions. It should be the 553 // last resort, though, so make it really expensive. 554 Cost.BrokenHints += 10; 555 } 556 // Would this break a satisfied hint? 557 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg); 558 // Update eviction cost. 559 Cost.BrokenHints += BreaksHint; 560 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight); 561 // Abort if this would be too expensive. 562 if (!(Cost < MaxCost)) 563 return false; 564 // Finally, apply the eviction policy for non-urgent evictions. 565 if (!Urgent && !shouldEvict(VirtReg, IsHint, *Intf, BreaksHint)) 566 return false; 567 } 568 } 569 MaxCost = Cost; 570 return true; 571} 572 573/// evictInterference - Evict any interferring registers that prevent VirtReg 574/// from being assigned to Physreg. This assumes that canEvictInterference 575/// returned true. 576void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, 577 SmallVectorImpl<LiveInterval*> &NewVRegs) { 578 // Make sure that VirtReg has a cascade number, and assign that cascade 579 // number to every evicted register. These live ranges than then only be 580 // evicted by a newer cascade, preventing infinite loops. 581 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade; 582 if (!Cascade) 583 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++; 584 585 DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI) 586 << " interference: Cascade " << Cascade << '\n'); 587 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { 588 LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); 589 assert(Q.seenAllInterferences() && "Didn't check all interfererences."); 590 for (unsigned i = 0, e = Q.interferingVRegs().size(); i != e; ++i) { 591 LiveInterval *Intf = Q.interferingVRegs()[i]; 592 unassign(*Intf, VRM->getPhys(Intf->reg)); 593 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade || 594 VirtReg.isSpillable() < Intf->isSpillable()) && 595 "Cannot decrease cascade number, illegal eviction"); 596 ExtraRegInfo[Intf->reg].Cascade = Cascade; 597 ++NumEvicted; 598 NewVRegs.push_back(Intf); 599 } 600 } 601} 602 603/// tryEvict - Try to evict all interferences for a physreg. 604/// @param VirtReg Currently unassigned virtual register. 605/// @param Order Physregs to try. 606/// @return Physreg to assign VirtReg, or 0. 607unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, 608 AllocationOrder &Order, 609 SmallVectorImpl<LiveInterval*> &NewVRegs, 610 unsigned CostPerUseLimit) { 611 NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled); 612 613 // Keep track of the cheapest interference seen so far. 614 EvictionCost BestCost(~0u); 615 unsigned BestPhys = 0; 616 617 // When we are just looking for a reduced cost per use, don't break any 618 // hints, and only evict smaller spill weights. 619 if (CostPerUseLimit < ~0u) { 620 BestCost.BrokenHints = 0; 621 BestCost.MaxWeight = VirtReg.weight; 622 } 623 624 Order.rewind(); 625 while (unsigned PhysReg = Order.next()) { 626 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit) 627 continue; 628 // The first use of a callee-saved register in a function has cost 1. 629 // Don't start using a CSR when the CostPerUseLimit is low. 630 if (CostPerUseLimit == 1) 631 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) 632 if (!MRI->isPhysRegUsed(CSR)) { 633 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " 634 << PrintReg(CSR, TRI) << '\n'); 635 continue; 636 } 637 638 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) 639 continue; 640 641 // Best so far. 642 BestPhys = PhysReg; 643 644 // Stop if the hint can be used. 645 if (Order.isHint(PhysReg)) 646 break; 647 } 648 649 if (!BestPhys) 650 return 0; 651 652 evictInterference(VirtReg, BestPhys, NewVRegs); 653 return BestPhys; 654} 655 656 657//===----------------------------------------------------------------------===// 658// Region Splitting 659//===----------------------------------------------------------------------===// 660 661/// addSplitConstraints - Fill out the SplitConstraints vector based on the 662/// interference pattern in Physreg and its aliases. Add the constraints to 663/// SpillPlacement and return the static cost of this split in Cost, assuming 664/// that all preferences in SplitConstraints are met. 665/// Return false if there are no bundles with positive bias. 666bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf, 667 float &Cost) { 668 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 669 670 // Reset interference dependent info. 671 SplitConstraints.resize(UseBlocks.size()); 672 float StaticCost = 0; 673 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 674 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 675 SpillPlacement::BlockConstraint &BC = SplitConstraints[i]; 676 677 BC.Number = BI.MBB->getNumber(); 678 Intf.moveToBlock(BC.Number); 679 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; 680 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare; 681 BC.ChangesValue = BI.FirstDef; 682 683 if (!Intf.hasInterference()) 684 continue; 685 686 // Number of spill code instructions to insert. 687 unsigned Ins = 0; 688 689 // Interference for the live-in value. 690 if (BI.LiveIn) { 691 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) 692 BC.Entry = SpillPlacement::MustSpill, ++Ins; 693 else if (Intf.first() < BI.FirstInstr) 694 BC.Entry = SpillPlacement::PrefSpill, ++Ins; 695 else if (Intf.first() < BI.LastInstr) 696 ++Ins; 697 } 698 699 // Interference for the live-out value. 700 if (BI.LiveOut) { 701 if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) 702 BC.Exit = SpillPlacement::MustSpill, ++Ins; 703 else if (Intf.last() > BI.LastInstr) 704 BC.Exit = SpillPlacement::PrefSpill, ++Ins; 705 else if (Intf.last() > BI.FirstInstr) 706 ++Ins; 707 } 708 709 // Accumulate the total frequency of inserted spill code. 710 if (Ins) 711 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number); 712 } 713 Cost = StaticCost; 714 715 // Add constraints for use-blocks. Note that these are the only constraints 716 // that may add a positive bias, it is downhill from here. 717 SpillPlacer->addConstraints(SplitConstraints); 718 return SpillPlacer->scanActiveBundles(); 719} 720 721 722/// addThroughConstraints - Add constraints and links to SpillPlacer from the 723/// live-through blocks in Blocks. 724void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf, 725 ArrayRef<unsigned> Blocks) { 726 const unsigned GroupSize = 8; 727 SpillPlacement::BlockConstraint BCS[GroupSize]; 728 unsigned TBS[GroupSize]; 729 unsigned B = 0, T = 0; 730 731 for (unsigned i = 0; i != Blocks.size(); ++i) { 732 unsigned Number = Blocks[i]; 733 Intf.moveToBlock(Number); 734 735 if (!Intf.hasInterference()) { 736 assert(T < GroupSize && "Array overflow"); 737 TBS[T] = Number; 738 if (++T == GroupSize) { 739 SpillPlacer->addLinks(makeArrayRef(TBS, T)); 740 T = 0; 741 } 742 continue; 743 } 744 745 assert(B < GroupSize && "Array overflow"); 746 BCS[B].Number = Number; 747 748 // Interference for the live-in value. 749 if (Intf.first() <= Indexes->getMBBStartIdx(Number)) 750 BCS[B].Entry = SpillPlacement::MustSpill; 751 else 752 BCS[B].Entry = SpillPlacement::PrefSpill; 753 754 // Interference for the live-out value. 755 if (Intf.last() >= SA->getLastSplitPoint(Number)) 756 BCS[B].Exit = SpillPlacement::MustSpill; 757 else 758 BCS[B].Exit = SpillPlacement::PrefSpill; 759 760 if (++B == GroupSize) { 761 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B); 762 SpillPlacer->addConstraints(Array); 763 B = 0; 764 } 765 } 766 767 ArrayRef<SpillPlacement::BlockConstraint> Array(BCS, B); 768 SpillPlacer->addConstraints(Array); 769 SpillPlacer->addLinks(makeArrayRef(TBS, T)); 770} 771 772void RAGreedy::growRegion(GlobalSplitCandidate &Cand) { 773 // Keep track of through blocks that have not been added to SpillPlacer. 774 BitVector Todo = SA->getThroughBlocks(); 775 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks; 776 unsigned AddedTo = 0; 777#ifndef NDEBUG 778 unsigned Visited = 0; 779#endif 780 781 for (;;) { 782 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive(); 783 // Find new through blocks in the periphery of PrefRegBundles. 784 for (int i = 0, e = NewBundles.size(); i != e; ++i) { 785 unsigned Bundle = NewBundles[i]; 786 // Look at all blocks connected to Bundle in the full graph. 787 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle); 788 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end(); 789 I != E; ++I) { 790 unsigned Block = *I; 791 if (!Todo.test(Block)) 792 continue; 793 Todo.reset(Block); 794 // This is a new through block. Add it to SpillPlacer later. 795 ActiveBlocks.push_back(Block); 796#ifndef NDEBUG 797 ++Visited; 798#endif 799 } 800 } 801 // Any new blocks to add? 802 if (ActiveBlocks.size() == AddedTo) 803 break; 804 805 // Compute through constraints from the interference, or assume that all 806 // through blocks prefer spilling when forming compact regions. 807 ArrayRef<unsigned> NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo); 808 if (Cand.PhysReg) 809 addThroughConstraints(Cand.Intf, NewBlocks); 810 else 811 // Provide a strong negative bias on through blocks to prevent unwanted 812 // liveness on loop backedges. 813 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true); 814 AddedTo = ActiveBlocks.size(); 815 816 // Perhaps iterating can enable more bundles? 817 SpillPlacer->iterate(); 818 } 819 DEBUG(dbgs() << ", v=" << Visited); 820} 821 822/// calcCompactRegion - Compute the set of edge bundles that should be live 823/// when splitting the current live range into compact regions. Compact 824/// regions can be computed without looking at interference. They are the 825/// regions formed by removing all the live-through blocks from the live range. 826/// 827/// Returns false if the current live range is already compact, or if the 828/// compact regions would form single block regions anyway. 829bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) { 830 // Without any through blocks, the live range is already compact. 831 if (!SA->getNumThroughBlocks()) 832 return false; 833 834 // Compact regions don't correspond to any physreg. 835 Cand.reset(IntfCache, 0); 836 837 DEBUG(dbgs() << "Compact region bundles"); 838 839 // Use the spill placer to determine the live bundles. GrowRegion pretends 840 // that all the through blocks have interference when PhysReg is unset. 841 SpillPlacer->prepare(Cand.LiveBundles); 842 843 // The static split cost will be zero since Cand.Intf reports no interference. 844 float Cost; 845 if (!addSplitConstraints(Cand.Intf, Cost)) { 846 DEBUG(dbgs() << ", none.\n"); 847 return false; 848 } 849 850 growRegion(Cand); 851 SpillPlacer->finish(); 852 853 if (!Cand.LiveBundles.any()) { 854 DEBUG(dbgs() << ", none.\n"); 855 return false; 856 } 857 858 DEBUG({ 859 for (int i = Cand.LiveBundles.find_first(); i>=0; 860 i = Cand.LiveBundles.find_next(i)) 861 dbgs() << " EB#" << i; 862 dbgs() << ".\n"; 863 }); 864 return true; 865} 866 867/// calcSpillCost - Compute how expensive it would be to split the live range in 868/// SA around all use blocks instead of forming bundle regions. 869float RAGreedy::calcSpillCost() { 870 float Cost = 0; 871 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 872 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 873 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 874 unsigned Number = BI.MBB->getNumber(); 875 // We normally only need one spill instruction - a load or a store. 876 Cost += SpillPlacer->getBlockFrequency(Number); 877 878 // Unless the value is redefined in the block. 879 if (BI.LiveIn && BI.LiveOut && BI.FirstDef) 880 Cost += SpillPlacer->getBlockFrequency(Number); 881 } 882 return Cost; 883} 884 885/// calcGlobalSplitCost - Return the global split cost of following the split 886/// pattern in LiveBundles. This cost should be added to the local cost of the 887/// interference pattern in SplitConstraints. 888/// 889float RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand) { 890 float GlobalCost = 0; 891 const BitVector &LiveBundles = Cand.LiveBundles; 892 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 893 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 894 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 895 SpillPlacement::BlockConstraint &BC = SplitConstraints[i]; 896 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, 0)]; 897 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, 1)]; 898 unsigned Ins = 0; 899 900 if (BI.LiveIn) 901 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg); 902 if (BI.LiveOut) 903 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg); 904 if (Ins) 905 GlobalCost += Ins * SpillPlacer->getBlockFrequency(BC.Number); 906 } 907 908 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { 909 unsigned Number = Cand.ActiveBlocks[i]; 910 bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; 911 bool RegOut = LiveBundles[Bundles->getBundle(Number, 1)]; 912 if (!RegIn && !RegOut) 913 continue; 914 if (RegIn && RegOut) { 915 // We need double spill code if this block has interference. 916 Cand.Intf.moveToBlock(Number); 917 if (Cand.Intf.hasInterference()) 918 GlobalCost += 2*SpillPlacer->getBlockFrequency(Number); 919 continue; 920 } 921 // live-in / stack-out or stack-in live-out. 922 GlobalCost += SpillPlacer->getBlockFrequency(Number); 923 } 924 return GlobalCost; 925} 926 927/// splitAroundRegion - Split the current live range around the regions 928/// determined by BundleCand and GlobalCand. 929/// 930/// Before calling this function, GlobalCand and BundleCand must be initialized 931/// so each bundle is assigned to a valid candidate, or NoCand for the 932/// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor 933/// objects must be initialized for the current live range, and intervals 934/// created for the used candidates. 935/// 936/// @param LREdit The LiveRangeEdit object handling the current split. 937/// @param UsedCands List of used GlobalCand entries. Every BundleCand value 938/// must appear in this list. 939void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit, 940 ArrayRef<unsigned> UsedCands) { 941 // These are the intervals created for new global ranges. We may create more 942 // intervals for local ranges. 943 const unsigned NumGlobalIntvs = LREdit.size(); 944 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n"); 945 assert(NumGlobalIntvs && "No global intervals configured"); 946 947 // Isolate even single instructions when dealing with a proper sub-class. 948 // That guarantees register class inflation for the stack interval because it 949 // is all copies. 950 unsigned Reg = SA->getParent().reg; 951 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); 952 953 // First handle all the blocks with uses. 954 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 955 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 956 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 957 unsigned Number = BI.MBB->getNumber(); 958 unsigned IntvIn = 0, IntvOut = 0; 959 SlotIndex IntfIn, IntfOut; 960 if (BI.LiveIn) { 961 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)]; 962 if (CandIn != NoCand) { 963 GlobalSplitCandidate &Cand = GlobalCand[CandIn]; 964 IntvIn = Cand.IntvIdx; 965 Cand.Intf.moveToBlock(Number); 966 IntfIn = Cand.Intf.first(); 967 } 968 } 969 if (BI.LiveOut) { 970 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)]; 971 if (CandOut != NoCand) { 972 GlobalSplitCandidate &Cand = GlobalCand[CandOut]; 973 IntvOut = Cand.IntvIdx; 974 Cand.Intf.moveToBlock(Number); 975 IntfOut = Cand.Intf.last(); 976 } 977 } 978 979 // Create separate intervals for isolated blocks with multiple uses. 980 if (!IntvIn && !IntvOut) { 981 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); 982 if (SA->shouldSplitSingleBlock(BI, SingleInstrs)) 983 SE->splitSingleBlock(BI); 984 continue; 985 } 986 987 if (IntvIn && IntvOut) 988 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut); 989 else if (IntvIn) 990 SE->splitRegInBlock(BI, IntvIn, IntfIn); 991 else 992 SE->splitRegOutBlock(BI, IntvOut, IntfOut); 993 } 994 995 // Handle live-through blocks. The relevant live-through blocks are stored in 996 // the ActiveBlocks list with each candidate. We need to filter out 997 // duplicates. 998 BitVector Todo = SA->getThroughBlocks(); 999 for (unsigned c = 0; c != UsedCands.size(); ++c) { 1000 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks; 1001 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) { 1002 unsigned Number = Blocks[i]; 1003 if (!Todo.test(Number)) 1004 continue; 1005 Todo.reset(Number); 1006 1007 unsigned IntvIn = 0, IntvOut = 0; 1008 SlotIndex IntfIn, IntfOut; 1009 1010 unsigned CandIn = BundleCand[Bundles->getBundle(Number, 0)]; 1011 if (CandIn != NoCand) { 1012 GlobalSplitCandidate &Cand = GlobalCand[CandIn]; 1013 IntvIn = Cand.IntvIdx; 1014 Cand.Intf.moveToBlock(Number); 1015 IntfIn = Cand.Intf.first(); 1016 } 1017 1018 unsigned CandOut = BundleCand[Bundles->getBundle(Number, 1)]; 1019 if (CandOut != NoCand) { 1020 GlobalSplitCandidate &Cand = GlobalCand[CandOut]; 1021 IntvOut = Cand.IntvIdx; 1022 Cand.Intf.moveToBlock(Number); 1023 IntfOut = Cand.Intf.last(); 1024 } 1025 if (!IntvIn && !IntvOut) 1026 continue; 1027 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut); 1028 } 1029 } 1030 1031 ++NumGlobalSplits; 1032 1033 SmallVector<unsigned, 8> IntvMap; 1034 SE->finish(&IntvMap); 1035 DebugVars->splitRegister(Reg, LREdit.regs()); 1036 1037 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 1038 unsigned OrigBlocks = SA->getNumLiveBlocks(); 1039 1040 // Sort out the new intervals created by splitting. We get four kinds: 1041 // - Remainder intervals should not be split again. 1042 // - Candidate intervals can be assigned to Cand.PhysReg. 1043 // - Block-local splits are candidates for local splitting. 1044 // - DCE leftovers should go back on the queue. 1045 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) { 1046 LiveInterval &Reg = *LREdit.get(i); 1047 1048 // Ignore old intervals from DCE. 1049 if (getStage(Reg) != RS_New) 1050 continue; 1051 1052 // Remainder interval. Don't try splitting again, spill if it doesn't 1053 // allocate. 1054 if (IntvMap[i] == 0) { 1055 setStage(Reg, RS_Spill); 1056 continue; 1057 } 1058 1059 // Global intervals. Allow repeated splitting as long as the number of live 1060 // blocks is strictly decreasing. 1061 if (IntvMap[i] < NumGlobalIntvs) { 1062 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) { 1063 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks 1064 << " blocks as original.\n"); 1065 // Don't allow repeated splitting as a safe guard against looping. 1066 setStage(Reg, RS_Split2); 1067 } 1068 continue; 1069 } 1070 1071 // Other intervals are treated as new. This includes local intervals created 1072 // for blocks with multiple uses, and anything created by DCE. 1073 } 1074 1075 if (VerifyEnabled) 1076 MF->verify(this, "After splitting live range around region"); 1077} 1078 1079unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, 1080 SmallVectorImpl<LiveInterval*> &NewVRegs) { 1081 unsigned NumCands = 0; 1082 unsigned BestCand = NoCand; 1083 float BestCost; 1084 SmallVector<unsigned, 8> UsedCands; 1085 1086 // Check if we can split this live range around a compact region. 1087 bool HasCompact = calcCompactRegion(GlobalCand.front()); 1088 if (HasCompact) { 1089 // Yes, keep GlobalCand[0] as the compact region candidate. 1090 NumCands = 1; 1091 BestCost = HUGE_VALF; 1092 } else { 1093 // No benefit from the compact region, our fallback will be per-block 1094 // splitting. Make sure we find a solution that is cheaper than spilling. 1095 BestCost = Hysteresis * calcSpillCost(); 1096 DEBUG(dbgs() << "Cost of isolating all blocks = " << BestCost << '\n'); 1097 } 1098 1099 Order.rewind(); 1100 while (unsigned PhysReg = Order.next()) { 1101 // Discard bad candidates before we run out of interference cache cursors. 1102 // This will only affect register classes with a lot of registers (>32). 1103 if (NumCands == IntfCache.getMaxCursors()) { 1104 unsigned WorstCount = ~0u; 1105 unsigned Worst = 0; 1106 for (unsigned i = 0; i != NumCands; ++i) { 1107 if (i == BestCand || !GlobalCand[i].PhysReg) 1108 continue; 1109 unsigned Count = GlobalCand[i].LiveBundles.count(); 1110 if (Count < WorstCount) 1111 Worst = i, WorstCount = Count; 1112 } 1113 --NumCands; 1114 GlobalCand[Worst] = GlobalCand[NumCands]; 1115 if (BestCand == NumCands) 1116 BestCand = Worst; 1117 } 1118 1119 if (GlobalCand.size() <= NumCands) 1120 GlobalCand.resize(NumCands+1); 1121 GlobalSplitCandidate &Cand = GlobalCand[NumCands]; 1122 Cand.reset(IntfCache, PhysReg); 1123 1124 SpillPlacer->prepare(Cand.LiveBundles); 1125 float Cost; 1126 if (!addSplitConstraints(Cand.Intf, Cost)) { 1127 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n"); 1128 continue; 1129 } 1130 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = " << Cost); 1131 if (Cost >= BestCost) { 1132 DEBUG({ 1133 if (BestCand == NoCand) 1134 dbgs() << " worse than no bundles\n"; 1135 else 1136 dbgs() << " worse than " 1137 << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; 1138 }); 1139 continue; 1140 } 1141 growRegion(Cand); 1142 1143 SpillPlacer->finish(); 1144 1145 // No live bundles, defer to splitSingleBlocks(). 1146 if (!Cand.LiveBundles.any()) { 1147 DEBUG(dbgs() << " no bundles.\n"); 1148 continue; 1149 } 1150 1151 Cost += calcGlobalSplitCost(Cand); 1152 DEBUG({ 1153 dbgs() << ", total = " << Cost << " with bundles"; 1154 for (int i = Cand.LiveBundles.find_first(); i>=0; 1155 i = Cand.LiveBundles.find_next(i)) 1156 dbgs() << " EB#" << i; 1157 dbgs() << ".\n"; 1158 }); 1159 if (Cost < BestCost) { 1160 BestCand = NumCands; 1161 BestCost = Hysteresis * Cost; // Prevent rounding effects. 1162 } 1163 ++NumCands; 1164 } 1165 1166 // No solutions found, fall back to single block splitting. 1167 if (!HasCompact && BestCand == NoCand) 1168 return 0; 1169 1170 // Prepare split editor. 1171 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); 1172 SE->reset(LREdit, SplitSpillMode); 1173 1174 // Assign all edge bundles to the preferred candidate, or NoCand. 1175 BundleCand.assign(Bundles->getNumBundles(), NoCand); 1176 1177 // Assign bundles for the best candidate region. 1178 if (BestCand != NoCand) { 1179 GlobalSplitCandidate &Cand = GlobalCand[BestCand]; 1180 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) { 1181 UsedCands.push_back(BestCand); 1182 Cand.IntvIdx = SE->openIntv(); 1183 DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in " 1184 << B << " bundles, intv " << Cand.IntvIdx << ".\n"); 1185 (void)B; 1186 } 1187 } 1188 1189 // Assign bundles for the compact region. 1190 if (HasCompact) { 1191 GlobalSplitCandidate &Cand = GlobalCand.front(); 1192 assert(!Cand.PhysReg && "Compact region has no physreg"); 1193 if (unsigned B = Cand.getBundles(BundleCand, 0)) { 1194 UsedCands.push_back(0); 1195 Cand.IntvIdx = SE->openIntv(); 1196 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv " 1197 << Cand.IntvIdx << ".\n"); 1198 (void)B; 1199 } 1200 } 1201 1202 splitAroundRegion(LREdit, UsedCands); 1203 return 0; 1204} 1205 1206 1207//===----------------------------------------------------------------------===// 1208// Per-Block Splitting 1209//===----------------------------------------------------------------------===// 1210 1211/// tryBlockSplit - Split a global live range around every block with uses. This 1212/// creates a lot of local live ranges, that will be split by tryLocalSplit if 1213/// they don't allocate. 1214unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, 1215 SmallVectorImpl<LiveInterval*> &NewVRegs) { 1216 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed"); 1217 unsigned Reg = VirtReg.reg; 1218 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)); 1219 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); 1220 SE->reset(LREdit, SplitSpillMode); 1221 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks(); 1222 for (unsigned i = 0; i != UseBlocks.size(); ++i) { 1223 const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; 1224 if (SA->shouldSplitSingleBlock(BI, SingleInstrs)) 1225 SE->splitSingleBlock(BI); 1226 } 1227 // No blocks were split. 1228 if (LREdit.empty()) 1229 return 0; 1230 1231 // We did split for some blocks. 1232 SmallVector<unsigned, 8> IntvMap; 1233 SE->finish(&IntvMap); 1234 1235 // Tell LiveDebugVariables about the new ranges. 1236 DebugVars->splitRegister(Reg, LREdit.regs()); 1237 1238 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 1239 1240 // Sort out the new intervals created by splitting. The remainder interval 1241 // goes straight to spilling, the new local ranges get to stay RS_New. 1242 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) { 1243 LiveInterval &LI = *LREdit.get(i); 1244 if (getStage(LI) == RS_New && IntvMap[i] == 0) 1245 setStage(LI, RS_Spill); 1246 } 1247 1248 if (VerifyEnabled) 1249 MF->verify(this, "After splitting live range around basic blocks"); 1250 return 0; 1251} 1252 1253//===----------------------------------------------------------------------===// 1254// Local Splitting 1255//===----------------------------------------------------------------------===// 1256 1257 1258/// calcGapWeights - Compute the maximum spill weight that needs to be evicted 1259/// in order to use PhysReg between two entries in SA->UseSlots. 1260/// 1261/// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1]. 1262/// 1263void RAGreedy::calcGapWeights(unsigned PhysReg, 1264 SmallVectorImpl<float> &GapWeight) { 1265 assert(SA->getUseBlocks().size() == 1 && "Not a local interval"); 1266 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front(); 1267 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots; 1268 const unsigned NumGaps = Uses.size()-1; 1269 1270 // Start and end points for the interference check. 1271 SlotIndex StartIdx = 1272 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr; 1273 SlotIndex StopIdx = 1274 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr; 1275 1276 GapWeight.assign(NumGaps, 0.0f); 1277 1278 // Add interference from each overlapping register. 1279 for (const unsigned *AI = TRI->getOverlaps(PhysReg); *AI; ++AI) { 1280 if (!query(const_cast<LiveInterval&>(SA->getParent()), *AI) 1281 .checkInterference()) 1282 continue; 1283 1284 // We know that VirtReg is a continuous interval from FirstInstr to 1285 // LastInstr, so we don't need InterferenceQuery. 1286 // 1287 // Interference that overlaps an instruction is counted in both gaps 1288 // surrounding the instruction. The exception is interference before 1289 // StartIdx and after StopIdx. 1290 // 1291 LiveIntervalUnion::SegmentIter IntI = getLiveUnion(*AI).find(StartIdx); 1292 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) { 1293 // Skip the gaps before IntI. 1294 while (Uses[Gap+1].getBoundaryIndex() < IntI.start()) 1295 if (++Gap == NumGaps) 1296 break; 1297 if (Gap == NumGaps) 1298 break; 1299 1300 // Update the gaps covered by IntI. 1301 const float weight = IntI.value()->weight; 1302 for (; Gap != NumGaps; ++Gap) { 1303 GapWeight[Gap] = std::max(GapWeight[Gap], weight); 1304 if (Uses[Gap+1].getBaseIndex() >= IntI.stop()) 1305 break; 1306 } 1307 if (Gap == NumGaps) 1308 break; 1309 } 1310 } 1311} 1312 1313/// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only 1314/// basic block. 1315/// 1316unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, 1317 SmallVectorImpl<LiveInterval*> &NewVRegs) { 1318 assert(SA->getUseBlocks().size() == 1 && "Not a local interval"); 1319 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front(); 1320 1321 // Note that it is possible to have an interval that is live-in or live-out 1322 // while only covering a single block - A phi-def can use undef values from 1323 // predecessors, and the block could be a single-block loop. 1324 // We don't bother doing anything clever about such a case, we simply assume 1325 // that the interval is continuous from FirstInstr to LastInstr. We should 1326 // make sure that we don't do anything illegal to such an interval, though. 1327 1328 const SmallVectorImpl<SlotIndex> &Uses = SA->UseSlots; 1329 if (Uses.size() <= 2) 1330 return 0; 1331 const unsigned NumGaps = Uses.size()-1; 1332 1333 DEBUG({ 1334 dbgs() << "tryLocalSplit: "; 1335 for (unsigned i = 0, e = Uses.size(); i != e; ++i) 1336 dbgs() << ' ' << SA->UseSlots[i]; 1337 dbgs() << '\n'; 1338 }); 1339 1340 // Since we allow local split results to be split again, there is a risk of 1341 // creating infinite loops. It is tempting to require that the new live 1342 // ranges have less instructions than the original. That would guarantee 1343 // convergence, but it is too strict. A live range with 3 instructions can be 1344 // split 2+3 (including the COPY), and we want to allow that. 1345 // 1346 // Instead we use these rules: 1347 // 1348 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the 1349 // noop split, of course). 1350 // 2. Require progress be made for ranges with getStage() == RS_Split2. All 1351 // the new ranges must have fewer instructions than before the split. 1352 // 3. New ranges with the same number of instructions are marked RS_Split2, 1353 // smaller ranges are marked RS_New. 1354 // 1355 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent 1356 // excessive splitting and infinite loops. 1357 // 1358 bool ProgressRequired = getStage(VirtReg) >= RS_Split2; 1359 1360 // Best split candidate. 1361 unsigned BestBefore = NumGaps; 1362 unsigned BestAfter = 0; 1363 float BestDiff = 0; 1364 1365 const float blockFreq = SpillPlacer->getBlockFrequency(BI.MBB->getNumber()); 1366 SmallVector<float, 8> GapWeight; 1367 1368 Order.rewind(); 1369 while (unsigned PhysReg = Order.next()) { 1370 // Keep track of the largest spill weight that would need to be evicted in 1371 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1]. 1372 calcGapWeights(PhysReg, GapWeight); 1373 1374 // Try to find the best sequence of gaps to close. 1375 // The new spill weight must be larger than any gap interference. 1376 1377 // We will split before Uses[SplitBefore] and after Uses[SplitAfter]. 1378 unsigned SplitBefore = 0, SplitAfter = 1; 1379 1380 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]). 1381 // It is the spill weight that needs to be evicted. 1382 float MaxGap = GapWeight[0]; 1383 1384 for (;;) { 1385 // Live before/after split? 1386 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn; 1387 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut; 1388 1389 DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' ' 1390 << Uses[SplitBefore] << '-' << Uses[SplitAfter] 1391 << " i=" << MaxGap); 1392 1393 // Stop before the interval gets so big we wouldn't be making progress. 1394 if (!LiveBefore && !LiveAfter) { 1395 DEBUG(dbgs() << " all\n"); 1396 break; 1397 } 1398 // Should the interval be extended or shrunk? 1399 bool Shrink = true; 1400 1401 // How many gaps would the new range have? 1402 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter; 1403 1404 // Legally, without causing looping? 1405 bool Legal = !ProgressRequired || NewGaps < NumGaps; 1406 1407 if (Legal && MaxGap < HUGE_VALF) { 1408 // Estimate the new spill weight. Each instruction reads or writes the 1409 // register. Conservatively assume there are no read-modify-write 1410 // instructions. 1411 // 1412 // Try to guess the size of the new interval. 1413 const float EstWeight = normalizeSpillWeight(blockFreq * (NewGaps + 1), 1414 Uses[SplitBefore].distance(Uses[SplitAfter]) + 1415 (LiveBefore + LiveAfter)*SlotIndex::InstrDist); 1416 // Would this split be possible to allocate? 1417 // Never allocate all gaps, we wouldn't be making progress. 1418 DEBUG(dbgs() << " w=" << EstWeight); 1419 if (EstWeight * Hysteresis >= MaxGap) { 1420 Shrink = false; 1421 float Diff = EstWeight - MaxGap; 1422 if (Diff > BestDiff) { 1423 DEBUG(dbgs() << " (best)"); 1424 BestDiff = Hysteresis * Diff; 1425 BestBefore = SplitBefore; 1426 BestAfter = SplitAfter; 1427 } 1428 } 1429 } 1430 1431 // Try to shrink. 1432 if (Shrink) { 1433 if (++SplitBefore < SplitAfter) { 1434 DEBUG(dbgs() << " shrink\n"); 1435 // Recompute the max when necessary. 1436 if (GapWeight[SplitBefore - 1] >= MaxGap) { 1437 MaxGap = GapWeight[SplitBefore]; 1438 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i) 1439 MaxGap = std::max(MaxGap, GapWeight[i]); 1440 } 1441 continue; 1442 } 1443 MaxGap = 0; 1444 } 1445 1446 // Try to extend the interval. 1447 if (SplitAfter >= NumGaps) { 1448 DEBUG(dbgs() << " end\n"); 1449 break; 1450 } 1451 1452 DEBUG(dbgs() << " extend\n"); 1453 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]); 1454 } 1455 } 1456 1457 // Didn't find any candidates? 1458 if (BestBefore == NumGaps) 1459 return 0; 1460 1461 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore] 1462 << '-' << Uses[BestAfter] << ", " << BestDiff 1463 << ", " << (BestAfter - BestBefore + 1) << " instrs\n"); 1464 1465 LiveRangeEdit LREdit(VirtReg, NewVRegs, this); 1466 SE->reset(LREdit); 1467 1468 SE->openIntv(); 1469 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]); 1470 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]); 1471 SE->useIntv(SegStart, SegStop); 1472 SmallVector<unsigned, 8> IntvMap; 1473 SE->finish(&IntvMap); 1474 DebugVars->splitRegister(VirtReg.reg, LREdit.regs()); 1475 1476 // If the new range has the same number of instructions as before, mark it as 1477 // RS_Split2 so the next split will be forced to make progress. Otherwise, 1478 // leave the new intervals as RS_New so they can compete. 1479 bool LiveBefore = BestBefore != 0 || BI.LiveIn; 1480 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut; 1481 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter; 1482 if (NewGaps >= NumGaps) { 1483 DEBUG(dbgs() << "Tagging non-progress ranges: "); 1484 assert(!ProgressRequired && "Didn't make progress when it was required."); 1485 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i) 1486 if (IntvMap[i] == 1) { 1487 setStage(*LREdit.get(i), RS_Split2); 1488 DEBUG(dbgs() << PrintReg(LREdit.get(i)->reg)); 1489 } 1490 DEBUG(dbgs() << '\n'); 1491 } 1492 ++NumLocalSplits; 1493 1494 return 0; 1495} 1496 1497//===----------------------------------------------------------------------===// 1498// Live Range Splitting 1499//===----------------------------------------------------------------------===// 1500 1501/// trySplit - Try to split VirtReg or one of its interferences, making it 1502/// assignable. 1503/// @return Physreg when VirtReg may be assigned and/or new NewVRegs. 1504unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, 1505 SmallVectorImpl<LiveInterval*>&NewVRegs) { 1506 // Ranges must be Split2 or less. 1507 if (getStage(VirtReg) >= RS_Spill) 1508 return 0; 1509 1510 // Local intervals are handled separately. 1511 if (LIS->intervalIsInOneMBB(VirtReg)) { 1512 NamedRegionTimer T("Local Splitting", TimerGroupName, TimePassesIsEnabled); 1513 SA->analyze(&VirtReg); 1514 return tryLocalSplit(VirtReg, Order, NewVRegs); 1515 } 1516 1517 NamedRegionTimer T("Global Splitting", TimerGroupName, TimePassesIsEnabled); 1518 1519 SA->analyze(&VirtReg); 1520 1521 // FIXME: SplitAnalysis may repair broken live ranges coming from the 1522 // coalescer. That may cause the range to become allocatable which means that 1523 // tryRegionSplit won't be making progress. This check should be replaced with 1524 // an assertion when the coalescer is fixed. 1525 if (SA->didRepairRange()) { 1526 // VirtReg has changed, so all cached queries are invalid. 1527 invalidateVirtRegs(); 1528 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) 1529 return PhysReg; 1530 } 1531 1532 // First try to split around a region spanning multiple blocks. RS_Split2 1533 // ranges already made dubious progress with region splitting, so they go 1534 // straight to single block splitting. 1535 if (getStage(VirtReg) < RS_Split2) { 1536 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs); 1537 if (PhysReg || !NewVRegs.empty()) 1538 return PhysReg; 1539 } 1540 1541 // Then isolate blocks. 1542 return tryBlockSplit(VirtReg, Order, NewVRegs); 1543} 1544 1545 1546//===----------------------------------------------------------------------===// 1547// Main Entry Point 1548//===----------------------------------------------------------------------===// 1549 1550unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, 1551 SmallVectorImpl<LiveInterval*> &NewVRegs) { 1552 // First try assigning a free register. 1553 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); 1554 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) 1555 return PhysReg; 1556 1557 LiveRangeStage Stage = getStage(VirtReg); 1558 DEBUG(dbgs() << StageName[Stage] 1559 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n'); 1560 1561 // Try to evict a less worthy live range, but only for ranges from the primary 1562 // queue. The RS_Split ranges already failed to do this, and they should not 1563 // get a second chance until they have been split. 1564 if (Stage != RS_Split) 1565 if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) 1566 return PhysReg; 1567 1568 assert(NewVRegs.empty() && "Cannot append to existing NewVRegs"); 1569 1570 // The first time we see a live range, don't try to split or spill. 1571 // Wait until the second time, when all smaller ranges have been allocated. 1572 // This gives a better picture of the interference to split around. 1573 if (Stage < RS_Split) { 1574 setStage(VirtReg, RS_Split); 1575 DEBUG(dbgs() << "wait for second round\n"); 1576 NewVRegs.push_back(&VirtReg); 1577 return 0; 1578 } 1579 1580 // If we couldn't allocate a register from spilling, there is probably some 1581 // invalid inline assembly. The base class wil report it. 1582 if (Stage >= RS_Done || !VirtReg.isSpillable()) 1583 return ~0u; 1584 1585 // Try splitting VirtReg or interferences. 1586 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs); 1587 if (PhysReg || !NewVRegs.empty()) 1588 return PhysReg; 1589 1590 // Finally spill VirtReg itself. 1591 NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled); 1592 LiveRangeEdit LRE(VirtReg, NewVRegs, this); 1593 spiller().spill(LRE); 1594 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done); 1595 1596 if (VerifyEnabled) 1597 MF->verify(this, "After spilling"); 1598 1599 // The live virtual register requesting allocation was spilled, so tell 1600 // the caller not to allocate anything during this round. 1601 return 0; 1602} 1603 1604bool RAGreedy::runOnMachineFunction(MachineFunction &mf) { 1605 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n" 1606 << "********** Function: " 1607 << ((Value*)mf.getFunction())->getName() << '\n'); 1608 1609 MF = &mf; 1610 if (VerifyEnabled) 1611 MF->verify(this, "Before greedy register allocator"); 1612 1613 RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>()); 1614 Indexes = &getAnalysis<SlotIndexes>(); 1615 DomTree = &getAnalysis<MachineDominatorTree>(); 1616 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); 1617 Loops = &getAnalysis<MachineLoopInfo>(); 1618 Bundles = &getAnalysis<EdgeBundles>(); 1619 SpillPlacer = &getAnalysis<SpillPlacement>(); 1620 DebugVars = &getAnalysis<LiveDebugVariables>(); 1621 1622 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops)); 1623 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree)); 1624 ExtraRegInfo.clear(); 1625 ExtraRegInfo.resize(MRI->getNumVirtRegs()); 1626 NextCascade = 1; 1627 IntfCache.init(MF, &getLiveUnion(0), Indexes, TRI); 1628 GlobalCand.resize(32); // This will grow as needed. 1629 1630 allocatePhysRegs(); 1631 addMBBLiveIns(MF); 1632 LIS->addKillFlags(); 1633 1634 // Run rewriter 1635 { 1636 NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled); 1637 VRM->rewrite(Indexes); 1638 } 1639 1640 // Write out new DBG_VALUE instructions. 1641 { 1642 NamedRegionTimer T("Emit Debug Info", TimerGroupName, TimePassesIsEnabled); 1643 DebugVars->emitDebugValues(VRM); 1644 } 1645 1646 // The pass output is in VirtRegMap. Release all the transient data. 1647 releaseMemory(); 1648 1649 return true; 1650} 1651