RegAllocGreedy.cpp revision ff092faffb85410b0013fb70bc991bb98b5663a5 
1//===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the RAGreedy function pass for register allocation in
11// optimized builds.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "regalloc"
16#include "LiveIntervalUnion.h"
17#include "RegAllocBase.h"
18#include "Spiller.h"
19#include "VirtRegMap.h"
20#include "VirtRegRewriter.h"
21#include "llvm/Analysis/AliasAnalysis.h"
22#include "llvm/Function.h"
23#include "llvm/PassAnalysisSupport.h"
24#include "llvm/CodeGen/CalcSpillWeights.h"
25#include "llvm/CodeGen/LiveIntervalAnalysis.h"
26#include "llvm/CodeGen/LiveStackAnalysis.h"
27#include "llvm/CodeGen/MachineFunctionPass.h"
28#include "llvm/CodeGen/MachineLoopInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/Passes.h"
31#include "llvm/CodeGen/RegAllocRegistry.h"
32#include "llvm/CodeGen/RegisterCoalescer.h"
33#include "llvm/Target/TargetOptions.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
41                                       createGreedyRegisterAllocator);
42
43namespace {
44class RAGreedy : public MachineFunctionPass, public RegAllocBase {
45  // context
46  MachineFunction *MF;
47  const TargetMachine *TM;
48  MachineRegisterInfo *MRI;
49
50  BitVector ReservedRegs;
51
52  // analyses
53  LiveStacks *LS;
54
55  // state
56  std::auto_ptr<Spiller> SpillerInstance;
57
58public:
59  RAGreedy();
60
61  /// Return the pass name.
62  virtual const char* getPassName() const {
63    return "Basic Register Allocator";
64  }
65
66  /// RAGreedy analysis usage.
67  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
68
69  virtual void releaseMemory();
70
71  virtual Spiller &spiller() { return *SpillerInstance; }
72
73  virtual float getPriority(LiveInterval *LI);
74
75  virtual unsigned selectOrSplit(LiveInterval &VirtReg,
76                                 SmallVectorImpl<LiveInterval*> &SplitVRegs);
77
78  /// Perform register allocation.
79  virtual bool runOnMachineFunction(MachineFunction &mf);
80
81  static char ID;
82
83private:
84  bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
85  bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
86};
87} // end anonymous namespace
88
89char RAGreedy::ID = 0;
90
91FunctionPass* llvm::createGreedyRegisterAllocator() {
92  return new RAGreedy();
93}
94
95RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
96  initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
97  initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
98  initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
99  initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
100  initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
101  initializeLiveStacksPass(*PassRegistry::getPassRegistry());
102  initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
103  initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
104  initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
105}
106
107void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
108  AU.setPreservesCFG();
109  AU.addRequired<AliasAnalysis>();
110  AU.addPreserved<AliasAnalysis>();
111  AU.addRequired<LiveIntervals>();
112  AU.addPreserved<SlotIndexes>();
113  if (StrongPHIElim)
114    AU.addRequiredID(StrongPHIEliminationID);
115  AU.addRequiredTransitive<RegisterCoalescer>();
116  AU.addRequired<CalculateSpillWeights>();
117  AU.addRequired<LiveStacks>();
118  AU.addPreserved<LiveStacks>();
119  AU.addRequiredID(MachineDominatorsID);
120  AU.addPreservedID(MachineDominatorsID);
121  AU.addRequired<MachineLoopInfo>();
122  AU.addPreserved<MachineLoopInfo>();
123  AU.addRequired<VirtRegMap>();
124  AU.addPreserved<VirtRegMap>();
125  MachineFunctionPass::getAnalysisUsage(AU);
126}
127
128void RAGreedy::releaseMemory() {
129  SpillerInstance.reset(0);
130  RegAllocBase::releaseMemory();
131}
132
133float RAGreedy::getPriority(LiveInterval *LI) {
134  float Priority = LI->weight;
135
136  // Prioritize hinted registers so they are allocated first.
137  std::pair<unsigned, unsigned> Hint;
138  if (Hint.first || Hint.second) {
139    // The hint can be target specific, a virtual register, or a physreg.
140    Priority *= 2;
141
142    // Prefer physreg hints above anything else.
143    if (Hint.first == 0 && TargetRegisterInfo::isPhysicalRegister(Hint.second))
144      Priority *= 2;
145  }
146  return Priority;
147}
148
149// Attempt to reassign this virtual register to a different physical register.
150//
151// FIXME: we are not yet caching these "second-level" interferences discovered
152// in the sub-queries. These interferences can change with each call to
153// selectOrSplit. However, we could implement a "may-interfere" cache that
154// could be conservatively dirtied when we reassign or split.
155//
156// FIXME: This may result in a lot of alias queries. We could summarize alias
157// live intervals in their parent register's live union, but it's messy.
158bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
159                            unsigned OldPhysReg) {
160  assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
161         "inconsistent phys reg assigment");
162
163  const TargetRegisterClass *TRC = MRI->getRegClass(InterferingVReg.reg);
164  for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
165         E = TRC->allocation_order_end(*MF);
166       I != E; ++I) {
167    unsigned PhysReg = *I;
168    if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg))
169      continue;
170
171    // Instantiate a "subquery", not to be confused with the Queries array.
172    LiveIntervalUnion::Query subQ(&InterferingVReg,
173                                  &PhysReg2LiveUnion[PhysReg]);
174    if (subQ.checkInterference())
175      continue;
176
177    for (const unsigned *AliasI = TRI->getAliasSet(PhysReg);
178         *AliasI; ++AliasI) {
179      subQ.init(&InterferingVReg, &PhysReg2LiveUnion[*AliasI]);
180      if (subQ.checkInterference())
181        continue;
182    }
183    DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
184          TRI->getName(OldPhysReg) << " to " << TRI->getName(PhysReg) << '\n');
185
186    // Reassign the interfering virtual reg to this physical reg.
187    PhysReg2LiveUnion[OldPhysReg].extract(InterferingVReg);
188    VRM->clearVirt(InterferingVReg.reg);
189    VRM->assignVirt2Phys(InterferingVReg.reg, PhysReg);
190    PhysReg2LiveUnion[PhysReg].unify(InterferingVReg);
191
192    return true;
193  }
194  return false;
195}
196
197// Collect all virtual regs currently assigned to PhysReg that interfere with
198// VirtReg.
199//
200// Currently, for simplicity, we only attempt to reassign a single interference
201// within the same register class.
202bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) {
203  LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
204
205  // Limit the interference search to one interference.
206  Q.collectInterferingVRegs(1);
207  assert(Q.interferingVRegs().size() == 1 &&
208         "expected at least one interference");
209
210  // Do not attempt reassignment unless we find only a single interference.
211  if (!Q.seenAllInterferences())
212    return false;
213
214  // Don't allow any interferences on aliases.
215  for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
216    if (query(VirtReg, *AliasI).checkInterference())
217      return false;
218  }
219
220  return reassignVReg(*Q.interferingVRegs()[0], PhysReg);
221}
222
223unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
224                                SmallVectorImpl<LiveInterval*> &SplitVRegs) {
225  // Populate a list of physical register spill candidates.
226  SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands;
227
228  // Check for an available register in this class.
229  const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
230  DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
231
232  // Preferred physical register computed from hints.
233  unsigned Hint = VRM->getRegAllocPref(VirtReg.reg);
234
235  // Try a hinted allocation.
236  if (Hint && !ReservedRegs.test(Hint) && TRC->contains(Hint) &&
237      checkPhysRegInterference(VirtReg, Hint) == 0)
238    return Hint;
239
240  for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
241         E = TRC->allocation_order_end(*MF);
242       I != E; ++I) {
243
244    unsigned PhysReg = *I;
245    if (ReservedRegs.test(PhysReg)) continue;
246
247    // Check interference and as a side effect, intialize queries for this
248    // VirtReg and its aliases.
249    unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg);
250    if (InterfReg == 0) {
251      // Found an available register.
252      return PhysReg;
253    }
254    assert(!VirtReg.empty() && "Empty VirtReg has interference");
255    LiveInterval *InterferingVirtReg =
256      Queries[InterfReg].firstInterference().liveUnionPos().value();
257
258    // The current VirtReg must either be spillable, or one of its interferences
259    // must have less spill weight.
260    if (InterferingVirtReg->weight < VirtReg.weight ) {
261      // For simplicity, only consider reassigning registers in the same class.
262      if (InterfReg == PhysReg)
263        ReassignCands.push_back(PhysReg);
264      else
265        PhysRegSpillCands.push_back(PhysReg);
266    }
267  }
268
269  // Try to reassign interfering physical register. Priority among
270  // PhysRegSpillCands does not matter yet, because the reassigned virtual
271  // registers will still be assigned to physical registers.
272  for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
273         PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
274    if (reassignInterferences(VirtReg, *PhysRegI))
275      // Reassignment successfull. The caller may allocate now to this PhysReg.
276      return *PhysRegI;
277  }
278
279  PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
280                           ReassignCands.end());
281
282  // Try to spill another interfering reg with less spill weight.
283  //
284  // FIXME: do this in two steps: (1) check for unspillable interferences while
285  // accumulating spill weight; (2) spill the interferences with lowest
286  // aggregate spill weight.
287  for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
288         PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
289
290    if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
291
292    assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
293           "Interference after spill.");
294    // Tell the caller to allocate to this newly freed physical register.
295    return *PhysRegI;
296  }
297
298  // No other spill candidates were found, so spill the current VirtReg.
299  DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
300  SmallVector<LiveInterval*, 1> pendingSpills;
301
302  spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
303
304  // The live virtual register requesting allocation was spilled, so tell
305  // the caller not to allocate anything during this round.
306  return 0;
307}
308
309bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
310  DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
311               << "********** Function: "
312               << ((Value*)mf.getFunction())->getName() << '\n');
313
314  MF = &mf;
315  TM = &mf.getTarget();
316  MRI = &mf.getRegInfo();
317
318  const TargetRegisterInfo *TRI = TM->getRegisterInfo();
319  RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
320                     getAnalysis<LiveIntervals>());
321
322  ReservedRegs = TRI->getReservedRegs(*MF);
323  SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
324  allocatePhysRegs();
325  addMBBLiveIns(MF);
326
327  // Run rewriter
328  std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
329  rewriter->runOnMachineFunction(*MF, *VRM, LIS);
330
331  // The pass output is in VirtRegMap. Release all the transient data.
332  releaseMemory();
333
334  return true;
335}
336
337