RegisterCoalescer.cpp revision c5c2fcd307695c40b00a64152d83c7af13c446c0
1//===- RegisterCoalescer.cpp - Generic Register Coalescing Interface -------==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the generic RegisterCoalescer interface which 11// is used as the common interface used by all clients and 12// implementations of register coalescing. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "regalloc" 17#include "RegisterCoalescer.h" 18#include "LiveDebugVariables.h" 19#include "RegisterClassInfo.h" 20#include "VirtRegMap.h" 21 22#include "llvm/Pass.h" 23#include "llvm/Value.h" 24#include "llvm/CodeGen/LiveIntervalAnalysis.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/Target/TargetInstrInfo.h" 28#include "llvm/Target/TargetRegisterInfo.h" 29#include "llvm/CodeGen/LiveIntervalAnalysis.h" 30#include "llvm/Analysis/AliasAnalysis.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineInstr.h" 33#include "llvm/CodeGen/MachineLoopInfo.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/Passes.h" 36#include "llvm/Target/TargetInstrInfo.h" 37#include "llvm/Target/TargetMachine.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/Support/CommandLine.h" 40#include "llvm/Support/Debug.h" 41#include "llvm/Support/ErrorHandling.h" 42#include "llvm/Support/raw_ostream.h" 43#include "llvm/ADT/OwningPtr.h" 44#include "llvm/ADT/SmallSet.h" 45#include "llvm/ADT/Statistic.h" 46#include "llvm/ADT/STLExtras.h" 47#include <algorithm> 48#include <cmath> 49using namespace llvm; 50 51STATISTIC(numJoins , "Number of interval joins performed"); 52STATISTIC(numCrossRCs , "Number of cross class joins performed"); 53STATISTIC(numCommutes , "Number of instruction commuting performed"); 54STATISTIC(numExtends , "Number of copies extended"); 55STATISTIC(NumReMats , "Number of instructions re-materialized"); 56STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); 57STATISTIC(numAborts , "Number of times interval joining aborted"); 58STATISTIC(NumInflated , "Number of register classes inflated"); 59 60static cl::opt<bool> 61EnableJoining("join-liveintervals", 62 cl::desc("Coalesce copies (default=true)"), 63 cl::init(true)); 64 65static cl::opt<bool> 66DisableCrossClassJoin("disable-cross-class-join", 67 cl::desc("Avoid coalescing cross register class copies"), 68 cl::init(false), cl::Hidden); 69 70static cl::opt<bool> 71EnablePhysicalJoin("join-physregs", 72 cl::desc("Join physical register copies"), 73 cl::init(false), cl::Hidden); 74 75static cl::opt<bool> 76VerifyCoalescing("verify-coalescing", 77 cl::desc("Verify machine instrs before and after register coalescing"), 78 cl::Hidden); 79 80namespace { 81 class RegisterCoalescer : public MachineFunctionPass { 82 MachineFunction* MF; 83 MachineRegisterInfo* MRI; 84 const TargetMachine* TM; 85 const TargetRegisterInfo* TRI; 86 const TargetInstrInfo* TII; 87 LiveIntervals *LIS; 88 LiveDebugVariables *LDV; 89 const MachineLoopInfo* Loops; 90 AliasAnalysis *AA; 91 RegisterClassInfo RegClassInfo; 92 93 /// JoinedCopies - Keep track of copies eliminated due to coalescing. 94 /// 95 SmallPtrSet<MachineInstr*, 32> JoinedCopies; 96 97 /// ReMatCopies - Keep track of copies eliminated due to remat. 98 /// 99 SmallPtrSet<MachineInstr*, 32> ReMatCopies; 100 101 /// ReMatDefs - Keep track of definition instructions which have 102 /// been remat'ed. 103 SmallPtrSet<MachineInstr*, 8> ReMatDefs; 104 105 /// joinIntervals - join compatible live intervals 106 void joinIntervals(); 107 108 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting 109 /// copies that cannot yet be coalesced into the "TryAgain" list. 110 void CopyCoalesceInMBB(MachineBasicBlock *MBB, 111 std::vector<MachineInstr*> &TryAgain); 112 113 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 114 /// which are the src/dst of the copy instruction CopyMI. This returns 115 /// true if the copy was successfully coalesced away. If it is not 116 /// currently possible to coalesce this interval, but it may be possible if 117 /// other things get coalesced, then it returns true by reference in 118 /// 'Again'. 119 bool JoinCopy(MachineInstr *TheCopy, bool &Again); 120 121 /// JoinIntervals - Attempt to join these two intervals. On failure, this 122 /// returns false. The output "SrcInt" will not have been modified, so we 123 /// can use this information below to update aliases. 124 bool JoinIntervals(CoalescerPair &CP); 125 126 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If 127 /// the source value number is defined by a copy from the destination reg 128 /// see if we can merge these two destination reg valno# into a single 129 /// value number, eliminating a copy. 130 bool AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI); 131 132 /// HasOtherReachingDefs - Return true if there are definitions of IntB 133 /// other than BValNo val# that can reach uses of AValno val# of IntA. 134 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB, 135 VNInfo *AValNo, VNInfo *BValNo); 136 137 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy. 138 /// If the source value number is defined by a commutable instruction and 139 /// its other operand is coalesced to the copy dest register, see if we 140 /// can transform the copy into a noop by commuting the definition. 141 bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI); 142 143 /// ReMaterializeTrivialDef - If the source of a copy is defined by a 144 /// trivial computation, replace the copy by rematerialize the definition. 145 /// If PreserveSrcInt is true, make sure SrcInt is valid after the call. 146 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, bool PreserveSrcInt, 147 unsigned DstReg, MachineInstr *CopyMI); 148 149 /// shouldJoinPhys - Return true if a physreg copy should be joined. 150 bool shouldJoinPhys(CoalescerPair &CP); 151 152 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce 153 /// two virtual registers from different register classes. 154 bool isWinToJoinCrossClass(unsigned SrcReg, 155 unsigned DstReg, 156 const TargetRegisterClass *SrcRC, 157 const TargetRegisterClass *DstRC, 158 const TargetRegisterClass *NewRC); 159 160 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and 161 /// update the subregister number if it is not zero. If DstReg is a 162 /// physical register and the existing subregister number of the def / use 163 /// being updated is not zero, make sure to set it to the correct physical 164 /// subregister. 165 void UpdateRegDefsUses(const CoalescerPair &CP); 166 167 /// RemoveDeadDef - If a def of a live interval is now determined dead, 168 /// remove the val# it defines. If the live interval becomes empty, remove 169 /// it as well. 170 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI); 171 172 /// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the 173 /// VNInfo copy flag for DstReg and all aliases. 174 void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI); 175 176 /// markAsJoined - Remember that CopyMI has already been joined. 177 void markAsJoined(MachineInstr *CopyMI); 178 179 /// eliminateUndefCopy - Handle copies of undef values. 180 bool eliminateUndefCopy(MachineInstr *CopyMI, const CoalescerPair &CP); 181 182 public: 183 static char ID; // Class identification, replacement for typeinfo 184 RegisterCoalescer() : MachineFunctionPass(ID) { 185 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry()); 186 } 187 188 virtual void getAnalysisUsage(AnalysisUsage &AU) const; 189 190 virtual void releaseMemory(); 191 192 /// runOnMachineFunction - pass entry point 193 virtual bool runOnMachineFunction(MachineFunction&); 194 195 /// print - Implement the dump method. 196 virtual void print(raw_ostream &O, const Module* = 0) const; 197 }; 198} /// end anonymous namespace 199 200char &llvm::RegisterCoalescerPassID = RegisterCoalescer::ID; 201 202INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing", 203 "Simple Register Coalescing", false, false) 204INITIALIZE_PASS_DEPENDENCY(LiveIntervals) 205INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables) 206INITIALIZE_PASS_DEPENDENCY(SlotIndexes) 207INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) 208INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination) 209INITIALIZE_PASS_DEPENDENCY(PHIElimination) 210INITIALIZE_PASS_DEPENDENCY(TwoAddressInstructionPass) 211INITIALIZE_AG_DEPENDENCY(AliasAnalysis) 212INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing", 213 "Simple Register Coalescing", false, false) 214 215char RegisterCoalescer::ID = 0; 216 217static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) { 218 if (!a) return b; 219 if (!b) return a; 220 return tri.composeSubRegIndices(a, b); 221} 222 223static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI, 224 unsigned &Src, unsigned &Dst, 225 unsigned &SrcSub, unsigned &DstSub) { 226 if (MI->isCopy()) { 227 Dst = MI->getOperand(0).getReg(); 228 DstSub = MI->getOperand(0).getSubReg(); 229 Src = MI->getOperand(1).getReg(); 230 SrcSub = MI->getOperand(1).getSubReg(); 231 } else if (MI->isSubregToReg()) { 232 Dst = MI->getOperand(0).getReg(); 233 DstSub = compose(tri, MI->getOperand(0).getSubReg(), 234 MI->getOperand(3).getImm()); 235 Src = MI->getOperand(2).getReg(); 236 SrcSub = MI->getOperand(2).getSubReg(); 237 } else 238 return false; 239 return true; 240} 241 242bool CoalescerPair::setRegisters(const MachineInstr *MI) { 243 SrcReg = DstReg = SubIdx = 0; 244 NewRC = 0; 245 Flipped = CrossClass = false; 246 247 unsigned Src, Dst, SrcSub, DstSub; 248 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub)) 249 return false; 250 Partial = SrcSub || DstSub; 251 252 // If one register is a physreg, it must be Dst. 253 if (TargetRegisterInfo::isPhysicalRegister(Src)) { 254 if (TargetRegisterInfo::isPhysicalRegister(Dst)) 255 return false; 256 std::swap(Src, Dst); 257 std::swap(SrcSub, DstSub); 258 Flipped = true; 259 } 260 261 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 262 263 if (TargetRegisterInfo::isPhysicalRegister(Dst)) { 264 // Eliminate DstSub on a physreg. 265 if (DstSub) { 266 Dst = TRI.getSubReg(Dst, DstSub); 267 if (!Dst) return false; 268 DstSub = 0; 269 } 270 271 // Eliminate SrcSub by picking a corresponding Dst superregister. 272 if (SrcSub) { 273 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); 274 if (!Dst) return false; 275 SrcSub = 0; 276 } else if (!MRI.getRegClass(Src)->contains(Dst)) { 277 return false; 278 } 279 } else { 280 // Both registers are virtual. 281 282 // Both registers have subreg indices. 283 if (SrcSub && DstSub) { 284 // For now we only handle the case of identical indices in commensurate 285 // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg 286 // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg. 287 if (SrcSub != DstSub) 288 return false; 289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 290 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 291 if (!TRI.getCommonSubClass(DstRC, SrcRC)) 292 return false; 293 SrcSub = DstSub = 0; 294 } 295 296 // There can be no SrcSub. 297 if (SrcSub) { 298 std::swap(Src, Dst); 299 DstSub = SrcSub; 300 SrcSub = 0; 301 assert(!Flipped && "Unexpected flip"); 302 Flipped = true; 303 } 304 305 // Find the new register class. 306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 307 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 308 if (DstSub) 309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); 310 else 311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); 312 if (!NewRC) 313 return false; 314 CrossClass = NewRC != DstRC || NewRC != SrcRC; 315 } 316 // Check our invariants 317 assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual"); 318 assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) && 319 "Cannot have a physical SubIdx"); 320 SrcReg = Src; 321 DstReg = Dst; 322 SubIdx = DstSub; 323 return true; 324} 325 326bool CoalescerPair::flip() { 327 if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg)) 328 return false; 329 std::swap(SrcReg, DstReg); 330 Flipped = !Flipped; 331 return true; 332} 333 334bool CoalescerPair::isCoalescable(const MachineInstr *MI) const { 335 if (!MI) 336 return false; 337 unsigned Src, Dst, SrcSub, DstSub; 338 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub)) 339 return false; 340 341 // Find the virtual register that is SrcReg. 342 if (Dst == SrcReg) { 343 std::swap(Src, Dst); 344 std::swap(SrcSub, DstSub); 345 } else if (Src != SrcReg) { 346 return false; 347 } 348 349 // Now check that Dst matches DstReg. 350 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { 351 if (!TargetRegisterInfo::isPhysicalRegister(Dst)) 352 return false; 353 assert(!SubIdx && "Inconsistent CoalescerPair state."); 354 // DstSub could be set for a physreg from INSERT_SUBREG. 355 if (DstSub) 356 Dst = TRI.getSubReg(Dst, DstSub); 357 // Full copy of Src. 358 if (!SrcSub) 359 return DstReg == Dst; 360 // This is a partial register copy. Check that the parts match. 361 return TRI.getSubReg(DstReg, SrcSub) == Dst; 362 } else { 363 // DstReg is virtual. 364 if (DstReg != Dst) 365 return false; 366 // Registers match, do the subregisters line up? 367 return compose(TRI, SubIdx, SrcSub) == DstSub; 368 } 369} 370 371void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const { 372 AU.setPreservesCFG(); 373 AU.addRequired<AliasAnalysis>(); 374 AU.addRequired<LiveIntervals>(); 375 AU.addPreserved<LiveIntervals>(); 376 AU.addRequired<LiveDebugVariables>(); 377 AU.addPreserved<LiveDebugVariables>(); 378 AU.addPreserved<SlotIndexes>(); 379 AU.addRequired<MachineLoopInfo>(); 380 AU.addPreserved<MachineLoopInfo>(); 381 AU.addPreservedID(MachineDominatorsID); 382 AU.addPreservedID(StrongPHIEliminationID); 383 AU.addPreservedID(PHIEliminationID); 384 AU.addPreservedID(TwoAddressInstructionPassID); 385 MachineFunctionPass::getAnalysisUsage(AU); 386} 387 388void RegisterCoalescer::markAsJoined(MachineInstr *CopyMI) { 389 /// Joined copies are not deleted immediately, but kept in JoinedCopies. 390 JoinedCopies.insert(CopyMI); 391 392 /// Mark all register operands of CopyMI as <undef> so they won't affect dead 393 /// code elimination. 394 for (MachineInstr::mop_iterator I = CopyMI->operands_begin(), 395 E = CopyMI->operands_end(); I != E; ++I) 396 if (I->isReg()) 397 I->setIsUndef(true); 398} 399 400/// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA 401/// being the source and IntB being the dest, thus this defines a value number 402/// in IntB. If the source value number (in IntA) is defined by a copy from B, 403/// see if we can merge these two pieces of B into a single value number, 404/// eliminating a copy. For example: 405/// 406/// A3 = B0 407/// ... 408/// B1 = A3 <- this copy 409/// 410/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 411/// value number to be replaced with B0 (which simplifies the B liveinterval). 412/// 413/// This returns true if an interval was modified. 414/// 415bool RegisterCoalescer::AdjustCopiesBackFrom(const CoalescerPair &CP, 416 MachineInstr *CopyMI) { 417 // Bail if there is no dst interval - can happen when merging physical subreg 418 // operations. 419 if (!LIS->hasInterval(CP.getDstReg())) 420 return false; 421 422 LiveInterval &IntA = 423 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); 424 LiveInterval &IntB = 425 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); 426 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(); 427 428 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 429 // the example above. 430 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); 431 if (BLR == IntB.end()) return false; 432 VNInfo *BValNo = BLR->valno; 433 434 // Get the location that B is defined at. Two options: either this value has 435 // an unknown definition point or it is defined at CopyIdx. If unknown, we 436 // can't process it. 437 if (!BValNo->isDefByCopy()) return false; 438 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); 439 440 // AValNo is the value number in A that defines the copy, A3 in the example. 441 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true); 442 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx); 443 // The live range might not exist after fun with physreg coalescing. 444 if (ALR == IntA.end()) return false; 445 VNInfo *AValNo = ALR->valno; 446 // If it's re-defined by an early clobber somewhere in the live range, then 447 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround. 448 // See PR3149: 449 // 172 %ECX<def> = MOV32rr %reg1039<kill> 450 // 180 INLINEASM <es:subl $5,$1 451 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, 452 // %EAX<kill>, 453 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0 454 // 188 %EAX<def> = MOV32rr %EAX<kill> 455 // 196 %ECX<def> = MOV32rr %ECX<kill> 456 // 204 %ECX<def> = MOV32rr %ECX<kill> 457 // 212 %EAX<def> = MOV32rr %EAX<kill> 458 // 220 %EAX<def> = MOV32rr %EAX 459 // 228 %reg1039<def> = MOV32rr %ECX<kill> 460 // The early clobber operand ties ECX input to the ECX def. 461 // 462 // The live interval of ECX is represented as this: 463 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47) 464 // The coalescer has no idea there was a def in the middle of [174,230]. 465 if (AValNo->hasRedefByEC()) 466 return false; 467 468 // If AValNo is defined as a copy from IntB, we can potentially process this. 469 // Get the instruction that defines this value number. 470 if (!CP.isCoalescable(AValNo->getCopy())) 471 return false; 472 473 // Get the LiveRange in IntB that this value number starts with. 474 LiveInterval::iterator ValLR = 475 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot()); 476 if (ValLR == IntB.end()) 477 return false; 478 479 // Make sure that the end of the live range is inside the same block as 480 // CopyMI. 481 MachineInstr *ValLREndInst = 482 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot()); 483 if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent()) 484 return false; 485 486 // Okay, we now know that ValLR ends in the same block that the CopyMI 487 // live-range starts. If there are no intervening live ranges between them in 488 // IntB, we can merge them. 489 if (ValLR+1 != BLR) return false; 490 491 // If a live interval is a physical register, conservatively check if any 492 // of its aliases is overlapping the live interval of the virtual register. 493 // If so, do not coalesce. 494 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { 495 for (const unsigned *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS) 496 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) { 497 DEBUG({ 498 dbgs() << "\t\tInterfere with alias "; 499 LIS->getInterval(*AS).print(dbgs(), TRI); 500 }); 501 return false; 502 } 503 } 504 505 DEBUG({ 506 dbgs() << "Extending: "; 507 IntB.print(dbgs(), TRI); 508 }); 509 510 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start; 511 // We are about to delete CopyMI, so need to remove it as the 'instruction 512 // that defines this value #'. Update the valnum with the new defining 513 // instruction #. 514 BValNo->def = FillerStart; 515 BValNo->setCopy(0); 516 517 // Okay, we can merge them. We need to insert a new liverange: 518 // [ValLR.end, BLR.begin) of either value number, then we merge the 519 // two value numbers. 520 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); 521 522 // If the IntB live range is assigned to a physical register, and if that 523 // physreg has sub-registers, update their live intervals as well. 524 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { 525 for (const unsigned *SR = TRI->getSubRegisters(IntB.reg); *SR; ++SR) { 526 if (!LIS->hasInterval(*SR)) 527 continue; 528 LiveInterval &SRLI = LIS->getInterval(*SR); 529 SRLI.addRange(LiveRange(FillerStart, FillerEnd, 530 SRLI.getNextValue(FillerStart, 0, 531 LIS->getVNInfoAllocator()))); 532 } 533 } 534 535 // Okay, merge "B1" into the same value number as "B0". 536 if (BValNo != ValLR->valno) { 537 // If B1 is killed by a PHI, then the merged live range must also be killed 538 // by the same PHI, as B0 and B1 can not overlap. 539 bool HasPHIKill = BValNo->hasPHIKill(); 540 IntB.MergeValueNumberInto(BValNo, ValLR->valno); 541 if (HasPHIKill) 542 ValLR->valno->setHasPHIKill(true); 543 } 544 DEBUG({ 545 dbgs() << " result = "; 546 IntB.print(dbgs(), TRI); 547 dbgs() << "\n"; 548 }); 549 550 // If the source instruction was killing the source register before the 551 // merge, unset the isKill marker given the live range has been extended. 552 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true); 553 if (UIdx != -1) { 554 ValLREndInst->getOperand(UIdx).setIsKill(false); 555 } 556 557 // Rewrite the copy. If the copy instruction was killing the destination 558 // register before the merge, find the last use and trim the live range. That 559 // will also add the isKill marker. 560 CopyMI->substituteRegister(IntA.reg, IntB.reg, CP.getSubIdx(), 561 *TRI); 562 if (ALR->end == CopyIdx) 563 LIS->shrinkToUses(&IntA); 564 565 ++numExtends; 566 return true; 567} 568 569/// HasOtherReachingDefs - Return true if there are definitions of IntB 570/// other than BValNo val# that can reach uses of AValno val# of IntA. 571bool RegisterCoalescer::HasOtherReachingDefs(LiveInterval &IntA, 572 LiveInterval &IntB, 573 VNInfo *AValNo, 574 VNInfo *BValNo) { 575 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); 576 AI != AE; ++AI) { 577 if (AI->valno != AValNo) continue; 578 LiveInterval::Ranges::iterator BI = 579 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start); 580 if (BI != IntB.ranges.begin()) 581 --BI; 582 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) { 583 if (BI->valno == BValNo) 584 continue; 585 if (BI->start <= AI->start && BI->end > AI->start) 586 return true; 587 if (BI->start > AI->start && BI->start < AI->end) 588 return true; 589 } 590 } 591 return false; 592} 593 594/// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with 595/// IntA being the source and IntB being the dest, thus this defines a value 596/// number in IntB. If the source value number (in IntA) is defined by a 597/// commutable instruction and its other operand is coalesced to the copy dest 598/// register, see if we can transform the copy into a noop by commuting the 599/// definition. For example, 600/// 601/// A3 = op A2 B0<kill> 602/// ... 603/// B1 = A3 <- this copy 604/// ... 605/// = op A3 <- more uses 606/// 607/// ==> 608/// 609/// B2 = op B0 A2<kill> 610/// ... 611/// B1 = B2 <- now an identify copy 612/// ... 613/// = op B2 <- more uses 614/// 615/// This returns true if an interval was modified. 616/// 617bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP, 618 MachineInstr *CopyMI) { 619 // FIXME: For now, only eliminate the copy by commuting its def when the 620 // source register is a virtual register. We want to guard against cases 621 // where the copy is a back edge copy and commuting the def lengthen the 622 // live interval of the source register to the entire loop. 623 if (CP.isPhys() && CP.isFlipped()) 624 return false; 625 626 // Bail if there is no dst interval. 627 if (!LIS->hasInterval(CP.getDstReg())) 628 return false; 629 630 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(); 631 632 LiveInterval &IntA = 633 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); 634 LiveInterval &IntB = 635 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); 636 637 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 638 // the example above. 639 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx); 640 if (!BValNo || !BValNo->isDefByCopy()) 641 return false; 642 643 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); 644 645 // AValNo is the value number in A that defines the copy, A3 in the example. 646 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true)); 647 assert(AValNo && "COPY source not live"); 648 649 // If other defs can reach uses of this def, then it's not safe to perform 650 // the optimization. 651 if (AValNo->isPHIDef() || AValNo->isUnused() || AValNo->hasPHIKill()) 652 return false; 653 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); 654 if (!DefMI) 655 return false; 656 if (!DefMI->isCommutable()) 657 return false; 658 // If DefMI is a two-address instruction then commuting it will change the 659 // destination register. 660 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); 661 assert(DefIdx != -1); 662 unsigned UseOpIdx; 663 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 664 return false; 665 unsigned Op1, Op2, NewDstIdx; 666 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2)) 667 return false; 668 if (Op1 == UseOpIdx) 669 NewDstIdx = Op2; 670 else if (Op2 == UseOpIdx) 671 NewDstIdx = Op1; 672 else 673 return false; 674 675 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); 676 unsigned NewReg = NewDstMO.getReg(); 677 if (NewReg != IntB.reg || !NewDstMO.isKill()) 678 return false; 679 680 // Make sure there are no other definitions of IntB that would reach the 681 // uses which the new definition can reach. 682 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo)) 683 return false; 684 685 // Abort if the aliases of IntB.reg have values that are not simply the 686 // clobbers from the superreg. 687 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) 688 for (const unsigned *AS = TRI->getAliasSet(IntB.reg); *AS; ++AS) 689 if (LIS->hasInterval(*AS) && 690 HasOtherReachingDefs(IntA, LIS->getInterval(*AS), AValNo, 0)) 691 return false; 692 693 // If some of the uses of IntA.reg is already coalesced away, return false. 694 // It's not possible to determine whether it's safe to perform the coalescing. 695 for (MachineRegisterInfo::use_nodbg_iterator UI = 696 MRI->use_nodbg_begin(IntA.reg), 697 UE = MRI->use_nodbg_end(); UI != UE; ++UI) { 698 MachineInstr *UseMI = &*UI; 699 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); 700 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); 701 if (ULR == IntA.end()) 702 continue; 703 if (ULR->valno == AValNo && JoinedCopies.count(UseMI)) 704 return false; 705 } 706 707 DEBUG(dbgs() << "\tRemoveCopyByCommutingDef: " << AValNo->def << '\t' 708 << *DefMI); 709 710 // At this point we have decided that it is legal to do this 711 // transformation. Start by commuting the instruction. 712 MachineBasicBlock *MBB = DefMI->getParent(); 713 MachineInstr *NewMI = TII->commuteInstruction(DefMI); 714 if (!NewMI) 715 return false; 716 if (TargetRegisterInfo::isVirtualRegister(IntA.reg) && 717 TargetRegisterInfo::isVirtualRegister(IntB.reg) && 718 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) 719 return false; 720 if (NewMI != DefMI) { 721 LIS->ReplaceMachineInstrInMaps(DefMI, NewMI); 722 MachineBasicBlock::iterator Pos = DefMI; 723 MBB->insert(Pos, NewMI); 724 MBB->erase(DefMI); 725 } 726 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); 727 NewMI->getOperand(OpIdx).setIsKill(); 728 729 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. 730 // A = or A, B 731 // ... 732 // B = A 733 // ... 734 // C = A<kill> 735 // ... 736 // = B 737 738 // Update uses of IntA of the specific Val# with IntB. 739 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg), 740 UE = MRI->use_end(); UI != UE;) { 741 MachineOperand &UseMO = UI.getOperand(); 742 MachineInstr *UseMI = &*UI; 743 ++UI; 744 if (JoinedCopies.count(UseMI)) 745 continue; 746 if (UseMI->isDebugValue()) { 747 // FIXME These don't have an instruction index. Not clear we have enough 748 // info to decide whether to do this replacement or not. For now do it. 749 UseMO.setReg(NewReg); 750 continue; 751 } 752 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); 753 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); 754 if (ULR == IntA.end() || ULR->valno != AValNo) 755 continue; 756 if (TargetRegisterInfo::isPhysicalRegister(NewReg)) 757 UseMO.substPhysReg(NewReg, *TRI); 758 else 759 UseMO.setReg(NewReg); 760 if (UseMI == CopyMI) 761 continue; 762 if (!UseMI->isCopy()) 763 continue; 764 if (UseMI->getOperand(0).getReg() != IntB.reg || 765 UseMI->getOperand(0).getSubReg()) 766 continue; 767 768 // This copy will become a noop. If it's defining a new val#, merge it into 769 // BValNo. 770 SlotIndex DefIdx = UseIdx.getRegSlot(); 771 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); 772 if (!DVNI) 773 continue; 774 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); 775 assert(DVNI->def == DefIdx); 776 BValNo = IntB.MergeValueNumberInto(BValNo, DVNI); 777 markAsJoined(UseMI); 778 } 779 780 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition 781 // is updated. 782 VNInfo *ValNo = BValNo; 783 ValNo->def = AValNo->def; 784 ValNo->setCopy(0); 785 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); 786 AI != AE; ++AI) { 787 if (AI->valno != AValNo) continue; 788 IntB.addRange(LiveRange(AI->start, AI->end, ValNo)); 789 } 790 DEBUG(dbgs() << "\t\textended: " << IntB << '\n'); 791 792 IntA.removeValNo(AValNo); 793 DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n'); 794 ++numCommutes; 795 return true; 796} 797 798/// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial 799/// computation, replace the copy by rematerialize the definition. 800bool RegisterCoalescer::ReMaterializeTrivialDef(LiveInterval &SrcInt, 801 bool preserveSrcInt, 802 unsigned DstReg, 803 MachineInstr *CopyMI) { 804 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true); 805 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx); 806 assert(SrcLR != SrcInt.end() && "Live range not found!"); 807 VNInfo *ValNo = SrcLR->valno; 808 if (ValNo->isPHIDef() || ValNo->isUnused()) 809 return false; 810 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def); 811 if (!DefMI) 812 return false; 813 assert(DefMI && "Defining instruction disappeared"); 814 if (!DefMI->isAsCheapAsAMove()) 815 return false; 816 if (!TII->isTriviallyReMaterializable(DefMI, AA)) 817 return false; 818 bool SawStore = false; 819 if (!DefMI->isSafeToMove(TII, AA, SawStore)) 820 return false; 821 const MCInstrDesc &MCID = DefMI->getDesc(); 822 if (MCID.getNumDefs() != 1) 823 return false; 824 if (!DefMI->isImplicitDef()) { 825 // Make sure the copy destination register class fits the instruction 826 // definition register class. The mismatch can happen as a result of earlier 827 // extract_subreg, insert_subreg, subreg_to_reg coalescing. 828 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI); 829 if (TargetRegisterInfo::isVirtualRegister(DstReg)) { 830 if (MRI->getRegClass(DstReg) != RC) 831 return false; 832 } else if (!RC->contains(DstReg)) 833 return false; 834 } 835 836 RemoveCopyFlag(DstReg, CopyMI); 837 838 MachineBasicBlock *MBB = CopyMI->getParent(); 839 MachineBasicBlock::iterator MII = 840 llvm::next(MachineBasicBlock::iterator(CopyMI)); 841 TII->reMaterialize(*MBB, MII, DstReg, 0, DefMI, *TRI); 842 MachineInstr *NewMI = prior(MII); 843 844 // CopyMI may have implicit operands, transfer them over to the newly 845 // rematerialized instruction. And update implicit def interval valnos. 846 for (unsigned i = CopyMI->getDesc().getNumOperands(), 847 e = CopyMI->getNumOperands(); i != e; ++i) { 848 MachineOperand &MO = CopyMI->getOperand(i); 849 if (MO.isReg() && MO.isImplicit()) 850 NewMI->addOperand(MO); 851 if (MO.isDef()) 852 RemoveCopyFlag(MO.getReg(), CopyMI); 853 } 854 855 LIS->ReplaceMachineInstrInMaps(CopyMI, NewMI); 856 CopyMI->eraseFromParent(); 857 ReMatCopies.insert(CopyMI); 858 ReMatDefs.insert(DefMI); 859 DEBUG(dbgs() << "Remat: " << *NewMI); 860 ++NumReMats; 861 862 // The source interval can become smaller because we removed a use. 863 if (preserveSrcInt) 864 LIS->shrinkToUses(&SrcInt); 865 866 return true; 867} 868 869/// eliminateUndefCopy - ProcessImpicitDefs may leave some copies of <undef> 870/// values, it only removes local variables. When we have a copy like: 871/// 872/// %vreg1 = COPY %vreg2<undef> 873/// 874/// We delete the copy and remove the corresponding value number from %vreg1. 875/// Any uses of that value number are marked as <undef>. 876bool RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI, 877 const CoalescerPair &CP) { 878 SlotIndex Idx = LIS->getInstructionIndex(CopyMI); 879 LiveInterval *SrcInt = &LIS->getInterval(CP.getSrcReg()); 880 if (SrcInt->liveAt(Idx)) 881 return false; 882 LiveInterval *DstInt = &LIS->getInterval(CP.getDstReg()); 883 if (DstInt->liveAt(Idx)) 884 return false; 885 886 // No intervals are live-in to CopyMI - it is undef. 887 if (CP.isFlipped()) 888 DstInt = SrcInt; 889 SrcInt = 0; 890 891 VNInfo *DeadVNI = DstInt->getVNInfoAt(Idx.getRegSlot()); 892 assert(DeadVNI && "No value defined in DstInt"); 893 DstInt->removeValNo(DeadVNI); 894 895 // Find new undef uses. 896 for (MachineRegisterInfo::reg_nodbg_iterator 897 I = MRI->reg_nodbg_begin(DstInt->reg), E = MRI->reg_nodbg_end(); 898 I != E; ++I) { 899 MachineOperand &MO = I.getOperand(); 900 if (MO.isDef() || MO.isUndef()) 901 continue; 902 MachineInstr *MI = MO.getParent(); 903 SlotIndex Idx = LIS->getInstructionIndex(MI); 904 if (DstInt->liveAt(Idx)) 905 continue; 906 MO.setIsUndef(true); 907 DEBUG(dbgs() << "\tnew undef: " << Idx << '\t' << *MI); 908 } 909 return true; 910} 911 912/// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and 913/// update the subregister number if it is not zero. If DstReg is a 914/// physical register and the existing subregister number of the def / use 915/// being updated is not zero, make sure to set it to the correct physical 916/// subregister. 917void 918RegisterCoalescer::UpdateRegDefsUses(const CoalescerPair &CP) { 919 bool DstIsPhys = CP.isPhys(); 920 unsigned SrcReg = CP.getSrcReg(); 921 unsigned DstReg = CP.getDstReg(); 922 unsigned SubIdx = CP.getSubIdx(); 923 924 // Update LiveDebugVariables. 925 LDV->renameRegister(SrcReg, DstReg, SubIdx); 926 927 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg); 928 MachineInstr *UseMI = I.skipInstruction();) { 929 // A PhysReg copy that won't be coalesced can perhaps be rematerialized 930 // instead. 931 if (DstIsPhys) { 932 if (UseMI->isFullCopy() && 933 UseMI->getOperand(1).getReg() == SrcReg && 934 UseMI->getOperand(0).getReg() != SrcReg && 935 UseMI->getOperand(0).getReg() != DstReg && 936 !JoinedCopies.count(UseMI) && 937 ReMaterializeTrivialDef(LIS->getInterval(SrcReg), false, 938 UseMI->getOperand(0).getReg(), UseMI)) 939 continue; 940 } 941 942 SmallVector<unsigned,8> Ops; 943 bool Reads, Writes; 944 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); 945 bool Kills = false, Deads = false; 946 947 // Replace SrcReg with DstReg in all UseMI operands. 948 for (unsigned i = 0, e = Ops.size(); i != e; ++i) { 949 MachineOperand &MO = UseMI->getOperand(Ops[i]); 950 Kills |= MO.isKill(); 951 Deads |= MO.isDead(); 952 953 // Make sure we don't create read-modify-write defs accidentally. We 954 // assume here that a SrcReg def cannot be joined into a live DstReg. If 955 // RegisterCoalescer starts tracking partially live registers, we will 956 // need to check the actual LiveInterval to determine if DstReg is live 957 // here. 958 if (SubIdx && !Reads) 959 MO.setIsUndef(); 960 961 if (DstIsPhys) 962 MO.substPhysReg(DstReg, *TRI); 963 else 964 MO.substVirtReg(DstReg, SubIdx, *TRI); 965 } 966 967 // This instruction is a copy that will be removed. 968 if (JoinedCopies.count(UseMI)) 969 continue; 970 971 if (SubIdx) { 972 // If UseMI was a simple SrcReg def, make sure we didn't turn it into a 973 // read-modify-write of DstReg. 974 if (Deads) 975 UseMI->addRegisterDead(DstReg, TRI); 976 else if (!Reads && Writes) 977 UseMI->addRegisterDefined(DstReg, TRI); 978 979 // Kill flags apply to the whole physical register. 980 if (DstIsPhys && Kills) 981 UseMI->addRegisterKilled(DstReg, TRI); 982 } 983 984 DEBUG({ 985 dbgs() << "\t\tupdated: "; 986 if (!UseMI->isDebugValue()) 987 dbgs() << LIS->getInstructionIndex(UseMI) << "\t"; 988 dbgs() << *UseMI; 989 }); 990 } 991} 992 993/// removeIntervalIfEmpty - Check if the live interval of a physical register 994/// is empty, if so remove it and also remove the empty intervals of its 995/// sub-registers. Return true if live interval is removed. 996static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS, 997 const TargetRegisterInfo *TRI) { 998 if (li.empty()) { 999 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) 1000 for (const unsigned* SR = TRI->getSubRegisters(li.reg); *SR; ++SR) { 1001 if (!LIS->hasInterval(*SR)) 1002 continue; 1003 LiveInterval &sli = LIS->getInterval(*SR); 1004 if (sli.empty()) 1005 LIS->removeInterval(*SR); 1006 } 1007 LIS->removeInterval(li.reg); 1008 return true; 1009 } 1010 return false; 1011} 1012 1013/// RemoveDeadDef - If a def of a live interval is now determined dead, remove 1014/// the val# it defines. If the live interval becomes empty, remove it as well. 1015bool RegisterCoalescer::RemoveDeadDef(LiveInterval &li, 1016 MachineInstr *DefMI) { 1017 SlotIndex DefIdx = LIS->getInstructionIndex(DefMI).getRegSlot(); 1018 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx); 1019 if (DefIdx != MLR->valno->def) 1020 return false; 1021 li.removeValNo(MLR->valno); 1022 return removeIntervalIfEmpty(li, LIS, TRI); 1023} 1024 1025void RegisterCoalescer::RemoveCopyFlag(unsigned DstReg, 1026 const MachineInstr *CopyMI) { 1027 SlotIndex DefIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(); 1028 if (LIS->hasInterval(DstReg)) { 1029 LiveInterval &LI = LIS->getInterval(DstReg); 1030 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx)) 1031 if (LR->valno->def == DefIdx) 1032 LR->valno->setCopy(0); 1033 } 1034 if (!TargetRegisterInfo::isPhysicalRegister(DstReg)) 1035 return; 1036 for (const unsigned* AS = TRI->getAliasSet(DstReg); *AS; ++AS) { 1037 if (!LIS->hasInterval(*AS)) 1038 continue; 1039 LiveInterval &LI = LIS->getInterval(*AS); 1040 if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx)) 1041 if (LR->valno->def == DefIdx) 1042 LR->valno->setCopy(0); 1043 } 1044} 1045 1046/// shouldJoinPhys - Return true if a copy involving a physreg should be joined. 1047/// We need to be careful about coalescing a source physical register with a 1048/// virtual register. Once the coalescing is done, it cannot be broken and these 1049/// are not spillable! If the destination interval uses are far away, think 1050/// twice about coalescing them! 1051bool RegisterCoalescer::shouldJoinPhys(CoalescerPair &CP) { 1052 bool Allocatable = LIS->isAllocatable(CP.getDstReg()); 1053 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg()); 1054 1055 /// Always join simple intervals that are defined by a single copy from a 1056 /// reserved register. This doesn't increase register pressure, so it is 1057 /// always beneficial. 1058 if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue()) 1059 return true; 1060 1061 if (!EnablePhysicalJoin) { 1062 DEBUG(dbgs() << "\tPhysreg joins disabled.\n"); 1063 return false; 1064 } 1065 1066 // Only coalesce to allocatable physreg, we don't want to risk modifying 1067 // reserved registers. 1068 if (!Allocatable) { 1069 DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n"); 1070 return false; // Not coalescable. 1071 } 1072 1073 // Don't join with physregs that have a ridiculous number of live 1074 // ranges. The data structure performance is really bad when that 1075 // happens. 1076 if (LIS->hasInterval(CP.getDstReg()) && 1077 LIS->getInterval(CP.getDstReg()).ranges.size() > 1000) { 1078 ++numAborts; 1079 DEBUG(dbgs() 1080 << "\tPhysical register live interval too complicated, abort!\n"); 1081 return false; 1082 } 1083 1084 // FIXME: Why are we skipping this test for partial copies? 1085 // CodeGen/X86/phys_subreg_coalesce-3.ll needs it. 1086 if (!CP.isPartial()) { 1087 const TargetRegisterClass *RC = MRI->getRegClass(CP.getSrcReg()); 1088 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2; 1089 unsigned Length = LIS->getApproximateInstructionCount(JoinVInt); 1090 if (Length > Threshold) { 1091 ++numAborts; 1092 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n"); 1093 return false; 1094 } 1095 } 1096 return true; 1097} 1098 1099/// isWinToJoinCrossClass - Return true if it's profitable to coalesce 1100/// two virtual registers from different register classes. 1101bool 1102RegisterCoalescer::isWinToJoinCrossClass(unsigned SrcReg, 1103 unsigned DstReg, 1104 const TargetRegisterClass *SrcRC, 1105 const TargetRegisterClass *DstRC, 1106 const TargetRegisterClass *NewRC) { 1107 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC); 1108 // This heuristics is good enough in practice, but it's obviously not *right*. 1109 // 4 is a magic number that works well enough for x86, ARM, etc. It filter 1110 // out all but the most restrictive register classes. 1111 if (NewRCCount > 4 || 1112 // Early exit if the function is fairly small, coalesce aggressively if 1113 // that's the case. For really special register classes with 3 or 1114 // fewer registers, be a bit more careful. 1115 (LIS->getFuncInstructionCount() / NewRCCount) < 8) 1116 return true; 1117 LiveInterval &SrcInt = LIS->getInterval(SrcReg); 1118 LiveInterval &DstInt = LIS->getInterval(DstReg); 1119 unsigned SrcSize = LIS->getApproximateInstructionCount(SrcInt); 1120 unsigned DstSize = LIS->getApproximateInstructionCount(DstInt); 1121 1122 // Coalesce aggressively if the intervals are small compared to the number of 1123 // registers in the new class. The number 4 is fairly arbitrary, chosen to be 1124 // less aggressive than the 8 used for the whole function size. 1125 const unsigned ThresSize = 4 * NewRCCount; 1126 if (SrcSize <= ThresSize && DstSize <= ThresSize) 1127 return true; 1128 1129 // Estimate *register use density*. If it doubles or more, abort. 1130 unsigned SrcUses = std::distance(MRI->use_nodbg_begin(SrcReg), 1131 MRI->use_nodbg_end()); 1132 unsigned DstUses = std::distance(MRI->use_nodbg_begin(DstReg), 1133 MRI->use_nodbg_end()); 1134 unsigned NewUses = SrcUses + DstUses; 1135 unsigned NewSize = SrcSize + DstSize; 1136 if (SrcRC != NewRC && SrcSize > ThresSize) { 1137 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); 1138 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount) 1139 return false; 1140 } 1141 if (DstRC != NewRC && DstSize > ThresSize) { 1142 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC); 1143 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount) 1144 return false; 1145 } 1146 return true; 1147} 1148 1149 1150/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 1151/// which are the src/dst of the copy instruction CopyMI. This returns true 1152/// if the copy was successfully coalesced away. If it is not currently 1153/// possible to coalesce this interval, but it may be possible if other 1154/// things get coalesced, then it returns true by reference in 'Again'. 1155bool RegisterCoalescer::JoinCopy(MachineInstr *CopyMI, bool &Again) { 1156 1157 Again = false; 1158 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI)) 1159 return false; // Already done. 1160 1161 DEBUG(dbgs() << LIS->getInstructionIndex(CopyMI) << '\t' << *CopyMI); 1162 1163 CoalescerPair CP(*TII, *TRI); 1164 if (!CP.setRegisters(CopyMI)) { 1165 DEBUG(dbgs() << "\tNot coalescable.\n"); 1166 return false; 1167 } 1168 1169 // If they are already joined we continue. 1170 if (CP.getSrcReg() == CP.getDstReg()) { 1171 markAsJoined(CopyMI); 1172 DEBUG(dbgs() << "\tCopy already coalesced.\n"); 1173 return false; // Not coalescable. 1174 } 1175 1176 // Eliminate undefs. 1177 if (!CP.isPhys() && eliminateUndefCopy(CopyMI, CP)) { 1178 markAsJoined(CopyMI); 1179 DEBUG(dbgs() << "\tEliminated copy of <undef> value.\n"); 1180 return false; // Not coalescable. 1181 } 1182 1183 DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI) 1184 << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSubIdx()) 1185 << "\n"); 1186 1187 // Enforce policies. 1188 if (CP.isPhys()) { 1189 if (!shouldJoinPhys(CP)) { 1190 // Before giving up coalescing, if definition of source is defined by 1191 // trivial computation, try rematerializing it. 1192 if (!CP.isFlipped() && 1193 ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true, 1194 CP.getDstReg(), CopyMI)) 1195 return true; 1196 return false; 1197 } 1198 } else { 1199 // Avoid constraining virtual register regclass too much. 1200 if (CP.isCrossClass()) { 1201 DEBUG(dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n"); 1202 if (DisableCrossClassJoin) { 1203 DEBUG(dbgs() << "\tCross-class joins disabled.\n"); 1204 return false; 1205 } 1206 if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(), 1207 MRI->getRegClass(CP.getSrcReg()), 1208 MRI->getRegClass(CP.getDstReg()), 1209 CP.getNewRC())) { 1210 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n"); 1211 Again = true; // May be possible to coalesce later. 1212 return false; 1213 } 1214 } 1215 1216 // When possible, let DstReg be the larger interval. 1217 if (!CP.getSubIdx() && LIS->getInterval(CP.getSrcReg()).ranges.size() > 1218 LIS->getInterval(CP.getDstReg()).ranges.size()) 1219 CP.flip(); 1220 } 1221 1222 // Okay, attempt to join these two intervals. On failure, this returns false. 1223 // Otherwise, if one of the intervals being joined is a physreg, this method 1224 // always canonicalizes DstInt to be it. The output "SrcInt" will not have 1225 // been modified, so we can use this information below to update aliases. 1226 if (!JoinIntervals(CP)) { 1227 // Coalescing failed. 1228 1229 // If definition of source is defined by trivial computation, try 1230 // rematerializing it. 1231 if (!CP.isFlipped() && 1232 ReMaterializeTrivialDef(LIS->getInterval(CP.getSrcReg()), true, 1233 CP.getDstReg(), CopyMI)) 1234 return true; 1235 1236 // If we can eliminate the copy without merging the live ranges, do so now. 1237 if (!CP.isPartial()) { 1238 if (AdjustCopiesBackFrom(CP, CopyMI) || 1239 RemoveCopyByCommutingDef(CP, CopyMI)) { 1240 markAsJoined(CopyMI); 1241 DEBUG(dbgs() << "\tTrivial!\n"); 1242 return true; 1243 } 1244 } 1245 1246 // Otherwise, we are unable to join the intervals. 1247 DEBUG(dbgs() << "\tInterference!\n"); 1248 Again = true; // May be possible to coalesce later. 1249 return false; 1250 } 1251 1252 // Coalescing to a virtual register that is of a sub-register class of the 1253 // other. Make sure the resulting register is set to the right register class. 1254 if (CP.isCrossClass()) { 1255 ++numCrossRCs; 1256 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); 1257 } 1258 1259 // Remember to delete the copy instruction. 1260 markAsJoined(CopyMI); 1261 1262 UpdateRegDefsUses(CP); 1263 1264 // If we have extended the live range of a physical register, make sure we 1265 // update live-in lists as well. 1266 if (CP.isPhys()) { 1267 SmallVector<MachineBasicBlock*, 16> BlockSeq; 1268 // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the 1269 // ranges for this, and they are preserved. 1270 LiveInterval &SrcInt = LIS->getInterval(CP.getSrcReg()); 1271 for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end(); 1272 I != E; ++I ) { 1273 LIS->findLiveInMBBs(I->start, I->end, BlockSeq); 1274 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) { 1275 MachineBasicBlock &block = *BlockSeq[idx]; 1276 if (!block.isLiveIn(CP.getDstReg())) 1277 block.addLiveIn(CP.getDstReg()); 1278 } 1279 BlockSeq.clear(); 1280 } 1281 } 1282 1283 // SrcReg is guaranteed to be the register whose live interval that is 1284 // being merged. 1285 LIS->removeInterval(CP.getSrcReg()); 1286 1287 // Update regalloc hint. 1288 TRI->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF); 1289 1290 DEBUG({ 1291 LiveInterval &DstInt = LIS->getInterval(CP.getDstReg()); 1292 dbgs() << "\tJoined. Result = "; 1293 DstInt.print(dbgs(), TRI); 1294 dbgs() << "\n"; 1295 }); 1296 1297 ++numJoins; 1298 return true; 1299} 1300 1301/// ComputeUltimateVN - Assuming we are going to join two live intervals, 1302/// compute what the resultant value numbers for each value in the input two 1303/// ranges will be. This is complicated by copies between the two which can 1304/// and will commonly cause multiple value numbers to be merged into one. 1305/// 1306/// VN is the value number that we're trying to resolve. InstDefiningValue 1307/// keeps track of the new InstDefiningValue assignment for the result 1308/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of 1309/// whether a value in this or other is a copy from the opposite set. 1310/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have 1311/// already been assigned. 1312/// 1313/// ThisFromOther[x] - If x is defined as a copy from the other interval, this 1314/// contains the value number the copy is from. 1315/// 1316static unsigned ComputeUltimateVN(VNInfo *VNI, 1317 SmallVector<VNInfo*, 16> &NewVNInfo, 1318 DenseMap<VNInfo*, VNInfo*> &ThisFromOther, 1319 DenseMap<VNInfo*, VNInfo*> &OtherFromThis, 1320 SmallVector<int, 16> &ThisValNoAssignments, 1321 SmallVector<int, 16> &OtherValNoAssignments) { 1322 unsigned VN = VNI->id; 1323 1324 // If the VN has already been computed, just return it. 1325 if (ThisValNoAssignments[VN] >= 0) 1326 return ThisValNoAssignments[VN]; 1327 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers"); 1328 1329 // If this val is not a copy from the other val, then it must be a new value 1330 // number in the destination. 1331 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI); 1332 if (I == ThisFromOther.end()) { 1333 NewVNInfo.push_back(VNI); 1334 return ThisValNoAssignments[VN] = NewVNInfo.size()-1; 1335 } 1336 VNInfo *OtherValNo = I->second; 1337 1338 // Otherwise, this *is* a copy from the RHS. If the other side has already 1339 // been computed, return it. 1340 if (OtherValNoAssignments[OtherValNo->id] >= 0) 1341 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id]; 1342 1343 // Mark this value number as currently being computed, then ask what the 1344 // ultimate value # of the other value is. 1345 ThisValNoAssignments[VN] = -2; 1346 unsigned UltimateVN = 1347 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther, 1348 OtherValNoAssignments, ThisValNoAssignments); 1349 return ThisValNoAssignments[VN] = UltimateVN; 1350} 1351 1352 1353// Find out if we have something like 1354// A = X 1355// B = X 1356// if so, we can pretend this is actually 1357// A = X 1358// B = A 1359// which allows us to coalesce A and B. 1360// VNI is the definition of B. LR is the life range of A that includes 1361// the slot just before B. If we return true, we add "B = X" to DupCopies. 1362// This implies that A dominates B. 1363static bool RegistersDefinedFromSameValue(LiveIntervals &li, 1364 const TargetRegisterInfo &tri, 1365 CoalescerPair &CP, 1366 VNInfo *VNI, 1367 LiveRange *LR, 1368 SmallVector<MachineInstr*, 8> &DupCopies) { 1369 // FIXME: This is very conservative. For example, we don't handle 1370 // physical registers. 1371 1372 MachineInstr *MI = VNI->getCopy(); 1373 1374 if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys()) 1375 return false; 1376 1377 unsigned Dst = MI->getOperand(0).getReg(); 1378 unsigned Src = MI->getOperand(1).getReg(); 1379 1380 if (!TargetRegisterInfo::isVirtualRegister(Src) || 1381 !TargetRegisterInfo::isVirtualRegister(Dst)) 1382 return false; 1383 1384 unsigned A = CP.getDstReg(); 1385 unsigned B = CP.getSrcReg(); 1386 1387 if (B == Dst) 1388 std::swap(A, B); 1389 assert(Dst == A); 1390 1391 VNInfo *Other = LR->valno; 1392 if (!Other->isDefByCopy()) 1393 return false; 1394 const MachineInstr *OtherMI = Other->getCopy(); 1395 1396 if (!OtherMI->isFullCopy()) 1397 return false; 1398 1399 unsigned OtherDst = OtherMI->getOperand(0).getReg(); 1400 unsigned OtherSrc = OtherMI->getOperand(1).getReg(); 1401 1402 if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) || 1403 !TargetRegisterInfo::isVirtualRegister(OtherDst)) 1404 return false; 1405 1406 assert(OtherDst == B); 1407 1408 if (Src != OtherSrc) 1409 return false; 1410 1411 // If the copies use two different value numbers of X, we cannot merge 1412 // A and B. 1413 LiveInterval &SrcInt = li.getInterval(Src); 1414 // getVNInfoBefore returns NULL for undef copies. In this case, the 1415 // optimization is still safe. 1416 if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def)) 1417 return false; 1418 1419 DupCopies.push_back(MI); 1420 1421 return true; 1422} 1423 1424// Loop over the value numbers of the Dst interval and record the values that 1425// are defined by a copy from the Src interval. 1426static void FindValuesCopiedFrom( 1427 LiveIntervals& lis, 1428 const TargetRegisterInfo& tri, 1429 CoalescerPair& CP, 1430 LiveInterval &Dst, LiveInterval &Src, 1431 DenseMap<VNInfo*, VNInfo*>& DstValsDefinedFromSrc, 1432 SmallVector<MachineInstr*, 8>& DupCopies) { 1433 1434 for (LiveInterval::vni_iterator i = Dst.vni_begin(), e = Dst.vni_end(); 1435 i != e; ++i) { 1436 VNInfo *VNI = *i; 1437 if (VNI->isUnused() || !VNI->isDefByCopy()) // Src not defined by a copy? 1438 continue; 1439 1440 // Never join with a register that has EarlyClobber redefs. 1441 if (VNI->hasRedefByEC()) 1442 return false; 1443 1444 // Figure out the value # from the Src. 1445 LiveRange *lr = Src.getLiveRangeContaining(VNI->def.getPrevSlot()); 1446 // The copy could be to an aliased physreg. 1447 if (!lr) continue; 1448 1449 // DstReg is known to be a register in the Dst interval. If the src is 1450 // from the Src interval, we can use its value #. 1451 MachineInstr *MI = VNI->getCopy(); 1452 if (!CP.isCoalescable(MI) && 1453 !RegistersDefinedFromSameValue(lis, tri, CP, VNI, lr, DupCopies)) 1454 continue; 1455 1456 DstValsDefinedFromSrc[VNI] = lr->valno; 1457 } 1458} 1459 1460/// JoinIntervals - Attempt to join these two intervals. On failure, this 1461/// returns false. 1462bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) { 1463 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg()); 1464 DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), TRI); dbgs() << "\n"; }); 1465 1466 // If a live interval is a physical register, check for interference with any 1467 // aliases. The interference check implemented here is a bit more conservative 1468 // than the full interfeence check below. We allow overlapping live ranges 1469 // only when one is a copy of the other. 1470 if (CP.isPhys()) { 1471 // Optimization for reserved registers like ESP. 1472 // We can only merge with a reserved physreg if RHS has a single value that 1473 // is a copy of CP.DstReg(). The live range of the reserved register will 1474 // look like a set of dead defs - we don't properly track the live range of 1475 // reserved registers. 1476 if (RegClassInfo.isReserved(CP.getDstReg())) { 1477 assert(CP.isFlipped() && RHS.containsOneValue() && 1478 "Invalid join with reserved register"); 1479 // Deny any overlapping intervals. This depends on all the reserved 1480 // register live ranges to look like dead defs. 1481 for (const unsigned *AS = TRI->getOverlaps(CP.getDstReg()); *AS; ++AS) { 1482 if (!LIS->hasInterval(*AS)) 1483 continue; 1484 if (RHS.overlaps(LIS->getInterval(*AS))) { 1485 DEBUG(dbgs() << "\t\tInterference: " << PrintReg(*AS, TRI) << '\n'); 1486 return false; 1487 } 1488 } 1489 // Skip any value computations, we are not adding new values to the 1490 // reserved register. Also skip merging the live ranges, the reserved 1491 // register live range doesn't need to be accurate as long as all the 1492 // defs are there. 1493 return true; 1494 } 1495 1496 for (const unsigned *AS = TRI->getAliasSet(CP.getDstReg()); *AS; ++AS){ 1497 if (!LIS->hasInterval(*AS)) 1498 continue; 1499 const LiveInterval &LHS = LIS->getInterval(*AS); 1500 LiveInterval::const_iterator LI = LHS.begin(); 1501 for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end(); 1502 RI != RE; ++RI) { 1503 LI = std::lower_bound(LI, LHS.end(), RI->start); 1504 // Does LHS have an overlapping live range starting before RI? 1505 if ((LI != LHS.begin() && LI[-1].end > RI->start) && 1506 (RI->start != RI->valno->def || 1507 !CP.isCoalescable(LIS->getInstructionFromIndex(RI->start)))) { 1508 DEBUG({ 1509 dbgs() << "\t\tInterference from alias: "; 1510 LHS.print(dbgs(), TRI); 1511 dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n"; 1512 }); 1513 return false; 1514 } 1515 1516 // Check that LHS ranges beginning in this range are copies. 1517 for (; LI != LHS.end() && LI->start < RI->end; ++LI) { 1518 if (LI->start != LI->valno->def || 1519 !CP.isCoalescable(LIS->getInstructionFromIndex(LI->start))) { 1520 DEBUG({ 1521 dbgs() << "\t\tInterference from alias: "; 1522 LHS.print(dbgs(), TRI); 1523 dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n"; 1524 }); 1525 return false; 1526 } 1527 } 1528 } 1529 } 1530 } 1531 1532 // Compute the final value assignment, assuming that the live ranges can be 1533 // coalesced. 1534 SmallVector<int, 16> LHSValNoAssignments; 1535 SmallVector<int, 16> RHSValNoAssignments; 1536 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS; 1537 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS; 1538 SmallVector<VNInfo*, 16> NewVNInfo; 1539 1540 SmallVector<MachineInstr*, 8> DupCopies; 1541 1542 LiveInterval &LHS = LIS->getOrCreateInterval(CP.getDstReg()); 1543 DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), TRI); dbgs() << "\n"; }); 1544 1545 // Build a map of LHS values defined by copies from RHS and vice-versa. 1546 FindValuesCopiedFrom(*LIS, *TRI, CP, LHS, RHS, LHSValsDefinedFromRHS, DupCopies); 1547 FindValuesCopiedFrom(*LIS, *TRI, CP, RHS, LHS, RHSValsDefinedFromLHS, DupCopies); 1548 1549 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1550 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1551 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); 1552 1553 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); 1554 i != e; ++i) { 1555 VNInfo *VNI = *i; 1556 unsigned VN = VNI->id; 1557 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused()) 1558 continue; 1559 ComputeUltimateVN(VNI, NewVNInfo, 1560 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, 1561 LHSValNoAssignments, RHSValNoAssignments); 1562 } 1563 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); 1564 i != e; ++i) { 1565 VNInfo *VNI = *i; 1566 unsigned VN = VNI->id; 1567 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused()) 1568 continue; 1569 // If this value number isn't a copy from the LHS, it's a new number. 1570 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) { 1571 NewVNInfo.push_back(VNI); 1572 RHSValNoAssignments[VN] = NewVNInfo.size()-1; 1573 continue; 1574 } 1575 1576 ComputeUltimateVN(VNI, NewVNInfo, 1577 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, 1578 RHSValNoAssignments, LHSValNoAssignments); 1579 } 1580 1581 // Armed with the mappings of LHS/RHS values to ultimate values, walk the 1582 // interval lists to see if these intervals are coalescable. 1583 LiveInterval::const_iterator I = LHS.begin(); 1584 LiveInterval::const_iterator IE = LHS.end(); 1585 LiveInterval::const_iterator J = RHS.begin(); 1586 LiveInterval::const_iterator JE = RHS.end(); 1587 1588 // Skip ahead until the first place of potential sharing. 1589 if (I != IE && J != JE) { 1590 if (I->start < J->start) { 1591 I = std::upper_bound(I, IE, J->start); 1592 if (I != LHS.begin()) --I; 1593 } else if (J->start < I->start) { 1594 J = std::upper_bound(J, JE, I->start); 1595 if (J != RHS.begin()) --J; 1596 } 1597 } 1598 1599 while (I != IE && J != JE) { 1600 // Determine if these two live ranges overlap. 1601 bool Overlaps; 1602 if (I->start < J->start) { 1603 Overlaps = I->end > J->start; 1604 } else { 1605 Overlaps = J->end > I->start; 1606 } 1607 1608 // If so, check value # info to determine if they are really different. 1609 if (Overlaps) { 1610 // If the live range overlap will map to the same value number in the 1611 // result liverange, we can still coalesce them. If not, we can't. 1612 if (LHSValNoAssignments[I->valno->id] != 1613 RHSValNoAssignments[J->valno->id]) 1614 return false; 1615 // If it's re-defined by an early clobber somewhere in the live range, 1616 // then conservatively abort coalescing. 1617 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC()) 1618 return false; 1619 } 1620 1621 if (I->end < J->end) 1622 ++I; 1623 else 1624 ++J; 1625 } 1626 1627 // Update kill info. Some live ranges are extended due to copy coalescing. 1628 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(), 1629 E = LHSValsDefinedFromRHS.end(); I != E; ++I) { 1630 VNInfo *VNI = I->first; 1631 unsigned LHSValID = LHSValNoAssignments[VNI->id]; 1632 if (VNI->hasPHIKill()) 1633 NewVNInfo[LHSValID]->setHasPHIKill(true); 1634 } 1635 1636 // Update kill info. Some live ranges are extended due to copy coalescing. 1637 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(), 1638 E = RHSValsDefinedFromLHS.end(); I != E; ++I) { 1639 VNInfo *VNI = I->first; 1640 unsigned RHSValID = RHSValNoAssignments[VNI->id]; 1641 if (VNI->hasPHIKill()) 1642 NewVNInfo[RHSValID]->setHasPHIKill(true); 1643 } 1644 1645 if (LHSValNoAssignments.empty()) 1646 LHSValNoAssignments.push_back(-1); 1647 if (RHSValNoAssignments.empty()) 1648 RHSValNoAssignments.push_back(-1); 1649 1650 SmallVector<unsigned, 8> SourceRegisters; 1651 for (SmallVector<MachineInstr*, 8>::iterator I = DupCopies.begin(), 1652 E = DupCopies.end(); I != E; ++I) { 1653 MachineInstr *MI = *I; 1654 1655 // We have pretended that the assignment to B in 1656 // A = X 1657 // B = X 1658 // was actually a copy from A. Now that we decided to coalesce A and B, 1659 // transform the code into 1660 // A = X 1661 // X = X 1662 // and mark the X as coalesced to keep the illusion. 1663 unsigned Src = MI->getOperand(1).getReg(); 1664 SourceRegisters.push_back(Src); 1665 MI->getOperand(0).substVirtReg(Src, 0, *TRI); 1666 1667 markAsJoined(MI); 1668 } 1669 1670 // If B = X was the last use of X in a liverange, we have to shrink it now 1671 // that B = X is gone. 1672 for (SmallVector<unsigned, 8>::iterator I = SourceRegisters.begin(), 1673 E = SourceRegisters.end(); I != E; ++I) { 1674 LIS->shrinkToUses(&LIS->getInterval(*I)); 1675 } 1676 1677 // If we get here, we know that we can coalesce the live ranges. Ask the 1678 // intervals to coalesce themselves now. 1679 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo, 1680 MRI); 1681 return true; 1682} 1683 1684namespace { 1685 // DepthMBBCompare - Comparison predicate that sort first based on the loop 1686 // depth of the basic block (the unsigned), and then on the MBB number. 1687 struct DepthMBBCompare { 1688 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 1689 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 1690 // Deeper loops first 1691 if (LHS.first != RHS.first) 1692 return LHS.first > RHS.first; 1693 1694 // Prefer blocks that are more connected in the CFG. This takes care of 1695 // the most difficult copies first while intervals are short. 1696 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size(); 1697 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size(); 1698 if (cl != cr) 1699 return cl > cr; 1700 1701 // As a last resort, sort by block number. 1702 return LHS.second->getNumber() < RHS.second->getNumber(); 1703 } 1704 }; 1705} 1706 1707void RegisterCoalescer::CopyCoalesceInMBB(MachineBasicBlock *MBB, 1708 std::vector<MachineInstr*> &TryAgain) { 1709 DEBUG(dbgs() << MBB->getName() << ":\n"); 1710 1711 SmallVector<MachineInstr*, 8> VirtCopies; 1712 SmallVector<MachineInstr*, 8> PhysCopies; 1713 SmallVector<MachineInstr*, 8> ImpDefCopies; 1714 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); 1715 MII != E;) { 1716 MachineInstr *Inst = MII++; 1717 1718 // If this isn't a copy nor a extract_subreg, we can't join intervals. 1719 unsigned SrcReg, DstReg; 1720 if (Inst->isCopy()) { 1721 DstReg = Inst->getOperand(0).getReg(); 1722 SrcReg = Inst->getOperand(1).getReg(); 1723 } else if (Inst->isSubregToReg()) { 1724 DstReg = Inst->getOperand(0).getReg(); 1725 SrcReg = Inst->getOperand(2).getReg(); 1726 } else 1727 continue; 1728 1729 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); 1730 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 1731 if (LIS->hasInterval(SrcReg) && LIS->getInterval(SrcReg).empty()) 1732 ImpDefCopies.push_back(Inst); 1733 else if (SrcIsPhys || DstIsPhys) 1734 PhysCopies.push_back(Inst); 1735 else 1736 VirtCopies.push_back(Inst); 1737 } 1738 1739 // Try coalescing implicit copies and insert_subreg <undef> first, 1740 // followed by copies to / from physical registers, then finally copies 1741 // from virtual registers to virtual registers. 1742 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) { 1743 MachineInstr *TheCopy = ImpDefCopies[i]; 1744 bool Again = false; 1745 if (!JoinCopy(TheCopy, Again)) 1746 if (Again) 1747 TryAgain.push_back(TheCopy); 1748 } 1749 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) { 1750 MachineInstr *TheCopy = PhysCopies[i]; 1751 bool Again = false; 1752 if (!JoinCopy(TheCopy, Again)) 1753 if (Again) 1754 TryAgain.push_back(TheCopy); 1755 } 1756 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) { 1757 MachineInstr *TheCopy = VirtCopies[i]; 1758 bool Again = false; 1759 if (!JoinCopy(TheCopy, Again)) 1760 if (Again) 1761 TryAgain.push_back(TheCopy); 1762 } 1763} 1764 1765void RegisterCoalescer::joinIntervals() { 1766 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n"); 1767 1768 std::vector<MachineInstr*> TryAgainList; 1769 if (Loops->empty()) { 1770 // If there are no loops in the function, join intervals in function order. 1771 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); 1772 I != E; ++I) 1773 CopyCoalesceInMBB(I, TryAgainList); 1774 } else { 1775 // Otherwise, join intervals in inner loops before other intervals. 1776 // Unfortunately we can't just iterate over loop hierarchy here because 1777 // there may be more MBB's than BB's. Collect MBB's for sorting. 1778 1779 // Join intervals in the function prolog first. We want to join physical 1780 // registers with virtual registers before the intervals got too long. 1781 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 1782 for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){ 1783 MachineBasicBlock *MBB = I; 1784 MBBs.push_back(std::make_pair(Loops->getLoopDepth(MBB), I)); 1785 } 1786 1787 // Sort by loop depth. 1788 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 1789 1790 // Finally, join intervals in loop nest order. 1791 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 1792 CopyCoalesceInMBB(MBBs[i].second, TryAgainList); 1793 } 1794 1795 // Joining intervals can allow other intervals to be joined. Iteratively join 1796 // until we make no progress. 1797 bool ProgressMade = true; 1798 while (ProgressMade) { 1799 ProgressMade = false; 1800 1801 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { 1802 MachineInstr *&TheCopy = TryAgainList[i]; 1803 if (!TheCopy) 1804 continue; 1805 1806 bool Again = false; 1807 bool Success = JoinCopy(TheCopy, Again); 1808 if (Success || !Again) { 1809 TheCopy= 0; // Mark this one as done. 1810 ProgressMade = true; 1811 } 1812 } 1813 } 1814} 1815 1816void RegisterCoalescer::releaseMemory() { 1817 JoinedCopies.clear(); 1818 ReMatCopies.clear(); 1819 ReMatDefs.clear(); 1820} 1821 1822bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) { 1823 MF = &fn; 1824 MRI = &fn.getRegInfo(); 1825 TM = &fn.getTarget(); 1826 TRI = TM->getRegisterInfo(); 1827 TII = TM->getInstrInfo(); 1828 LIS = &getAnalysis<LiveIntervals>(); 1829 LDV = &getAnalysis<LiveDebugVariables>(); 1830 AA = &getAnalysis<AliasAnalysis>(); 1831 Loops = &getAnalysis<MachineLoopInfo>(); 1832 1833 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n" 1834 << "********** Function: " 1835 << ((Value*)MF->getFunction())->getName() << '\n'); 1836 1837 if (VerifyCoalescing) 1838 MF->verify(this, "Before register coalescing"); 1839 1840 RegClassInfo.runOnMachineFunction(fn); 1841 1842 // Join (coalesce) intervals if requested. 1843 if (EnableJoining) { 1844 joinIntervals(); 1845 DEBUG({ 1846 dbgs() << "********** INTERVALS POST JOINING **********\n"; 1847 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); 1848 I != E; ++I){ 1849 I->second->print(dbgs(), TRI); 1850 dbgs() << "\n"; 1851 } 1852 }); 1853 } 1854 1855 // Perform a final pass over the instructions and compute spill weights 1856 // and remove identity moves. 1857 SmallVector<unsigned, 4> DeadDefs, InflateRegs; 1858 for (MachineFunction::iterator mbbi = MF->begin(), mbbe = MF->end(); 1859 mbbi != mbbe; ++mbbi) { 1860 MachineBasicBlock* mbb = mbbi; 1861 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 1862 mii != mie; ) { 1863 MachineInstr *MI = mii; 1864 if (JoinedCopies.count(MI)) { 1865 // Delete all coalesced copies. 1866 bool DoDelete = true; 1867 assert(MI->isCopyLike() && "Unrecognized copy instruction"); 1868 unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg(); 1869 unsigned DstReg = MI->getOperand(0).getReg(); 1870 1871 // Collect candidates for register class inflation. 1872 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && 1873 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg))) 1874 InflateRegs.push_back(SrcReg); 1875 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 1876 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg))) 1877 InflateRegs.push_back(DstReg); 1878 1879 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 1880 MI->getNumOperands() > 2) 1881 // Do not delete extract_subreg, insert_subreg of physical 1882 // registers unless the definition is dead. e.g. 1883 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1 1884 // or else the scavenger may complain. LowerSubregs will 1885 // delete them later. 1886 DoDelete = false; 1887 1888 if (MI->allDefsAreDead()) { 1889 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && 1890 LIS->hasInterval(SrcReg)) 1891 LIS->shrinkToUses(&LIS->getInterval(SrcReg)); 1892 DoDelete = true; 1893 } 1894 if (!DoDelete) { 1895 // We need the instruction to adjust liveness, so make it a KILL. 1896 if (MI->isSubregToReg()) { 1897 MI->RemoveOperand(3); 1898 MI->RemoveOperand(1); 1899 } 1900 MI->setDesc(TII->get(TargetOpcode::KILL)); 1901 mii = llvm::next(mii); 1902 } else { 1903 LIS->RemoveMachineInstrFromMaps(MI); 1904 mii = mbbi->erase(mii); 1905 ++numPeep; 1906 } 1907 continue; 1908 } 1909 1910 // Now check if this is a remat'ed def instruction which is now dead. 1911 if (ReMatDefs.count(MI)) { 1912 bool isDead = true; 1913 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1914 const MachineOperand &MO = MI->getOperand(i); 1915 if (!MO.isReg()) 1916 continue; 1917 unsigned Reg = MO.getReg(); 1918 if (!Reg) 1919 continue; 1920 DeadDefs.push_back(Reg); 1921 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 1922 // Remat may also enable register class inflation. 1923 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg))) 1924 InflateRegs.push_back(Reg); 1925 } 1926 if (MO.isDead()) 1927 continue; 1928 if (TargetRegisterInfo::isPhysicalRegister(Reg) || 1929 !MRI->use_nodbg_empty(Reg)) { 1930 isDead = false; 1931 break; 1932 } 1933 } 1934 if (isDead) { 1935 while (!DeadDefs.empty()) { 1936 unsigned DeadDef = DeadDefs.back(); 1937 DeadDefs.pop_back(); 1938 RemoveDeadDef(LIS->getInterval(DeadDef), MI); 1939 } 1940 LIS->RemoveMachineInstrFromMaps(mii); 1941 mii = mbbi->erase(mii); 1942 continue; 1943 } else 1944 DeadDefs.clear(); 1945 } 1946 1947 ++mii; 1948 1949 // Check for now unnecessary kill flags. 1950 if (LIS->isNotInMIMap(MI)) continue; 1951 SlotIndex DefIdx = LIS->getInstructionIndex(MI).getRegSlot(); 1952 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1953 MachineOperand &MO = MI->getOperand(i); 1954 if (!MO.isReg() || !MO.isKill()) continue; 1955 unsigned reg = MO.getReg(); 1956 if (!reg || !LIS->hasInterval(reg)) continue; 1957 if (!LIS->getInterval(reg).killedAt(DefIdx)) { 1958 MO.setIsKill(false); 1959 continue; 1960 } 1961 // When leaving a kill flag on a physreg, check if any subregs should 1962 // remain alive. 1963 if (!TargetRegisterInfo::isPhysicalRegister(reg)) 1964 continue; 1965 for (const unsigned *SR = TRI->getSubRegisters(reg); 1966 unsigned S = *SR; ++SR) 1967 if (LIS->hasInterval(S) && LIS->getInterval(S).liveAt(DefIdx)) 1968 MI->addRegisterDefined(S, TRI); 1969 } 1970 } 1971 } 1972 1973 // After deleting a lot of copies, register classes may be less constrained. 1974 // Removing sub-register opreands may alow GR32_ABCD -> GR32 and DPR_VFP2 -> 1975 // DPR inflation. 1976 array_pod_sort(InflateRegs.begin(), InflateRegs.end()); 1977 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()), 1978 InflateRegs.end()); 1979 DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size() << " regs.\n"); 1980 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) { 1981 unsigned Reg = InflateRegs[i]; 1982 if (MRI->reg_nodbg_empty(Reg)) 1983 continue; 1984 if (MRI->recomputeRegClass(Reg, *TM)) { 1985 DEBUG(dbgs() << PrintReg(Reg) << " inflated to " 1986 << MRI->getRegClass(Reg)->getName() << '\n'); 1987 ++NumInflated; 1988 } 1989 } 1990 1991 DEBUG(dump()); 1992 DEBUG(LDV->dump()); 1993 if (VerifyCoalescing) 1994 MF->verify(this, "After register coalescing"); 1995 return true; 1996} 1997 1998/// print - Implement the dump method. 1999void RegisterCoalescer::print(raw_ostream &O, const Module* m) const { 2000 LIS->print(O, m); 2001} 2002