RegisterCoalescer.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)//===-- RegisterCoalescer.h - Register Coalescing Interface -----*- C++ -*-===// 2d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// 3d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// The LLVM Compiler Infrastructure 4d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// 5d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 6d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// License. See LICENSE.TXT for details. 7d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// 8d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)//===----------------------------------------------------------------------===// 9d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// 10d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// This file contains the abstract interface for register coalescers, 11d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// allowing them to interact with and query register allocators. 12d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)// 13d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)//===----------------------------------------------------------------------===// 14d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 15d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#ifndef LLVM_CODEGEN_REGISTER_COALESCER_H 1668043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles)#define LLVM_CODEGEN_REGISTER_COALESCER_H 17d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 18d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)namespace llvm { 19d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 20d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) class MachineInstr; 21d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) class TargetRegisterInfo; 22d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) class TargetRegisterClass; 23d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) class TargetInstrInfo; 24d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 25d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// CoalescerPair - A helper class for register coalescers. When deciding if 26d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// two registers can be coalesced, CoalescerPair can determine if a copy 27d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// instruction would become an identity copy after coalescing. 28d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) class CoalescerPair { 2968043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) const TargetRegisterInfo &TRI; 30d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 31d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// DstReg - The register that will be left after coalescing. It can be a 32d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// virtual or physical register. 33d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned DstReg; 34d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 35d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// SrcReg - the virtual register that will be coalesced into dstReg. 36d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned SrcReg; 37d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 38d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// DstIdx - The sub-register index of the old DstReg in the new coalesced 39d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// register. 40d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned DstIdx; 41d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 42d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced 43d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// register. 44d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned SrcIdx; 45d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 46d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// Partial - True when the original copy was a partial subregister copy. 47d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool Partial; 48d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 49d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// CrossClass - True when both regs are virtual, and newRC is constrained. 50d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool CrossClass; 51d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 52d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// Flipped - True when DstReg and SrcReg are reversed from the original 53d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// copy instruction. 54d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool Flipped; 55d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 56d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// NewRC - The register class of the coalesced register, or NULL if DstReg 57d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// is a physreg. This register class may be a super-register of both 58d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// SrcReg and DstReg. 59d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) const TargetRegisterClass *NewRC; 60d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 61d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) public: 62d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) CoalescerPair(const TargetRegisterInfo &tri) 63d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 64d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {} 65d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 66d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// Create a CoalescerPair representing a virtreg-to-physreg copy. 67d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// No need to call setRegisters(). 68d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) CoalescerPair(unsigned VirtReg, unsigned PhysReg, 69d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) const TargetRegisterInfo &tri) 70d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 71d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) Partial(false), CrossClass(false), Flipped(false), NewRC(nullptr) {} 72d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 73d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// setRegisters - set registers to match the copy instruction MI. Return 74d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// false if MI is not a coalescable copy instruction. 75d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool setRegisters(const MachineInstr*); 76d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 77d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible 78d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// because DstReg is a physical register, or SubIdx is set. 79d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool flip(); 80d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 81d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// isCoalescable - Return true if MI is a copy instruction that will become 82d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// an identity copy after coalescing. 83d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool isCoalescable(const MachineInstr*) const; 84d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 85d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// isPhys - Return true if DstReg is a physical register. 86d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool isPhys() const { return !NewRC; } 87d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 88d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// isPartial - Return true if the original copy instruction did not copy 89d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// the full register, but was a subreg operation. 90d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool isPartial() const { return Partial; } 91d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 92d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// isCrossClass - Return true if DstReg is virtual and NewRC is a smaller 93d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// register class than DstReg's. 94d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool isCrossClass() const { return CrossClass; } 95d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 96d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// isFlipped - Return true when getSrcReg is the register being defined by 97d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// the original copy instruction. 98d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) bool isFlipped() const { return Flipped; } 99d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 100d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// getDstReg - Return the register (virtual or physical) that will remain 101d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// after coalescing. 102d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned getDstReg() const { return DstReg; } 103d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 104d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// getSrcReg - Return the virtual register that will be coalesced away. 105d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned getSrcReg() const { return SrcReg; } 106d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 107d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// getDstIdx - Return the subregister index that DstReg will be coalesced 108d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// into, or 0. 109d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) unsigned getDstIdx() const { return DstIdx; } 110d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 111d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// getSrcIdx - Return the subregister index that SrcReg will be coalesced 11268043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) /// into, or 0. 11368043e1e95eeb07d5cae7aca370b26518b0867d6Torne (Richard Coles) unsigned getSrcIdx() const { return SrcIdx; } 114d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 115d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) /// getNewRC - Return the register class of the coalesced register. 116d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) const TargetRegisterClass *getNewRC() const { return NewRC; } 117d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) }; 118d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)} // End llvm namespace 119d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles) 120d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)#endif 121d0247b1b59f9c528cb6df88b4f2b9afaf80d181eTorne (Richard Coles)