ScheduleDAGInstrs.cpp revision a78d3228e8b2a14915ea9908dbaaf2c934803e11
1//===---- ScheduleDAGInstrs.cpp - MachineInstr Rescheduling ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the ScheduleDAGInstrs class, which implements re-scheduling 11// of MachineInstrs. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "sched-instrs" 16#include "llvm/Operator.h" 17#include "llvm/Analysis/AliasAnalysis.h" 18#include "llvm/Analysis/ValueTracking.h" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "llvm/CodeGen/MachineFunctionPass.h" 21#include "llvm/CodeGen/MachineMemOperand.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/PseudoSourceValue.h" 24#include "llvm/CodeGen/RegisterPressure.h" 25#include "llvm/CodeGen/ScheduleDAGILP.h" 26#include "llvm/CodeGen/ScheduleDAGInstrs.h" 27#include "llvm/MC/MCInstrItineraries.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetRegisterInfo.h" 31#include "llvm/Target/TargetSubtargetInfo.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/Format.h" 35#include "llvm/Support/raw_ostream.h" 36#include "llvm/ADT/SmallSet.h" 37#include "llvm/ADT/SmallPtrSet.h" 38using namespace llvm; 39 40static cl::opt<bool> EnableAASchedMI("enable-aa-sched-mi", cl::Hidden, 41 cl::ZeroOrMore, cl::init(false), 42 cl::desc("Enable use of AA during MI GAD construction")); 43 44ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, 45 const MachineLoopInfo &mli, 46 const MachineDominatorTree &mdt, 47 bool IsPostRAFlag, 48 LiveIntervals *lis) 49 : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis), 50 IsPostRA(IsPostRAFlag), CanHandleTerminators(false), FirstDbgValue(0) { 51 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); 52 DbgValues.clear(); 53 assert(!(IsPostRA && MRI.getNumVirtRegs()) && 54 "Virtual registers must be removed prior to PostRA scheduling"); 55 56 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 57 SchedModel.init(*ST.getSchedModel(), &ST, TII); 58} 59 60/// getUnderlyingObjectFromInt - This is the function that does the work of 61/// looking through basic ptrtoint+arithmetic+inttoptr sequences. 62static const Value *getUnderlyingObjectFromInt(const Value *V) { 63 do { 64 if (const Operator *U = dyn_cast<Operator>(V)) { 65 // If we find a ptrtoint, we can transfer control back to the 66 // regular getUnderlyingObjectFromInt. 67 if (U->getOpcode() == Instruction::PtrToInt) 68 return U->getOperand(0); 69 // If we find an add of a constant or a multiplied value, it's 70 // likely that the other operand will lead us to the base 71 // object. We don't have to worry about the case where the 72 // object address is somehow being computed by the multiply, 73 // because our callers only care when the result is an 74 // identifiable object. 75 if (U->getOpcode() != Instruction::Add || 76 (!isa<ConstantInt>(U->getOperand(1)) && 77 Operator::getOpcode(U->getOperand(1)) != Instruction::Mul)) 78 return V; 79 V = U->getOperand(0); 80 } else { 81 return V; 82 } 83 assert(V->getType()->isIntegerTy() && "Unexpected operand type!"); 84 } while (1); 85} 86 87/// getUnderlyingObject - This is a wrapper around GetUnderlyingObject 88/// and adds support for basic ptrtoint+arithmetic+inttoptr sequences. 89static const Value *getUnderlyingObject(const Value *V) { 90 // First just call Value::getUnderlyingObject to let it do what it does. 91 do { 92 V = GetUnderlyingObject(V); 93 // If it found an inttoptr, use special code to continue climing. 94 if (Operator::getOpcode(V) != Instruction::IntToPtr) 95 break; 96 const Value *O = getUnderlyingObjectFromInt(cast<User>(V)->getOperand(0)); 97 // If that succeeded in finding a pointer, continue the search. 98 if (!O->getType()->isPointerTy()) 99 break; 100 V = O; 101 } while (1); 102 return V; 103} 104 105/// getUnderlyingObjectForInstr - If this machine instr has memory reference 106/// information and it can be tracked to a normal reference to a known 107/// object, return the Value for that object. Otherwise return null. 108static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI, 109 const MachineFrameInfo *MFI, 110 bool &MayAlias) { 111 MayAlias = true; 112 if (!MI->hasOneMemOperand() || 113 !(*MI->memoperands_begin())->getValue() || 114 (*MI->memoperands_begin())->isVolatile()) 115 return 0; 116 117 const Value *V = (*MI->memoperands_begin())->getValue(); 118 if (!V) 119 return 0; 120 121 V = getUnderlyingObject(V); 122 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 123 // For now, ignore PseudoSourceValues which may alias LLVM IR values 124 // because the code that uses this function has no way to cope with 125 // such aliases. 126 if (PSV->isAliased(MFI)) 127 return 0; 128 129 MayAlias = PSV->mayAlias(MFI); 130 return V; 131 } 132 133 if (isIdentifiedObject(V)) 134 return V; 135 136 return 0; 137} 138 139void ScheduleDAGInstrs::startBlock(MachineBasicBlock *bb) { 140 BB = bb; 141} 142 143void ScheduleDAGInstrs::finishBlock() { 144 // Subclasses should no longer refer to the old block. 145 BB = 0; 146} 147 148/// Initialize the map with the number of registers. 149void Reg2SUnitsMap::setRegLimit(unsigned Limit) { 150 PhysRegSet.setUniverse(Limit); 151 SUnits.resize(Limit); 152} 153 154/// Clear the map without deallocating storage. 155void Reg2SUnitsMap::clear() { 156 for (const_iterator I = reg_begin(), E = reg_end(); I != E; ++I) { 157 SUnits[*I].clear(); 158 } 159 PhysRegSet.clear(); 160} 161 162/// Initialize the DAG and common scheduler state for the current scheduling 163/// region. This does not actually create the DAG, only clears it. The 164/// scheduling driver may call BuildSchedGraph multiple times per scheduling 165/// region. 166void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb, 167 MachineBasicBlock::iterator begin, 168 MachineBasicBlock::iterator end, 169 unsigned endcount) { 170 assert(bb == BB && "startBlock should set BB"); 171 RegionBegin = begin; 172 RegionEnd = end; 173 EndIndex = endcount; 174 MISUnitMap.clear(); 175 176 ScheduleDAG::clearDAG(); 177} 178 179/// Close the current scheduling region. Don't clear any state in case the 180/// driver wants to refer to the previous scheduling region. 181void ScheduleDAGInstrs::exitRegion() { 182 // Nothing to do. 183} 184 185/// addSchedBarrierDeps - Add dependencies from instructions in the current 186/// list of instructions being scheduled to scheduling barrier by adding 187/// the exit SU to the register defs and use list. This is because we want to 188/// make sure instructions which define registers that are either used by 189/// the terminator or are live-out are properly scheduled. This is 190/// especially important when the definition latency of the return value(s) 191/// are too high to be hidden by the branch or when the liveout registers 192/// used by instructions in the fallthrough block. 193void ScheduleDAGInstrs::addSchedBarrierDeps() { 194 MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : 0; 195 ExitSU.setInstr(ExitMI); 196 bool AllDepKnown = ExitMI && 197 (ExitMI->isCall() || ExitMI->isBarrier()); 198 if (ExitMI && AllDepKnown) { 199 // If it's a call or a barrier, add dependencies on the defs and uses of 200 // instruction. 201 for (unsigned i = 0, e = ExitMI->getNumOperands(); i != e; ++i) { 202 const MachineOperand &MO = ExitMI->getOperand(i); 203 if (!MO.isReg() || MO.isDef()) continue; 204 unsigned Reg = MO.getReg(); 205 if (Reg == 0) continue; 206 207 if (TRI->isPhysicalRegister(Reg)) 208 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1)); 209 else { 210 assert(!IsPostRA && "Virtual register encountered after regalloc."); 211 addVRegUseDeps(&ExitSU, i); 212 } 213 } 214 } else { 215 // For others, e.g. fallthrough, conditional branch, assume the exit 216 // uses all the registers that are livein to the successor blocks. 217 assert(Uses.empty() && "Uses in set before adding deps?"); 218 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), 219 SE = BB->succ_end(); SI != SE; ++SI) 220 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), 221 E = (*SI)->livein_end(); I != E; ++I) { 222 unsigned Reg = *I; 223 if (!Uses.contains(Reg)) 224 Uses[Reg].push_back(PhysRegSUOper(&ExitSU, -1)); 225 } 226 } 227} 228 229/// MO is an operand of SU's instruction that defines a physical register. Add 230/// data dependencies from SU to any uses of the physical register. 231void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { 232 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 233 assert(MO.isDef() && "expect physreg def"); 234 235 // Ask the target if address-backscheduling is desirable, and if so how much. 236 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 237 238 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 239 Alias.isValid(); ++Alias) { 240 if (!Uses.contains(*Alias)) 241 continue; 242 std::vector<PhysRegSUOper> &UseList = Uses[*Alias]; 243 for (unsigned i = 0, e = UseList.size(); i != e; ++i) { 244 SUnit *UseSU = UseList[i].SU; 245 if (UseSU == SU) 246 continue; 247 248 SDep dep(SU, SDep::Data, *Alias); 249 250 // Adjust the dependence latency using operand def/use information, 251 // then allow the target to perform its own adjustments. 252 int UseOp = UseList[i].OpIdx; 253 MachineInstr *RegUse = UseOp < 0 ? 0 : UseSU->getInstr(); 254 dep.setLatency( 255 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, 256 RegUse, UseOp, /*FindMin=*/false)); 257 dep.setMinLatency( 258 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, 259 RegUse, UseOp, /*FindMin=*/true)); 260 261 ST.adjustSchedDependency(SU, UseSU, dep); 262 UseSU->addPred(dep); 263 } 264 } 265} 266 267/// addPhysRegDeps - Add register dependencies (data, anti, and output) from 268/// this SUnit to following instructions in the same scheduling region that 269/// depend the physical register referenced at OperIdx. 270void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { 271 const MachineInstr *MI = SU->getInstr(); 272 const MachineOperand &MO = MI->getOperand(OperIdx); 273 274 // Optionally add output and anti dependencies. For anti 275 // dependencies we use a latency of 0 because for a multi-issue 276 // target we want to allow the defining instruction to issue 277 // in the same cycle as the using instruction. 278 // TODO: Using a latency of 1 here for output dependencies assumes 279 // there's no cost for reusing registers. 280 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output; 281 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true); 282 Alias.isValid(); ++Alias) { 283 if (!Defs.contains(*Alias)) 284 continue; 285 std::vector<PhysRegSUOper> &DefList = Defs[*Alias]; 286 for (unsigned i = 0, e = DefList.size(); i != e; ++i) { 287 SUnit *DefSU = DefList[i].SU; 288 if (DefSU == &ExitSU) 289 continue; 290 if (DefSU != SU && 291 (Kind != SDep::Output || !MO.isDead() || 292 !DefSU->getInstr()->registerDefIsDead(*Alias))) { 293 if (Kind == SDep::Anti) 294 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); 295 else { 296 SDep Dep(SU, Kind, /*Reg=*/*Alias); 297 unsigned OutLatency = 298 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); 299 Dep.setMinLatency(OutLatency); 300 Dep.setLatency(OutLatency); 301 DefSU->addPred(Dep); 302 } 303 } 304 } 305 } 306 307 if (!MO.isDef()) { 308 // Either insert a new Reg2SUnits entry with an empty SUnits list, or 309 // retrieve the existing SUnits list for this register's uses. 310 // Push this SUnit on the use list. 311 Uses[MO.getReg()].push_back(PhysRegSUOper(SU, OperIdx)); 312 } 313 else { 314 addPhysRegDataDeps(SU, OperIdx); 315 316 // Either insert a new Reg2SUnits entry with an empty SUnits list, or 317 // retrieve the existing SUnits list for this register's defs. 318 std::vector<PhysRegSUOper> &DefList = Defs[MO.getReg()]; 319 320 // clear this register's use list 321 if (Uses.contains(MO.getReg())) 322 Uses[MO.getReg()].clear(); 323 324 if (!MO.isDead()) 325 DefList.clear(); 326 327 // Calls will not be reordered because of chain dependencies (see 328 // below). Since call operands are dead, calls may continue to be added 329 // to the DefList making dependence checking quadratic in the size of 330 // the block. Instead, we leave only one call at the back of the 331 // DefList. 332 if (SU->isCall) { 333 while (!DefList.empty() && DefList.back().SU->isCall) 334 DefList.pop_back(); 335 } 336 // Defs are pushed in the order they are visited and never reordered. 337 DefList.push_back(PhysRegSUOper(SU, OperIdx)); 338 } 339} 340 341/// addVRegDefDeps - Add register output and data dependencies from this SUnit 342/// to instructions that occur later in the same scheduling region if they read 343/// from or write to the virtual register defined at OperIdx. 344/// 345/// TODO: Hoist loop induction variable increments. This has to be 346/// reevaluated. Generally, IV scheduling should be done before coalescing. 347void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { 348 const MachineInstr *MI = SU->getInstr(); 349 unsigned Reg = MI->getOperand(OperIdx).getReg(); 350 351 // Singly defined vregs do not have output/anti dependencies. 352 // The current operand is a def, so we have at least one. 353 // Check here if there are any others... 354 if (MRI.hasOneDef(Reg)) 355 return; 356 357 // Add output dependence to the next nearest def of this vreg. 358 // 359 // Unless this definition is dead, the output dependence should be 360 // transitively redundant with antidependencies from this definition's 361 // uses. We're conservative for now until we have a way to guarantee the uses 362 // are not eliminated sometime during scheduling. The output dependence edge 363 // is also useful if output latency exceeds def-use latency. 364 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); 365 if (DefI == VRegDefs.end()) 366 VRegDefs.insert(VReg2SUnit(Reg, SU)); 367 else { 368 SUnit *DefSU = DefI->SU; 369 if (DefSU != SU && DefSU != &ExitSU) { 370 SDep Dep(SU, SDep::Output, Reg); 371 unsigned OutLatency = 372 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()); 373 Dep.setMinLatency(OutLatency); 374 Dep.setLatency(OutLatency); 375 DefSU->addPred(Dep); 376 } 377 DefI->SU = SU; 378 } 379} 380 381/// addVRegUseDeps - Add a register data dependency if the instruction that 382/// defines the virtual register used at OperIdx is mapped to an SUnit. Add a 383/// register antidependency from this SUnit to instructions that occur later in 384/// the same scheduling region if they write the virtual register. 385/// 386/// TODO: Handle ExitSU "uses" properly. 387void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { 388 MachineInstr *MI = SU->getInstr(); 389 unsigned Reg = MI->getOperand(OperIdx).getReg(); 390 391 // Lookup this operand's reaching definition. 392 assert(LIS && "vreg dependencies requires LiveIntervals"); 393 LiveRangeQuery LRQ(LIS->getInterval(Reg), LIS->getInstructionIndex(MI)); 394 VNInfo *VNI = LRQ.valueIn(); 395 396 // VNI will be valid because MachineOperand::readsReg() is checked by caller. 397 assert(VNI && "No value to read by operand"); 398 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def); 399 // Phis and other noninstructions (after coalescing) have a NULL Def. 400 if (Def) { 401 SUnit *DefSU = getSUnit(Def); 402 if (DefSU) { 403 // The reaching Def lives within this scheduling region. 404 // Create a data dependence. 405 SDep dep(DefSU, SDep::Data, Reg); 406 // Adjust the dependence latency using operand def/use information, then 407 // allow the target to perform its own adjustments. 408 int DefOp = Def->findRegisterDefOperandIdx(Reg); 409 dep.setLatency( 410 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false)); 411 dep.setMinLatency( 412 SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true)); 413 414 const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); 415 ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep)); 416 SU->addPred(dep); 417 } 418 } 419 420 // Add antidependence to the following def of the vreg it uses. 421 VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg); 422 if (DefI != VRegDefs.end() && DefI->SU != SU) 423 DefI->SU->addPred(SDep(SU, SDep::Anti, Reg)); 424} 425 426/// Return true if MI is an instruction we are unable to reason about 427/// (like a call or something with unmodeled side effects). 428static inline bool isGlobalMemoryObject(AliasAnalysis *AA, MachineInstr *MI) { 429 if (MI->isCall() || MI->hasUnmodeledSideEffects() || 430 (MI->hasOrderedMemoryRef() && 431 (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) 432 return true; 433 return false; 434} 435 436// This MI might have either incomplete info, or known to be unsafe 437// to deal with (i.e. volatile object). 438static inline bool isUnsafeMemoryObject(MachineInstr *MI, 439 const MachineFrameInfo *MFI) { 440 if (!MI || MI->memoperands_empty()) 441 return true; 442 // We purposefully do no check for hasOneMemOperand() here 443 // in hope to trigger an assert downstream in order to 444 // finish implementation. 445 if ((*MI->memoperands_begin())->isVolatile() || 446 MI->hasUnmodeledSideEffects()) 447 return true; 448 449 const Value *V = (*MI->memoperands_begin())->getValue(); 450 if (!V) 451 return true; 452 453 V = getUnderlyingObject(V); 454 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) { 455 // Similarly to getUnderlyingObjectForInstr: 456 // For now, ignore PseudoSourceValues which may alias LLVM IR values 457 // because the code that uses this function has no way to cope with 458 // such aliases. 459 if (PSV->isAliased(MFI)) 460 return true; 461 } 462 // Does this pointer refer to a distinct and identifiable object? 463 if (!isIdentifiedObject(V)) 464 return true; 465 466 return false; 467} 468 469/// This returns true if the two MIs need a chain edge betwee them. 470/// If these are not even memory operations, we still may need 471/// chain deps between them. The question really is - could 472/// these two MIs be reordered during scheduling from memory dependency 473/// point of view. 474static bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI, 475 MachineInstr *MIa, 476 MachineInstr *MIb) { 477 // Cover a trivial case - no edge is need to itself. 478 if (MIa == MIb) 479 return false; 480 481 if (isUnsafeMemoryObject(MIa, MFI) || isUnsafeMemoryObject(MIb, MFI)) 482 return true; 483 484 // If we are dealing with two "normal" loads, we do not need an edge 485 // between them - they could be reordered. 486 if (!MIa->mayStore() && !MIb->mayStore()) 487 return false; 488 489 // To this point analysis is generic. From here on we do need AA. 490 if (!AA) 491 return true; 492 493 MachineMemOperand *MMOa = *MIa->memoperands_begin(); 494 MachineMemOperand *MMOb = *MIb->memoperands_begin(); 495 496 // FIXME: Need to handle multiple memory operands to support all targets. 497 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) 498 llvm_unreachable("Multiple memory operands."); 499 500 // The following interface to AA is fashioned after DAGCombiner::isAlias 501 // and operates with MachineMemOperand offset with some important 502 // assumptions: 503 // - LLVM fundamentally assumes flat address spaces. 504 // - MachineOperand offset can *only* result from legalization and 505 // cannot affect queries other than the trivial case of overlap 506 // checking. 507 // - These offsets never wrap and never step outside 508 // of allocated objects. 509 // - There should never be any negative offsets here. 510 // 511 // FIXME: Modify API to hide this math from "user" 512 // FIXME: Even before we go to AA we can reason locally about some 513 // memory objects. It can save compile time, and possibly catch some 514 // corner cases not currently covered. 515 516 assert ((MMOa->getOffset() >= 0) && "Negative MachineMemOperand offset"); 517 assert ((MMOb->getOffset() >= 0) && "Negative MachineMemOperand offset"); 518 519 int64_t MinOffset = std::min(MMOa->getOffset(), MMOb->getOffset()); 520 int64_t Overlapa = MMOa->getSize() + MMOa->getOffset() - MinOffset; 521 int64_t Overlapb = MMOb->getSize() + MMOb->getOffset() - MinOffset; 522 523 AliasAnalysis::AliasResult AAResult = AA->alias( 524 AliasAnalysis::Location(MMOa->getValue(), Overlapa, 525 MMOa->getTBAAInfo()), 526 AliasAnalysis::Location(MMOb->getValue(), Overlapb, 527 MMOb->getTBAAInfo())); 528 529 return (AAResult != AliasAnalysis::NoAlias); 530} 531 532/// This recursive function iterates over chain deps of SUb looking for 533/// "latest" node that needs a chain edge to SUa. 534static unsigned 535iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI, 536 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth, 537 SmallPtrSet<const SUnit*, 16> &Visited) { 538 if (!SUa || !SUb || SUb == ExitSU) 539 return *Depth; 540 541 // Remember visited nodes. 542 if (!Visited.insert(SUb)) 543 return *Depth; 544 // If there is _some_ dependency already in place, do not 545 // descend any further. 546 // TODO: Need to make sure that if that dependency got eliminated or ignored 547 // for any reason in the future, we would not violate DAG topology. 548 // Currently it does not happen, but makes an implicit assumption about 549 // future implementation. 550 // 551 // Independently, if we encounter node that is some sort of global 552 // object (like a call) we already have full set of dependencies to it 553 // and we can stop descending. 554 if (SUa->isSucc(SUb) || 555 isGlobalMemoryObject(AA, SUb->getInstr())) 556 return *Depth; 557 558 // If we do need an edge, or we have exceeded depth budget, 559 // add that edge to the predecessors chain of SUb, 560 // and stop descending. 561 if (*Depth > 200 || 562 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) { 563 SUb->addPred(SDep(SUa, SDep::MayAliasMem)); 564 return *Depth; 565 } 566 // Track current depth. 567 (*Depth)++; 568 // Iterate over chain dependencies only. 569 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end(); 570 I != E; ++I) 571 if (I->isCtrl()) 572 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited); 573 return *Depth; 574} 575 576/// This function assumes that "downward" from SU there exist 577/// tail/leaf of already constructed DAG. It iterates downward and 578/// checks whether SU can be aliasing any node dominated 579/// by it. 580static void adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, 581 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, 582 unsigned LatencyToLoad) { 583 if (!SU) 584 return; 585 586 SmallPtrSet<const SUnit*, 16> Visited; 587 unsigned Depth = 0; 588 589 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end(); 590 I != IE; ++I) { 591 if (SU == *I) 592 continue; 593 if (MIsNeedChainEdge(AA, MFI, SU->getInstr(), (*I)->getInstr())) { 594 SDep Dep(SU, SDep::MayAliasMem); 595 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0); 596 (*I)->addPred(Dep); 597 } 598 // Now go through all the chain successors and iterate from them. 599 // Keep track of visited nodes. 600 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(), 601 JE = (*I)->Succs.end(); J != JE; ++J) 602 if (J->isCtrl()) 603 iterateChainSucc (AA, MFI, SU, J->getSUnit(), 604 ExitSU, &Depth, Visited); 605 } 606} 607 608/// Check whether two objects need a chain edge, if so, add it 609/// otherwise remember the rejected SU. 610static inline 611void addChainDependency (AliasAnalysis *AA, const MachineFrameInfo *MFI, 612 SUnit *SUa, SUnit *SUb, 613 std::set<SUnit *> &RejectList, 614 unsigned TrueMemOrderLatency = 0, 615 bool isNormalMemory = false) { 616 // If this is a false dependency, 617 // do not add the edge, but rememeber the rejected node. 618 if (!EnableAASchedMI || 619 MIsNeedChainEdge(AA, MFI, SUa->getInstr(), SUb->getInstr())) { 620 SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier); 621 Dep.setLatency(TrueMemOrderLatency); 622 SUb->addPred(Dep); 623 } 624 else { 625 // Duplicate entries should be ignored. 626 RejectList.insert(SUb); 627 DEBUG(dbgs() << "\tReject chain dep between SU(" 628 << SUa->NodeNum << ") and SU(" 629 << SUb->NodeNum << ")\n"); 630 } 631} 632 633/// Create an SUnit for each real instruction, numbered in top-down toplological 634/// order. The instruction order A < B, implies that no edge exists from B to A. 635/// 636/// Map each real instruction to its SUnit. 637/// 638/// After initSUnits, the SUnits vector cannot be resized and the scheduler may 639/// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs 640/// instead of pointers. 641/// 642/// MachineScheduler relies on initSUnits numbering the nodes by their order in 643/// the original instruction list. 644void ScheduleDAGInstrs::initSUnits() { 645 // We'll be allocating one SUnit for each real instruction in the region, 646 // which is contained within a basic block. 647 SUnits.reserve(BB->size()); 648 649 for (MachineBasicBlock::iterator I = RegionBegin; I != RegionEnd; ++I) { 650 MachineInstr *MI = I; 651 if (MI->isDebugValue()) 652 continue; 653 654 SUnit *SU = newSUnit(MI); 655 MISUnitMap[MI] = SU; 656 657 SU->isCall = MI->isCall(); 658 SU->isCommutable = MI->isCommutable(); 659 660 // Assign the Latency field of SU using target-provided information. 661 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr()); 662 } 663} 664 665/// If RegPressure is non null, compute register pressure as a side effect. The 666/// DAG builder is an efficient place to do it because it already visits 667/// operands. 668void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA, 669 RegPressureTracker *RPTracker) { 670 // Create an SUnit for each real instruction. 671 initSUnits(); 672 673 // We build scheduling units by walking a block's instruction list from bottom 674 // to top. 675 676 // Remember where a generic side-effecting instruction is as we procede. 677 SUnit *BarrierChain = 0, *AliasChain = 0; 678 679 // Memory references to specific known memory locations are tracked 680 // so that they can be given more precise dependencies. We track 681 // separately the known memory locations that may alias and those 682 // that are known not to alias 683 std::map<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs; 684 std::map<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses; 685 std::set<SUnit*> RejectMemNodes; 686 687 // Remove any stale debug info; sometimes BuildSchedGraph is called again 688 // without emitting the info from the previous call. 689 DbgValues.clear(); 690 FirstDbgValue = NULL; 691 692 assert(Defs.empty() && Uses.empty() && 693 "Only BuildGraph should update Defs/Uses"); 694 Defs.setRegLimit(TRI->getNumRegs()); 695 Uses.setRegLimit(TRI->getNumRegs()); 696 697 assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs"); 698 // FIXME: Allow SparseSet to reserve space for the creation of virtual 699 // registers during scheduling. Don't artificially inflate the Universe 700 // because we want to assert that vregs are not created during DAG building. 701 VRegDefs.setUniverse(MRI.getNumVirtRegs()); 702 703 // Model data dependencies between instructions being scheduled and the 704 // ExitSU. 705 addSchedBarrierDeps(); 706 707 // Walk the list of instructions, from bottom moving up. 708 MachineInstr *PrevMI = NULL; 709 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin; 710 MII != MIE; --MII) { 711 MachineInstr *MI = prior(MII); 712 if (MI && PrevMI) { 713 DbgValues.push_back(std::make_pair(PrevMI, MI)); 714 PrevMI = NULL; 715 } 716 717 if (MI->isDebugValue()) { 718 PrevMI = MI; 719 continue; 720 } 721 if (RPTracker) { 722 RPTracker->recede(); 723 assert(RPTracker->getPos() == prior(MII) && "RPTracker can't find MI"); 724 } 725 726 assert((!MI->isTerminator() || CanHandleTerminators) && !MI->isLabel() && 727 "Cannot schedule terminators or labels!"); 728 729 SUnit *SU = MISUnitMap[MI]; 730 assert(SU && "No SUnit mapped to this MI"); 731 732 // Add register-based dependencies (data, anti, and output). 733 for (unsigned j = 0, n = MI->getNumOperands(); j != n; ++j) { 734 const MachineOperand &MO = MI->getOperand(j); 735 if (!MO.isReg()) continue; 736 unsigned Reg = MO.getReg(); 737 if (Reg == 0) continue; 738 739 if (TRI->isPhysicalRegister(Reg)) 740 addPhysRegDeps(SU, j); 741 else { 742 assert(!IsPostRA && "Virtual register encountered!"); 743 if (MO.isDef()) 744 addVRegDefDeps(SU, j); 745 else if (MO.readsReg()) // ignore undef operands 746 addVRegUseDeps(SU, j); 747 } 748 } 749 750 // Add chain dependencies. 751 // Chain dependencies used to enforce memory order should have 752 // latency of 0 (except for true dependency of Store followed by 753 // aliased Load... we estimate that with a single cycle of latency 754 // assuming the hardware will bypass) 755 // Note that isStoreToStackSlot and isLoadFromStackSLot are not usable 756 // after stack slots are lowered to actual addresses. 757 // TODO: Use an AliasAnalysis and do real alias-analysis queries, and 758 // produce more precise dependence information. 759 unsigned TrueMemOrderLatency = MI->mayStore() ? 1 : 0; 760 if (isGlobalMemoryObject(AA, MI)) { 761 // Be conservative with these and add dependencies on all memory 762 // references, even those that are known to not alias. 763 for (std::map<const Value *, SUnit *>::iterator I = 764 NonAliasMemDefs.begin(), E = NonAliasMemDefs.end(); I != E; ++I) { 765 I->second->addPred(SDep(SU, SDep::Barrier)); 766 } 767 for (std::map<const Value *, std::vector<SUnit *> >::iterator I = 768 NonAliasMemUses.begin(), E = NonAliasMemUses.end(); I != E; ++I) { 769 for (unsigned i = 0, e = I->second.size(); i != e; ++i) { 770 SDep Dep(SU, SDep::Barrier); 771 Dep.setLatency(TrueMemOrderLatency); 772 I->second[i]->addPred(Dep); 773 } 774 } 775 // Add SU to the barrier chain. 776 if (BarrierChain) 777 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 778 BarrierChain = SU; 779 // This is a barrier event that acts as a pivotal node in the DAG, 780 // so it is safe to clear list of exposed nodes. 781 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 782 TrueMemOrderLatency); 783 RejectMemNodes.clear(); 784 NonAliasMemDefs.clear(); 785 NonAliasMemUses.clear(); 786 787 // fall-through 788 new_alias_chain: 789 // Chain all possibly aliasing memory references though SU. 790 if (AliasChain) { 791 unsigned ChainLatency = 0; 792 if (AliasChain->getInstr()->mayLoad()) 793 ChainLatency = TrueMemOrderLatency; 794 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes, 795 ChainLatency); 796 } 797 AliasChain = SU; 798 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) 799 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes, 800 TrueMemOrderLatency); 801 for (std::map<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(), 802 E = AliasMemDefs.end(); I != E; ++I) 803 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes); 804 for (std::map<const Value *, std::vector<SUnit *> >::iterator I = 805 AliasMemUses.begin(), E = AliasMemUses.end(); I != E; ++I) { 806 for (unsigned i = 0, e = I->second.size(); i != e; ++i) 807 addChainDependency(AA, MFI, SU, I->second[i], RejectMemNodes, 808 TrueMemOrderLatency); 809 } 810 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 811 TrueMemOrderLatency); 812 PendingLoads.clear(); 813 AliasMemDefs.clear(); 814 AliasMemUses.clear(); 815 } else if (MI->mayStore()) { 816 bool MayAlias = true; 817 if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) { 818 // A store to a specific PseudoSourceValue. Add precise dependencies. 819 // Record the def in MemDefs, first adding a dep if there is 820 // an existing def. 821 std::map<const Value *, SUnit *>::iterator I = 822 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); 823 std::map<const Value *, SUnit *>::iterator IE = 824 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); 825 if (I != IE) { 826 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 827 0, true); 828 I->second = SU; 829 } else { 830 if (MayAlias) 831 AliasMemDefs[V] = SU; 832 else 833 NonAliasMemDefs[V] = SU; 834 } 835 // Handle the uses in MemUses, if there are any. 836 std::map<const Value *, std::vector<SUnit *> >::iterator J = 837 ((MayAlias) ? AliasMemUses.find(V) : NonAliasMemUses.find(V)); 838 std::map<const Value *, std::vector<SUnit *> >::iterator JE = 839 ((MayAlias) ? AliasMemUses.end() : NonAliasMemUses.end()); 840 if (J != JE) { 841 for (unsigned i = 0, e = J->second.size(); i != e; ++i) 842 addChainDependency(AA, MFI, SU, J->second[i], RejectMemNodes, 843 TrueMemOrderLatency, true); 844 J->second.clear(); 845 } 846 if (MayAlias) { 847 // Add dependencies from all the PendingLoads, i.e. loads 848 // with no underlying object. 849 for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) 850 addChainDependency(AA, MFI, SU, PendingLoads[k], RejectMemNodes, 851 TrueMemOrderLatency); 852 // Add dependence on alias chain, if needed. 853 if (AliasChain) 854 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes); 855 // But we also should check dependent instructions for the 856 // SU in question. 857 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, 858 TrueMemOrderLatency); 859 } 860 // Add dependence on barrier chain, if needed. 861 // There is no point to check aliasing on barrier event. Even if 862 // SU and barrier _could_ be reordered, they should not. In addition, 863 // we have lost all RejectMemNodes below barrier. 864 if (BarrierChain) 865 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 866 } else { 867 // Treat all other stores conservatively. 868 goto new_alias_chain; 869 } 870 871 if (!ExitSU.isPred(SU)) 872 // Push store's up a bit to avoid them getting in between cmp 873 // and branches. 874 ExitSU.addPred(SDep(SU, SDep::Artificial)); 875 } else if (MI->mayLoad()) { 876 bool MayAlias = true; 877 if (MI->isInvariantLoad(AA)) { 878 // Invariant load, no chain dependencies needed! 879 } else { 880 if (const Value *V = 881 getUnderlyingObjectForInstr(MI, MFI, MayAlias)) { 882 // A load from a specific PseudoSourceValue. Add precise dependencies. 883 std::map<const Value *, SUnit *>::iterator I = 884 ((MayAlias) ? AliasMemDefs.find(V) : NonAliasMemDefs.find(V)); 885 std::map<const Value *, SUnit *>::iterator IE = 886 ((MayAlias) ? AliasMemDefs.end() : NonAliasMemDefs.end()); 887 if (I != IE) 888 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes, 0, true); 889 if (MayAlias) 890 AliasMemUses[V].push_back(SU); 891 else 892 NonAliasMemUses[V].push_back(SU); 893 } else { 894 // A load with no underlying object. Depend on all 895 // potentially aliasing stores. 896 for (std::map<const Value *, SUnit *>::iterator I = 897 AliasMemDefs.begin(), E = AliasMemDefs.end(); I != E; ++I) 898 addChainDependency(AA, MFI, SU, I->second, RejectMemNodes); 899 900 PendingLoads.push_back(SU); 901 MayAlias = true; 902 } 903 if (MayAlias) 904 adjustChainDeps(AA, MFI, SU, &ExitSU, RejectMemNodes, /*Latency=*/0); 905 // Add dependencies on alias and barrier chains, if needed. 906 if (MayAlias && AliasChain) 907 addChainDependency(AA, MFI, SU, AliasChain, RejectMemNodes); 908 if (BarrierChain) 909 BarrierChain->addPred(SDep(SU, SDep::Barrier)); 910 } 911 } 912 } 913 if (PrevMI) 914 FirstDbgValue = PrevMI; 915 916 Defs.clear(); 917 Uses.clear(); 918 VRegDefs.clear(); 919 PendingLoads.clear(); 920} 921 922void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const { 923#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 924 SU->getInstr()->dump(); 925#endif 926} 927 928std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const { 929 std::string s; 930 raw_string_ostream oss(s); 931 if (SU == &EntrySU) 932 oss << "<entry>"; 933 else if (SU == &ExitSU) 934 oss << "<exit>"; 935 else 936 SU->getInstr()->print(oss); 937 return oss.str(); 938} 939 940/// Return the basic block label. It is not necessarilly unique because a block 941/// contains multiple scheduling regions. But it is fine for visualization. 942std::string ScheduleDAGInstrs::getDAGName() const { 943 return "dag." + BB->getFullName(); 944} 945 946namespace { 947/// \brief Manage the stack used by a reverse depth-first search over the DAG. 948class SchedDAGReverseDFS { 949 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack; 950public: 951 bool isComplete() const { return DFSStack.empty(); } 952 953 void follow(const SUnit *SU) { 954 DFSStack.push_back(std::make_pair(SU, SU->Preds.begin())); 955 } 956 void advance() { ++DFSStack.back().second; } 957 958 void backtrack() { DFSStack.pop_back(); } 959 960 const SUnit *getCurr() const { return DFSStack.back().first; } 961 962 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; } 963 964 SUnit::const_pred_iterator getPredEnd() const { 965 return getCurr()->Preds.end(); 966 } 967}; 968} // anonymous 969 970void ScheduleDAGILP::resize(unsigned NumSUnits) { 971 ILPValues.resize(NumSUnits); 972} 973 974ILPValue ScheduleDAGILP::getILP(const SUnit *SU) { 975 return ILPValues[SU->NodeNum]; 976} 977 978// A leaf node has an ILP of 1/1. 979static ILPValue initILP(const SUnit *SU) { 980 unsigned Cnt = SU->getInstr()->isTransient() ? 0 : 1; 981 return ILPValue(Cnt, 1 + SU->getDepth()); 982} 983 984/// Compute an ILP metric for all nodes in the subDAG reachable via depth-first 985/// search from this root. 986void ScheduleDAGILP::computeILP(const SUnit *Root) { 987 if (!IsBottomUp) 988 llvm_unreachable("Top-down ILP metric is unimplemnted"); 989 990 SchedDAGReverseDFS DFS; 991 // Mark a node visited by validating it. 992 ILPValues[Root->NodeNum] = initILP(Root); 993 DFS.follow(Root); 994 for (;;) { 995 // Traverse the leftmost path as far as possible. 996 while (DFS.getPred() != DFS.getPredEnd()) { 997 const SUnit *PredSU = DFS.getPred()->getSUnit(); 998 DFS.advance(); 999 // If the pred is already valid, skip it. 1000 if (ILPValues[PredSU->NodeNum].isValid()) 1001 continue; 1002 ILPValues[PredSU->NodeNum] = initILP(PredSU); 1003 DFS.follow(PredSU); 1004 } 1005 // Visit the top of the stack in postorder and backtrack. 1006 unsigned PredCount = ILPValues[DFS.getCurr()->NodeNum].InstrCount; 1007 DFS.backtrack(); 1008 if (DFS.isComplete()) 1009 break; 1010 // Add the recently finished predecessor's bottom-up descendent count. 1011 ILPValues[DFS.getCurr()->NodeNum].InstrCount += PredCount; 1012 } 1013} 1014 1015#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1016void ILPValue::print(raw_ostream &OS) const { 1017 if (!isValid()) 1018 OS << "BADILP"; 1019 OS << InstrCount << " / " << Cycles << " = " 1020 << format("%g", ((double)InstrCount / Cycles)); 1021} 1022 1023void ILPValue::dump() const { 1024 dbgs() << *this << '\n'; 1025} 1026 1027namespace llvm { 1028 1029raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val) { 1030 Val.print(OS); 1031 return OS; 1032} 1033 1034} // namespace llvm 1035#endif // !NDEBUG || LLVM_ENABLE_DUMP 1036