FastISel.cpp revision 016c5829a5dacc3b28cb264b4b6d166552e3d568
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/Operator.h" 47#include "llvm/CodeGen/Analysis.h" 48#include "llvm/CodeGen/FastISel.h" 49#include "llvm/CodeGen/FunctionLoweringInfo.h" 50#include "llvm/CodeGen/MachineInstrBuilder.h" 51#include "llvm/CodeGen/MachineModuleInfo.h" 52#include "llvm/CodeGen/MachineRegisterInfo.h" 53#include "llvm/Analysis/DebugInfo.h" 54#include "llvm/Analysis/Loads.h" 55#include "llvm/Target/TargetData.h" 56#include "llvm/Target/TargetInstrInfo.h" 57#include "llvm/Target/TargetLowering.h" 58#include "llvm/Target/TargetMachine.h" 59#include "llvm/Support/ErrorHandling.h" 60#include "llvm/Support/Debug.h" 61using namespace llvm; 62 63/// startNewBlock - Set the current block to which generated machine 64/// instructions will be appended, and clear the local CSE map. 65/// 66void FastISel::startNewBlock() { 67 LocalValueMap.clear(); 68 69 // Start out as null, meaining no local-value instructions have 70 // been emitted. 71 LastLocalValue = 0; 72 73 // Advance the last local value past any EH_LABEL instructions. 74 MachineBasicBlock::iterator 75 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end(); 76 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { 77 LastLocalValue = I; 78 ++I; 79 } 80} 81 82bool FastISel::hasTrivialKill(const Value *V) const { 83 // Don't consider constants or arguments to have trivial kills. 84 const Instruction *I = dyn_cast<Instruction>(V); 85 if (!I) 86 return false; 87 88 // No-op casts are trivially coalesced by fast-isel. 89 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 90 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 91 !hasTrivialKill(Cast->getOperand(0))) 92 return false; 93 94 // Only instructions with a single use in the same basic block are considered 95 // to have trivial kills. 96 return I->hasOneUse() && 97 !(I->getOpcode() == Instruction::BitCast || 98 I->getOpcode() == Instruction::PtrToInt || 99 I->getOpcode() == Instruction::IntToPtr) && 100 cast<Instruction>(*I->use_begin())->getParent() == I->getParent(); 101} 102 103unsigned FastISel::getRegForValue(const Value *V) { 104 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 105 // Don't handle non-simple values in FastISel. 106 if (!RealVT.isSimple()) 107 return 0; 108 109 // Ignore illegal types. We must do this before looking up the value 110 // in ValueMap because Arguments are given virtual registers regardless 111 // of whether FastISel can handle them. 112 MVT VT = RealVT.getSimpleVT(); 113 if (!TLI.isTypeLegal(VT)) { 114 // Handle integer promotions, though, because they're common and easy. 115 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 116 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 117 else 118 return 0; 119 } 120 121 // Look up the value to see if we already have a register for it. We 122 // cache values defined by Instructions across blocks, and other values 123 // only locally. This is because Instructions already have the SSA 124 // def-dominates-use requirement enforced. 125 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 126 if (I != FuncInfo.ValueMap.end()) 127 return I->second; 128 129 unsigned Reg = LocalValueMap[V]; 130 if (Reg != 0) 131 return Reg; 132 133 // In bottom-up mode, just create the virtual register which will be used 134 // to hold the value. It will be materialized later. 135 if (isa<Instruction>(V) && 136 (!isa<AllocaInst>(V) || 137 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) 138 return FuncInfo.InitializeRegForValue(V); 139 140 SavePoint SaveInsertPt = enterLocalValueArea(); 141 142 // Materialize the value in a register. Emit any instructions in the 143 // local value area. 144 Reg = materializeRegForValue(V, VT); 145 146 leaveLocalValueArea(SaveInsertPt); 147 148 return Reg; 149} 150 151/// materializeRegForValue - Helper for getRegForValue. This function is 152/// called when the value isn't already available in a register and must 153/// be materialized with new instructions. 154unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 155 unsigned Reg = 0; 156 157 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 158 if (CI->getValue().getActiveBits() <= 64) 159 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 160 } else if (isa<AllocaInst>(V)) { 161 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 162 } else if (isa<ConstantPointerNull>(V)) { 163 // Translate this as an integer zero so that it can be 164 // local-CSE'd with actual integer zeros. 165 Reg = 166 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 167 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 168 if (CF->isNullValue()) { 169 Reg = TargetMaterializeFloatZero(CF); 170 } else { 171 // Try to emit the constant directly. 172 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 173 } 174 175 if (!Reg) { 176 // Try to emit the constant by using an integer constant with a cast. 177 const APFloat &Flt = CF->getValueAPF(); 178 EVT IntVT = TLI.getPointerTy(); 179 180 uint64_t x[2]; 181 uint32_t IntBitWidth = IntVT.getSizeInBits(); 182 bool isExact; 183 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 184 APFloat::rmTowardZero, &isExact); 185 if (isExact) { 186 APInt IntVal(IntBitWidth, 2, x); 187 188 unsigned IntegerReg = 189 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 190 if (IntegerReg != 0) 191 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 192 IntegerReg, /*Kill=*/false); 193 } 194 } 195 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 196 if (!SelectOperator(Op, Op->getOpcode())) 197 if (!isa<Instruction>(Op) || 198 !TargetSelectInstruction(cast<Instruction>(Op))) 199 return 0; 200 Reg = lookUpRegForValue(Op); 201 } else if (isa<UndefValue>(V)) { 202 Reg = createResultReg(TLI.getRegClassFor(VT)); 203 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 204 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 205 } 206 207 // If target-independent code couldn't handle the value, give target-specific 208 // code a try. 209 if (!Reg && isa<Constant>(V)) 210 Reg = TargetMaterializeConstant(cast<Constant>(V)); 211 212 // Don't cache constant materializations in the general ValueMap. 213 // To do so would require tracking what uses they dominate. 214 if (Reg != 0) { 215 LocalValueMap[V] = Reg; 216 LastLocalValue = MRI.getVRegDef(Reg); 217 } 218 return Reg; 219} 220 221unsigned FastISel::lookUpRegForValue(const Value *V) { 222 // Look up the value to see if we already have a register for it. We 223 // cache values defined by Instructions across blocks, and other values 224 // only locally. This is because Instructions already have the SSA 225 // def-dominates-use requirement enforced. 226 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 227 if (I != FuncInfo.ValueMap.end()) 228 return I->second; 229 return LocalValueMap[V]; 230} 231 232/// UpdateValueMap - Update the value map to include the new mapping for this 233/// instruction, or insert an extra copy to get the result in a previous 234/// determined register. 235/// NOTE: This is only necessary because we might select a block that uses 236/// a value before we select the block that defines the value. It might be 237/// possible to fix this by selecting blocks in reverse postorder. 238void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { 239 if (!isa<Instruction>(I)) { 240 LocalValueMap[I] = Reg; 241 return; 242 } 243 244 unsigned &AssignedReg = FuncInfo.ValueMap[I]; 245 if (AssignedReg == 0) 246 // Use the new register. 247 AssignedReg = Reg; 248 else if (Reg != AssignedReg) { 249 // Arrange for uses of AssignedReg to be replaced by uses of Reg. 250 for (unsigned i = 0; i < NumRegs; i++) 251 FuncInfo.RegFixups[AssignedReg+i] = Reg+i; 252 253 AssignedReg = Reg; 254 } 255} 256 257std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 258 unsigned IdxN = getRegForValue(Idx); 259 if (IdxN == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return std::pair<unsigned, bool>(0, false); 262 263 bool IdxNIsKill = hasTrivialKill(Idx); 264 265 // If the index is smaller or larger than intptr_t, truncate or extend it. 266 MVT PtrVT = TLI.getPointerTy(); 267 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 268 if (IdxVT.bitsLT(PtrVT)) { 269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 270 IdxN, IdxNIsKill); 271 IdxNIsKill = true; 272 } 273 else if (IdxVT.bitsGT(PtrVT)) { 274 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 275 IdxN, IdxNIsKill); 276 IdxNIsKill = true; 277 } 278 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 279} 280 281void FastISel::recomputeInsertPt() { 282 if (getLastLocalValue()) { 283 FuncInfo.InsertPt = getLastLocalValue(); 284 FuncInfo.MBB = FuncInfo.InsertPt->getParent(); 285 ++FuncInfo.InsertPt; 286 } else 287 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI(); 288 289 // Now skip past any EH_LABELs, which must remain at the beginning. 290 while (FuncInfo.InsertPt != FuncInfo.MBB->end() && 291 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 292 ++FuncInfo.InsertPt; 293} 294 295/// recomputeDebugLocForMaterializedRegs - Recompute debug location for 296/// very first instruction in a basic block. All instructions emitted 297/// to materialize registers do not have location information, see 298/// enterLocalValueArea(), becase they may not be emited at the right 299/// location. 300void FastISel::recomputeDebugLocForMaterializedRegs() { 301 if (!getLastLocalValue()) 302 return; 303 MachineInstr *First = FuncInfo.MBB->getFirstNonPHI(); 304 if (!First->getDebugLoc().isUnknown()) 305 return; 306 307 for (MachineBasicBlock::iterator I = FuncInfo.MBB->begin(), 308 E = FuncInfo.MBB->end(); I != E; ++I) { 309 DebugLoc DL = I->getDebugLoc(); 310 if (!DL.isUnknown()) { 311 First->setDebugLoc(DL); 312 return; 313 } 314 } 315} 316 317FastISel::SavePoint FastISel::enterLocalValueArea() { 318 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; 319 DebugLoc OldDL = DL; 320 recomputeInsertPt(); 321 DL = DebugLoc(); 322 SavePoint SP = { OldInsertPt, OldDL }; 323 return SP; 324} 325 326void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { 327 if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) 328 LastLocalValue = llvm::prior(FuncInfo.InsertPt); 329 330 // Restore the previous insert position. 331 FuncInfo.InsertPt = OldInsertPt.InsertPt; 332 DL = OldInsertPt.DL; 333} 334 335/// SelectBinaryOp - Select and emit code for a binary operator instruction, 336/// which has an opcode which directly corresponds to the given ISD opcode. 337/// 338bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 339 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 340 if (VT == MVT::Other || !VT.isSimple()) 341 // Unhandled type. Halt "fast" selection and bail. 342 return false; 343 344 // We only handle legal types. For example, on x86-32 the instruction 345 // selector contains all of the 64-bit instructions from x86-64, 346 // under the assumption that i64 won't be used if the target doesn't 347 // support it. 348 if (!TLI.isTypeLegal(VT)) { 349 // MVT::i1 is special. Allow AND, OR, or XOR because they 350 // don't require additional zeroing, which makes them easy. 351 if (VT == MVT::i1 && 352 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 353 ISDOpcode == ISD::XOR)) 354 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 355 else 356 return false; 357 } 358 359 // Check if the first operand is a constant, and handle it as "ri". At -O0, 360 // we don't have anything that canonicalizes operand order. 361 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0))) 362 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) { 363 unsigned Op1 = getRegForValue(I->getOperand(1)); 364 if (Op1 == 0) return false; 365 366 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 367 368 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, 369 Op1IsKill, CI->getZExtValue(), 370 VT.getSimpleVT()); 371 if (ResultReg == 0) return false; 372 373 // We successfully emitted code for the given LLVM Instruction. 374 UpdateValueMap(I, ResultReg); 375 return true; 376 } 377 378 379 unsigned Op0 = getRegForValue(I->getOperand(0)); 380 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail. 381 return false; 382 383 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 384 385 // Check if the second operand is a constant and handle it appropriately. 386 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 387 uint64_t Imm = CI->getZExtValue(); 388 389 // Transform "sdiv exact X, 8" -> "sra X, 3". 390 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && 391 cast<BinaryOperator>(I)->isExact() && 392 isPowerOf2_64(Imm)) { 393 Imm = Log2_64(Imm); 394 ISDOpcode = ISD::SRA; 395 } 396 397 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 398 Op0IsKill, Imm, VT.getSimpleVT()); 399 if (ResultReg == 0) return false; 400 401 // We successfully emitted code for the given LLVM Instruction. 402 UpdateValueMap(I, ResultReg); 403 return true; 404 } 405 406 // Check if the second operand is a constant float. 407 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 408 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 409 ISDOpcode, Op0, Op0IsKill, CF); 410 if (ResultReg != 0) { 411 // We successfully emitted code for the given LLVM Instruction. 412 UpdateValueMap(I, ResultReg); 413 return true; 414 } 415 } 416 417 unsigned Op1 = getRegForValue(I->getOperand(1)); 418 if (Op1 == 0) 419 // Unhandled operand. Halt "fast" selection and bail. 420 return false; 421 422 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 423 424 // Now we have both operands in registers. Emit the instruction. 425 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 426 ISDOpcode, 427 Op0, Op0IsKill, 428 Op1, Op1IsKill); 429 if (ResultReg == 0) 430 // Target-specific code wasn't able to find a machine opcode for 431 // the given ISD opcode and type. Halt "fast" selection and bail. 432 return false; 433 434 // We successfully emitted code for the given LLVM Instruction. 435 UpdateValueMap(I, ResultReg); 436 return true; 437} 438 439bool FastISel::SelectGetElementPtr(const User *I) { 440 unsigned N = getRegForValue(I->getOperand(0)); 441 if (N == 0) 442 // Unhandled operand. Halt "fast" selection and bail. 443 return false; 444 445 bool NIsKill = hasTrivialKill(I->getOperand(0)); 446 447 const Type *Ty = I->getOperand(0)->getType(); 448 MVT VT = TLI.getPointerTy(); 449 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 450 E = I->op_end(); OI != E; ++OI) { 451 const Value *Idx = *OI; 452 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 453 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 454 if (Field) { 455 // N = N + Offset 456 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 457 // FIXME: This can be optimized by combining the add with a 458 // subsequent one. 459 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 460 if (N == 0) 461 // Unhandled operand. Halt "fast" selection and bail. 462 return false; 463 NIsKill = true; 464 } 465 Ty = StTy->getElementType(Field); 466 } else { 467 Ty = cast<SequentialType>(Ty)->getElementType(); 468 469 // If this is a constant subscript, handle it quickly. 470 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 471 if (CI->isZero()) continue; 472 uint64_t Offs = 473 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 474 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 475 if (N == 0) 476 // Unhandled operand. Halt "fast" selection and bail. 477 return false; 478 NIsKill = true; 479 continue; 480 } 481 482 // N = N + Idx * ElementSize; 483 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 484 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 485 unsigned IdxN = Pair.first; 486 bool IdxNIsKill = Pair.second; 487 if (IdxN == 0) 488 // Unhandled operand. Halt "fast" selection and bail. 489 return false; 490 491 if (ElementSize != 1) { 492 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 493 if (IdxN == 0) 494 // Unhandled operand. Halt "fast" selection and bail. 495 return false; 496 IdxNIsKill = true; 497 } 498 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 499 if (N == 0) 500 // Unhandled operand. Halt "fast" selection and bail. 501 return false; 502 } 503 } 504 505 // We successfully emitted code for the given LLVM Instruction. 506 UpdateValueMap(I, N); 507 return true; 508} 509 510bool FastISel::SelectCall(const User *I) { 511 const CallInst *Call = cast<CallInst>(I); 512 513 // Handle simple inline asms. 514 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getArgOperand(0))) { 515 // Don't attempt to handle constraints. 516 if (!IA->getConstraintString().empty()) 517 return false; 518 519 unsigned ExtraInfo = 0; 520 if (IA->hasSideEffects()) 521 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 522 if (IA->isAlignStack()) 523 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 524 525 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 526 TII.get(TargetOpcode::INLINEASM)) 527 .addExternalSymbol(IA->getAsmString().c_str()) 528 .addImm(ExtraInfo); 529 return true; 530 } 531 532 const Function *F = Call->getCalledFunction(); 533 if (!F) return false; 534 535 // Handle selected intrinsic function calls. 536 switch (F->getIntrinsicID()) { 537 default: break; 538 case Intrinsic::dbg_declare: { 539 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call); 540 if (!DIVariable(DI->getVariable()).Verify() || 541 !FuncInfo.MF->getMMI().hasDebugInfo()) 542 return true; 543 544 const Value *Address = DI->getAddress(); 545 if (!Address || isa<UndefValue>(Address) || isa<AllocaInst>(Address)) 546 return true; 547 548 unsigned Reg = 0; 549 unsigned Offset = 0; 550 if (const Argument *Arg = dyn_cast<Argument>(Address)) { 551 if (Arg->hasByValAttr()) { 552 // Byval arguments' frame index is recorded during argument lowering. 553 // Use this info directly. 554 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 555 if (Offset) 556 Reg = TRI.getFrameRegister(*FuncInfo.MF); 557 } 558 } 559 if (!Reg) 560 Reg = getRegForValue(Address); 561 562 if (Reg) 563 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 564 TII.get(TargetOpcode::DBG_VALUE)) 565 .addReg(Reg, RegState::Debug).addImm(Offset) 566 .addMetadata(DI->getVariable()); 567 return true; 568 } 569 case Intrinsic::dbg_value: { 570 // This form of DBG_VALUE is target-independent. 571 const DbgValueInst *DI = cast<DbgValueInst>(Call); 572 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 573 const Value *V = DI->getValue(); 574 if (!V) { 575 // Currently the optimizer can produce this; insert an undef to 576 // help debugging. Probably the optimizer should not do this. 577 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 578 .addReg(0U).addImm(DI->getOffset()) 579 .addMetadata(DI->getVariable()); 580 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 581 if (CI->getBitWidth() > 64) 582 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 583 .addCImm(CI).addImm(DI->getOffset()) 584 .addMetadata(DI->getVariable()); 585 else 586 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 587 .addImm(CI->getZExtValue()).addImm(DI->getOffset()) 588 .addMetadata(DI->getVariable()); 589 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 590 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 591 .addFPImm(CF).addImm(DI->getOffset()) 592 .addMetadata(DI->getVariable()); 593 } else if (unsigned Reg = lookUpRegForValue(V)) { 594 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 595 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 596 .addMetadata(DI->getVariable()); 597 } else { 598 // We can't yet handle anything else here because it would require 599 // generating code, thus altering codegen because of debug info. 600 DEBUG(dbgs() << "Dropping debug info for " << DI); 601 } 602 return true; 603 } 604 case Intrinsic::eh_exception: { 605 EVT VT = TLI.getValueType(Call->getType()); 606 if (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)!=TargetLowering::Expand) 607 break; 608 609 assert(FuncInfo.MBB->isLandingPad() && 610 "Call to eh.exception not in landing pad!"); 611 unsigned Reg = TLI.getExceptionAddressRegister(); 612 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 613 unsigned ResultReg = createResultReg(RC); 614 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 615 ResultReg).addReg(Reg); 616 UpdateValueMap(Call, ResultReg); 617 return true; 618 } 619 case Intrinsic::eh_selector: { 620 EVT VT = TLI.getValueType(Call->getType()); 621 if (TLI.getOperationAction(ISD::EHSELECTION, VT) != TargetLowering::Expand) 622 break; 623 if (FuncInfo.MBB->isLandingPad()) 624 AddCatchInfo(*Call, &FuncInfo.MF->getMMI(), FuncInfo.MBB); 625 else { 626#ifndef NDEBUG 627 FuncInfo.CatchInfoLost.insert(Call); 628#endif 629 // FIXME: Mark exception selector register as live in. Hack for PR1508. 630 unsigned Reg = TLI.getExceptionSelectorRegister(); 631 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 632 } 633 634 unsigned Reg = TLI.getExceptionSelectorRegister(); 635 EVT SrcVT = TLI.getPointerTy(); 636 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 637 unsigned ResultReg = createResultReg(RC); 638 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 639 ResultReg).addReg(Reg); 640 641 bool ResultRegIsKill = hasTrivialKill(Call); 642 643 // Cast the register to the type of the selector. 644 if (SrcVT.bitsGT(MVT::i32)) 645 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 646 ResultReg, ResultRegIsKill); 647 else if (SrcVT.bitsLT(MVT::i32)) 648 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 649 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); 650 if (ResultReg == 0) 651 // Unhandled operand. Halt "fast" selection and bail. 652 return false; 653 654 UpdateValueMap(Call, ResultReg); 655 656 return true; 657 } 658 case Intrinsic::objectsize: { 659 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1)); 660 unsigned long long Res = CI->isZero() ? -1ULL : 0; 661 Constant *ResCI = ConstantInt::get(Call->getType(), Res); 662 unsigned ResultReg = getRegForValue(ResCI); 663 if (ResultReg == 0) 664 return false; 665 UpdateValueMap(Call, ResultReg); 666 return true; 667 } 668 } 669 670 // An arbitrary call. Bail. 671 return false; 672} 673 674bool FastISel::SelectCast(const User *I, unsigned Opcode) { 675 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 676 EVT DstVT = TLI.getValueType(I->getType()); 677 678 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 679 DstVT == MVT::Other || !DstVT.isSimple()) 680 // Unhandled type. Halt "fast" selection and bail. 681 return false; 682 683 // Check if the destination type is legal. 684 if (!TLI.isTypeLegal(DstVT)) 685 return false; 686 687 // Check if the source operand is legal. 688 if (!TLI.isTypeLegal(SrcVT)) 689 return false; 690 691 unsigned InputReg = getRegForValue(I->getOperand(0)); 692 if (!InputReg) 693 // Unhandled operand. Halt "fast" selection and bail. 694 return false; 695 696 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 697 698 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 699 DstVT.getSimpleVT(), 700 Opcode, 701 InputReg, InputRegIsKill); 702 if (!ResultReg) 703 return false; 704 705 UpdateValueMap(I, ResultReg); 706 return true; 707} 708 709bool FastISel::SelectBitCast(const User *I) { 710 // If the bitcast doesn't change the type, just use the operand value. 711 if (I->getType() == I->getOperand(0)->getType()) { 712 unsigned Reg = getRegForValue(I->getOperand(0)); 713 if (Reg == 0) 714 return false; 715 UpdateValueMap(I, Reg); 716 return true; 717 } 718 719 // Bitcasts of other values become reg-reg copies or BITCAST operators. 720 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 721 EVT DstVT = TLI.getValueType(I->getType()); 722 723 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 724 DstVT == MVT::Other || !DstVT.isSimple() || 725 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 726 // Unhandled type. Halt "fast" selection and bail. 727 return false; 728 729 unsigned Op0 = getRegForValue(I->getOperand(0)); 730 if (Op0 == 0) 731 // Unhandled operand. Halt "fast" selection and bail. 732 return false; 733 734 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 735 736 // First, try to perform the bitcast by inserting a reg-reg copy. 737 unsigned ResultReg = 0; 738 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 739 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 740 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 741 // Don't attempt a cross-class copy. It will likely fail. 742 if (SrcClass == DstClass) { 743 ResultReg = createResultReg(DstClass); 744 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 745 ResultReg).addReg(Op0); 746 } 747 } 748 749 // If the reg-reg copy failed, select a BITCAST opcode. 750 if (!ResultReg) 751 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 752 ISD::BITCAST, Op0, Op0IsKill); 753 754 if (!ResultReg) 755 return false; 756 757 UpdateValueMap(I, ResultReg); 758 return true; 759} 760 761bool 762FastISel::SelectInstruction(const Instruction *I) { 763 // Just before the terminator instruction, insert instructions to 764 // feed PHI nodes in successor blocks. 765 if (isa<TerminatorInst>(I)) 766 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 767 return false; 768 769 DL = I->getDebugLoc(); 770 771 // First, try doing target-independent selection. 772 if (SelectOperator(I, I->getOpcode())) { 773 DL = DebugLoc(); 774 return true; 775 } 776 777 // Next, try calling the target to attempt to handle the instruction. 778 if (TargetSelectInstruction(I)) { 779 DL = DebugLoc(); 780 return true; 781 } 782 783 DL = DebugLoc(); 784 return false; 785} 786 787/// FastEmitBranch - Emit an unconditional branch to the given block, 788/// unless it is the immediate (fall-through) successor, and update 789/// the CFG. 790void 791FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 792 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) { 793 // The unconditional fall-through case, which needs no instructions. 794 } else { 795 // The unconditional branch case. 796 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 797 SmallVector<MachineOperand, 0>(), DL); 798 } 799 FuncInfo.MBB->addSuccessor(MSucc); 800} 801 802/// SelectFNeg - Emit an FNeg operation. 803/// 804bool 805FastISel::SelectFNeg(const User *I) { 806 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 807 if (OpReg == 0) return false; 808 809 bool OpRegIsKill = hasTrivialKill(I); 810 811 // If the target has ISD::FNEG, use it. 812 EVT VT = TLI.getValueType(I->getType()); 813 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 814 ISD::FNEG, OpReg, OpRegIsKill); 815 if (ResultReg != 0) { 816 UpdateValueMap(I, ResultReg); 817 return true; 818 } 819 820 // Bitcast the value to integer, twiddle the sign bit with xor, 821 // and then bitcast it back to floating-point. 822 if (VT.getSizeInBits() > 64) return false; 823 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 824 if (!TLI.isTypeLegal(IntVT)) 825 return false; 826 827 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 828 ISD::BITCAST, OpReg, OpRegIsKill); 829 if (IntReg == 0) 830 return false; 831 832 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 833 IntReg, /*Kill=*/true, 834 UINT64_C(1) << (VT.getSizeInBits()-1), 835 IntVT.getSimpleVT()); 836 if (IntResultReg == 0) 837 return false; 838 839 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 840 ISD::BITCAST, IntResultReg, /*Kill=*/true); 841 if (ResultReg == 0) 842 return false; 843 844 UpdateValueMap(I, ResultReg); 845 return true; 846} 847 848bool 849FastISel::SelectExtractValue(const User *U) { 850 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U); 851 if (!EVI) 852 return false; 853 854 // Make sure we only try to handle extracts with a legal result. But also 855 // allow i1 because it's easy. 856 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true); 857 if (!RealVT.isSimple()) 858 return false; 859 MVT VT = RealVT.getSimpleVT(); 860 if (!TLI.isTypeLegal(VT) && VT != MVT::i1) 861 return false; 862 863 const Value *Op0 = EVI->getOperand(0); 864 const Type *AggTy = Op0->getType(); 865 866 // Get the base result register. 867 unsigned ResultReg; 868 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0); 869 if (I != FuncInfo.ValueMap.end()) 870 ResultReg = I->second; 871 else if (isa<Instruction>(Op0)) 872 ResultReg = FuncInfo.InitializeRegForValue(Op0); 873 else 874 return false; // fast-isel can't handle aggregate constants at the moment 875 876 // Get the actual result register, which is an offset from the base register. 877 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->idx_begin(), EVI->idx_end()); 878 879 SmallVector<EVT, 4> AggValueVTs; 880 ComputeValueVTs(TLI, AggTy, AggValueVTs); 881 882 for (unsigned i = 0; i < VTIndex; i++) 883 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]); 884 885 UpdateValueMap(EVI, ResultReg); 886 return true; 887} 888 889bool 890FastISel::SelectOperator(const User *I, unsigned Opcode) { 891 switch (Opcode) { 892 case Instruction::Add: 893 return SelectBinaryOp(I, ISD::ADD); 894 case Instruction::FAdd: 895 return SelectBinaryOp(I, ISD::FADD); 896 case Instruction::Sub: 897 return SelectBinaryOp(I, ISD::SUB); 898 case Instruction::FSub: 899 // FNeg is currently represented in LLVM IR as a special case of FSub. 900 if (BinaryOperator::isFNeg(I)) 901 return SelectFNeg(I); 902 return SelectBinaryOp(I, ISD::FSUB); 903 case Instruction::Mul: 904 return SelectBinaryOp(I, ISD::MUL); 905 case Instruction::FMul: 906 return SelectBinaryOp(I, ISD::FMUL); 907 case Instruction::SDiv: 908 return SelectBinaryOp(I, ISD::SDIV); 909 case Instruction::UDiv: 910 return SelectBinaryOp(I, ISD::UDIV); 911 case Instruction::FDiv: 912 return SelectBinaryOp(I, ISD::FDIV); 913 case Instruction::SRem: 914 return SelectBinaryOp(I, ISD::SREM); 915 case Instruction::URem: 916 return SelectBinaryOp(I, ISD::UREM); 917 case Instruction::FRem: 918 return SelectBinaryOp(I, ISD::FREM); 919 case Instruction::Shl: 920 return SelectBinaryOp(I, ISD::SHL); 921 case Instruction::LShr: 922 return SelectBinaryOp(I, ISD::SRL); 923 case Instruction::AShr: 924 return SelectBinaryOp(I, ISD::SRA); 925 case Instruction::And: 926 return SelectBinaryOp(I, ISD::AND); 927 case Instruction::Or: 928 return SelectBinaryOp(I, ISD::OR); 929 case Instruction::Xor: 930 return SelectBinaryOp(I, ISD::XOR); 931 932 case Instruction::GetElementPtr: 933 return SelectGetElementPtr(I); 934 935 case Instruction::Br: { 936 const BranchInst *BI = cast<BranchInst>(I); 937 938 if (BI->isUnconditional()) { 939 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 940 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc]; 941 FastEmitBranch(MSucc, BI->getDebugLoc()); 942 return true; 943 } 944 945 // Conditional branches are not handed yet. 946 // Halt "fast" selection and bail. 947 return false; 948 } 949 950 case Instruction::Unreachable: 951 // Nothing to emit. 952 return true; 953 954 case Instruction::Alloca: 955 // FunctionLowering has the static-sized case covered. 956 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I))) 957 return true; 958 959 // Dynamic-sized alloca is not handled yet. 960 return false; 961 962 case Instruction::Call: 963 return SelectCall(I); 964 965 case Instruction::BitCast: 966 return SelectBitCast(I); 967 968 case Instruction::FPToSI: 969 return SelectCast(I, ISD::FP_TO_SINT); 970 case Instruction::ZExt: 971 return SelectCast(I, ISD::ZERO_EXTEND); 972 case Instruction::SExt: 973 return SelectCast(I, ISD::SIGN_EXTEND); 974 case Instruction::Trunc: 975 return SelectCast(I, ISD::TRUNCATE); 976 case Instruction::SIToFP: 977 return SelectCast(I, ISD::SINT_TO_FP); 978 979 case Instruction::IntToPtr: // Deliberate fall-through. 980 case Instruction::PtrToInt: { 981 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 982 EVT DstVT = TLI.getValueType(I->getType()); 983 if (DstVT.bitsGT(SrcVT)) 984 return SelectCast(I, ISD::ZERO_EXTEND); 985 if (DstVT.bitsLT(SrcVT)) 986 return SelectCast(I, ISD::TRUNCATE); 987 unsigned Reg = getRegForValue(I->getOperand(0)); 988 if (Reg == 0) return false; 989 UpdateValueMap(I, Reg); 990 return true; 991 } 992 993 case Instruction::ExtractValue: 994 return SelectExtractValue(I); 995 996 case Instruction::PHI: 997 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 998 999 default: 1000 // Unhandled instruction. Halt "fast" selection and bail. 1001 return false; 1002 } 1003} 1004 1005FastISel::FastISel(FunctionLoweringInfo &funcInfo) 1006 : FuncInfo(funcInfo), 1007 MRI(FuncInfo.MF->getRegInfo()), 1008 MFI(*FuncInfo.MF->getFrameInfo()), 1009 MCP(*FuncInfo.MF->getConstantPool()), 1010 TM(FuncInfo.MF->getTarget()), 1011 TD(*TM.getTargetData()), 1012 TII(*TM.getInstrInfo()), 1013 TLI(*TM.getTargetLowering()), 1014 TRI(*TM.getRegisterInfo()) { 1015} 1016 1017FastISel::~FastISel() {} 1018 1019unsigned FastISel::FastEmit_(MVT, MVT, 1020 unsigned) { 1021 return 0; 1022} 1023 1024unsigned FastISel::FastEmit_r(MVT, MVT, 1025 unsigned, 1026 unsigned /*Op0*/, bool /*Op0IsKill*/) { 1027 return 0; 1028} 1029 1030unsigned FastISel::FastEmit_rr(MVT, MVT, 1031 unsigned, 1032 unsigned /*Op0*/, bool /*Op0IsKill*/, 1033 unsigned /*Op1*/, bool /*Op1IsKill*/) { 1034 return 0; 1035} 1036 1037unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 1038 return 0; 1039} 1040 1041unsigned FastISel::FastEmit_f(MVT, MVT, 1042 unsigned, const ConstantFP * /*FPImm*/) { 1043 return 0; 1044} 1045 1046unsigned FastISel::FastEmit_ri(MVT, MVT, 1047 unsigned, 1048 unsigned /*Op0*/, bool /*Op0IsKill*/, 1049 uint64_t /*Imm*/) { 1050 return 0; 1051} 1052 1053unsigned FastISel::FastEmit_rf(MVT, MVT, 1054 unsigned, 1055 unsigned /*Op0*/, bool /*Op0IsKill*/, 1056 const ConstantFP * /*FPImm*/) { 1057 return 0; 1058} 1059 1060unsigned FastISel::FastEmit_rri(MVT, MVT, 1061 unsigned, 1062 unsigned /*Op0*/, bool /*Op0IsKill*/, 1063 unsigned /*Op1*/, bool /*Op1IsKill*/, 1064 uint64_t /*Imm*/) { 1065 return 0; 1066} 1067 1068/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 1069/// to emit an instruction with an immediate operand using FastEmit_ri. 1070/// If that fails, it materializes the immediate into a register and try 1071/// FastEmit_rr instead. 1072unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 1073 unsigned Op0, bool Op0IsKill, 1074 uint64_t Imm, MVT ImmType) { 1075 // If this is a multiply by a power of two, emit this as a shift left. 1076 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) { 1077 Opcode = ISD::SHL; 1078 Imm = Log2_64(Imm); 1079 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { 1080 // div x, 8 -> srl x, 3 1081 Opcode = ISD::SRL; 1082 Imm = Log2_64(Imm); 1083 } 1084 1085 // Horrible hack (to be removed), check to make sure shift amounts are 1086 // in-range. 1087 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && 1088 Imm >= VT.getSizeInBits()) 1089 return 0; 1090 1091 // First check if immediate type is legal. If not, we can't use the ri form. 1092 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 1093 if (ResultReg != 0) 1094 return ResultReg; 1095 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 1096 if (MaterialReg == 0) { 1097 // This is a bit ugly/slow, but failing here means falling out of 1098 // fast-isel, which would be very slow. 1099 const IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(), 1100 VT.getSizeInBits()); 1101 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm)); 1102 } 1103 return FastEmit_rr(VT, VT, Opcode, 1104 Op0, Op0IsKill, 1105 MaterialReg, /*Kill=*/true); 1106} 1107 1108unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 1109 return MRI.createVirtualRegister(RC); 1110} 1111 1112unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 1113 const TargetRegisterClass* RC) { 1114 unsigned ResultReg = createResultReg(RC); 1115 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1116 1117 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); 1118 return ResultReg; 1119} 1120 1121unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 1122 const TargetRegisterClass *RC, 1123 unsigned Op0, bool Op0IsKill) { 1124 unsigned ResultReg = createResultReg(RC); 1125 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1126 1127 if (II.getNumDefs() >= 1) 1128 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1129 .addReg(Op0, Op0IsKill * RegState::Kill); 1130 else { 1131 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1132 .addReg(Op0, Op0IsKill * RegState::Kill); 1133 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1134 ResultReg).addReg(II.ImplicitDefs[0]); 1135 } 1136 1137 return ResultReg; 1138} 1139 1140unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1141 const TargetRegisterClass *RC, 1142 unsigned Op0, bool Op0IsKill, 1143 unsigned Op1, bool Op1IsKill) { 1144 unsigned ResultReg = createResultReg(RC); 1145 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1146 1147 if (II.getNumDefs() >= 1) 1148 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1149 .addReg(Op0, Op0IsKill * RegState::Kill) 1150 .addReg(Op1, Op1IsKill * RegState::Kill); 1151 else { 1152 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1153 .addReg(Op0, Op0IsKill * RegState::Kill) 1154 .addReg(Op1, Op1IsKill * RegState::Kill); 1155 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1156 ResultReg).addReg(II.ImplicitDefs[0]); 1157 } 1158 return ResultReg; 1159} 1160 1161unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, 1162 const TargetRegisterClass *RC, 1163 unsigned Op0, bool Op0IsKill, 1164 unsigned Op1, bool Op1IsKill, 1165 unsigned Op2, bool Op2IsKill) { 1166 unsigned ResultReg = createResultReg(RC); 1167 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1168 1169 if (II.getNumDefs() >= 1) 1170 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1171 .addReg(Op0, Op0IsKill * RegState::Kill) 1172 .addReg(Op1, Op1IsKill * RegState::Kill) 1173 .addReg(Op2, Op2IsKill * RegState::Kill); 1174 else { 1175 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1176 .addReg(Op0, Op0IsKill * RegState::Kill) 1177 .addReg(Op1, Op1IsKill * RegState::Kill) 1178 .addReg(Op2, Op2IsKill * RegState::Kill); 1179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1180 ResultReg).addReg(II.ImplicitDefs[0]); 1181 } 1182 return ResultReg; 1183} 1184 1185unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1186 const TargetRegisterClass *RC, 1187 unsigned Op0, bool Op0IsKill, 1188 uint64_t Imm) { 1189 unsigned ResultReg = createResultReg(RC); 1190 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1191 1192 if (II.getNumDefs() >= 1) 1193 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1194 .addReg(Op0, Op0IsKill * RegState::Kill) 1195 .addImm(Imm); 1196 else { 1197 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1198 .addReg(Op0, Op0IsKill * RegState::Kill) 1199 .addImm(Imm); 1200 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1201 ResultReg).addReg(II.ImplicitDefs[0]); 1202 } 1203 return ResultReg; 1204} 1205 1206unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode, 1207 const TargetRegisterClass *RC, 1208 unsigned Op0, bool Op0IsKill, 1209 uint64_t Imm1, uint64_t Imm2) { 1210 unsigned ResultReg = createResultReg(RC); 1211 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1212 1213 if (II.getNumDefs() >= 1) 1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1215 .addReg(Op0, Op0IsKill * RegState::Kill) 1216 .addImm(Imm1) 1217 .addImm(Imm2); 1218 else { 1219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1220 .addReg(Op0, Op0IsKill * RegState::Kill) 1221 .addImm(Imm1) 1222 .addImm(Imm2); 1223 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1224 ResultReg).addReg(II.ImplicitDefs[0]); 1225 } 1226 return ResultReg; 1227} 1228 1229unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1230 const TargetRegisterClass *RC, 1231 unsigned Op0, bool Op0IsKill, 1232 const ConstantFP *FPImm) { 1233 unsigned ResultReg = createResultReg(RC); 1234 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1235 1236 if (II.getNumDefs() >= 1) 1237 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1238 .addReg(Op0, Op0IsKill * RegState::Kill) 1239 .addFPImm(FPImm); 1240 else { 1241 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1242 .addReg(Op0, Op0IsKill * RegState::Kill) 1243 .addFPImm(FPImm); 1244 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1245 ResultReg).addReg(II.ImplicitDefs[0]); 1246 } 1247 return ResultReg; 1248} 1249 1250unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1251 const TargetRegisterClass *RC, 1252 unsigned Op0, bool Op0IsKill, 1253 unsigned Op1, bool Op1IsKill, 1254 uint64_t Imm) { 1255 unsigned ResultReg = createResultReg(RC); 1256 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1257 1258 if (II.getNumDefs() >= 1) 1259 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1260 .addReg(Op0, Op0IsKill * RegState::Kill) 1261 .addReg(Op1, Op1IsKill * RegState::Kill) 1262 .addImm(Imm); 1263 else { 1264 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1265 .addReg(Op0, Op0IsKill * RegState::Kill) 1266 .addReg(Op1, Op1IsKill * RegState::Kill) 1267 .addImm(Imm); 1268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1269 ResultReg).addReg(II.ImplicitDefs[0]); 1270 } 1271 return ResultReg; 1272} 1273 1274unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1275 const TargetRegisterClass *RC, 1276 uint64_t Imm) { 1277 unsigned ResultReg = createResultReg(RC); 1278 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1279 1280 if (II.getNumDefs() >= 1) 1281 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); 1282 else { 1283 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm); 1284 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1285 ResultReg).addReg(II.ImplicitDefs[0]); 1286 } 1287 return ResultReg; 1288} 1289 1290unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode, 1291 const TargetRegisterClass *RC, 1292 uint64_t Imm1, uint64_t Imm2) { 1293 unsigned ResultReg = createResultReg(RC); 1294 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1295 1296 if (II.getNumDefs() >= 1) 1297 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1298 .addImm(Imm1).addImm(Imm2); 1299 else { 1300 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2); 1301 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1302 ResultReg).addReg(II.ImplicitDefs[0]); 1303 } 1304 return ResultReg; 1305} 1306 1307unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1308 unsigned Op0, bool Op0IsKill, 1309 uint32_t Idx) { 1310 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1311 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 1312 "Cannot yet extract from physregs"); 1313 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 1314 DL, TII.get(TargetOpcode::COPY), ResultReg) 1315 .addReg(Op0, getKillRegState(Op0IsKill), Idx); 1316 return ResultReg; 1317} 1318 1319/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1320/// with all but the least significant bit set to zero. 1321unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1322 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1323} 1324 1325/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1326/// Emit code to ensure constants are copied into registers when needed. 1327/// Remember the virtual registers that need to be added to the Machine PHI 1328/// nodes as input. We cannot just directly add them, because expansion 1329/// might result in multiple MBB's for one BB. As such, the start of the 1330/// BB might correspond to a different MBB than the end. 1331bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1332 const TerminatorInst *TI = LLVMBB->getTerminator(); 1333 1334 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1335 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); 1336 1337 // Check successor nodes' PHI nodes that expect a constant to be available 1338 // from this block. 1339 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1340 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1341 if (!isa<PHINode>(SuccBB->begin())) continue; 1342 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 1343 1344 // If this terminator has multiple identical successors (common for 1345 // switches), only handle each succ once. 1346 if (!SuccsHandled.insert(SuccMBB)) continue; 1347 1348 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1349 1350 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1351 // nodes and Machine PHI nodes, but the incoming operands have not been 1352 // emitted yet. 1353 for (BasicBlock::const_iterator I = SuccBB->begin(); 1354 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1355 1356 // Ignore dead phi's. 1357 if (PN->use_empty()) continue; 1358 1359 // Only handle legal types. Two interesting things to note here. First, 1360 // by bailing out early, we may leave behind some dead instructions, 1361 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1362 // own moves. Second, this check is necessary because FastISel doesn't 1363 // use CreateRegs to create registers, so it always creates 1364 // exactly one register for each non-void instruction. 1365 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1366 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1367 // Promote MVT::i1. 1368 if (VT == MVT::i1) 1369 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1370 else { 1371 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1372 return false; 1373 } 1374 } 1375 1376 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1377 1378 // Set the DebugLoc for the copy. Prefer the location of the operand 1379 // if there is one; use the location of the PHI otherwise. 1380 DL = PN->getDebugLoc(); 1381 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1382 DL = Inst->getDebugLoc(); 1383 1384 unsigned Reg = getRegForValue(PHIOp); 1385 if (Reg == 0) { 1386 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1387 return false; 1388 } 1389 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1390 DL = DebugLoc(); 1391 } 1392 } 1393 1394 return true; 1395} 1396