FastISel.cpp revision 0193cd4779ab0f4f0bf5cec1dc8e61039d8263ad 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetInstrInfo.h"
19using namespace llvm;
20
21BasicBlock::iterator
22FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
23                             DenseMap<const Value*, unsigned> &ValueMap) {
24  BasicBlock::iterator I = Begin;
25
26  for (; I != End; ++I) {
27    switch (I->getOpcode()) {
28    case Instruction::Add: {
29      unsigned Op0 = ValueMap[I->getOperand(0)];
30      unsigned Op1 = ValueMap[I->getOperand(1)];
31      MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
32      if (VT == MVT::Other || !VT.isSimple()) {
33        // Unhandled type. Halt "fast" selection and bail.
34        return I;
35      }
36      unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISD::ADD, Op0, Op1);
37      if (ResultReg == 0) {
38        // Target-specific code wasn't able to find a machine opcode for
39        // the given ISD opcode and type. Halt "fast" selection and bail.
40        return I;
41      }
42      ValueMap[I] = ResultReg;
43      break;
44    }
45    case Instruction::Br: {
46      BranchInst *BI = cast<BranchInst>(I);
47
48      // For now, check for and handle just the most trivial case: an
49      // unconditional fall-through branch.
50      if (BI->isUnconditional() &&
51          next(MachineFunction::iterator(MBB))->getBasicBlock() ==
52            BI->getSuccessor(0)) {
53        MBB->addSuccessor(next(MachineFunction::iterator(MBB)));
54        break;
55      }
56
57      // Something more complicated. Halt "fast" selection and bail.
58      return I;
59    }
60    default:
61      // Unhandled instruction. Halt "fast" selection and bail.
62      return I;
63    }
64  }
65
66  return I;
67}
68
69FastISel::~FastISel() {}
70
71unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
72  return 0;
73}
74
75unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
76                              unsigned /*Op0*/) {
77  return 0;
78}
79
80unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
81                               unsigned /*Op0*/, unsigned /*Op0*/) {
82  return 0;
83}
84
85unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
86                                    const TargetRegisterClass* RC) {
87  MachineRegisterInfo &MRI = MF->getRegInfo();
88  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
89  unsigned ResultReg = MRI.createVirtualRegister(RC);
90
91  MachineInstr *MI = BuildMI(*MF, II, ResultReg);
92
93  MBB->push_back(MI);
94  return ResultReg;
95}
96
97unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
98                                  const TargetRegisterClass *RC,
99                                  unsigned Op0) {
100  MachineRegisterInfo &MRI = MF->getRegInfo();
101  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
102  unsigned ResultReg = MRI.createVirtualRegister(RC);
103
104  MachineInstr *MI = BuildMI(*MF, II, ResultReg);
105  MI->addOperand(MachineOperand::CreateReg(Op0, false));
106
107  MBB->push_back(MI);
108  return ResultReg;
109}
110
111unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
112                                   const TargetRegisterClass *RC,
113                                   unsigned Op0, unsigned Op1) {
114  MachineRegisterInfo &MRI = MF->getRegInfo();
115  const TargetInstrDesc &II = TII->get(MachineInstOpcode);
116  unsigned ResultReg = MRI.createVirtualRegister(RC);
117
118  MachineInstr *MI = BuildMI(*MF, II, ResultReg);
119  MI->addOperand(MachineOperand::CreateReg(Op0, false));
120  MI->addOperand(MachineOperand::CreateReg(Op1, false));
121
122  MBB->push_back(MI);
123  return ResultReg;
124}
125