FastISel.cpp revision 0b44e49f000a4da6b9948bdaa923b48911d2f47a
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "FunctionLoweringInfo.h" 57using namespace llvm; 58 59unsigned FastISel::getRegForValue(Value *V) { 60 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 61 // Don't handle non-simple values in FastISel. 62 if (!RealVT.isSimple()) 63 return 0; 64 65 // Ignore illegal types. We must do this before looking up the value 66 // in ValueMap because Arguments are given virtual registers regardless 67 // of whether FastISel can handle them. 68 MVT VT = RealVT.getSimpleVT(); 69 if (!TLI.isTypeLegal(VT)) { 70 // Promote MVT::i1 to a legal type though, because it's common and easy. 71 if (VT == MVT::i1) 72 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 73 else 74 return 0; 75 } 76 77 // Look up the value to see if we already have a register for it. We 78 // cache values defined by Instructions across blocks, and other values 79 // only locally. This is because Instructions already have the SSA 80 // def-dominates-use requirement enforced. 81 if (ValueMap.count(V)) 82 return ValueMap[V]; 83 unsigned Reg = LocalValueMap[V]; 84 if (Reg != 0) 85 return Reg; 86 87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 88 if (CI->getValue().getActiveBits() <= 64) 89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 90 } else if (isa<AllocaInst>(V)) { 91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 92 } else if (isa<ConstantPointerNull>(V)) { 93 // Translate this as an integer zero so that it can be 94 // local-CSE'd with actual integer zeros. 95 Reg = 96 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 99 100 if (!Reg) { 101 const APFloat &Flt = CF->getValueAPF(); 102 EVT IntVT = TLI.getPointerTy(); 103 104 uint64_t x[2]; 105 uint32_t IntBitWidth = IntVT.getSizeInBits(); 106 bool isExact; 107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 108 APFloat::rmTowardZero, &isExact); 109 if (isExact) { 110 APInt IntVal(IntBitWidth, 2, x); 111 112 unsigned IntegerReg = 113 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 114 if (IntegerReg != 0) 115 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 116 } 117 } 118 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 119 if (!SelectOperator(CE, CE->getOpcode())) return 0; 120 Reg = LocalValueMap[CE]; 121 } else if (isa<UndefValue>(V)) { 122 Reg = createResultReg(TLI.getRegClassFor(VT)); 123 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 124 } 125 126 // If target-independent code couldn't handle the value, give target-specific 127 // code a try. 128 if (!Reg && isa<Constant>(V)) 129 Reg = TargetMaterializeConstant(cast<Constant>(V)); 130 131 // Don't cache constant materializations in the general ValueMap. 132 // To do so would require tracking what uses they dominate. 133 if (Reg != 0) 134 LocalValueMap[V] = Reg; 135 return Reg; 136} 137 138unsigned FastISel::lookUpRegForValue(Value *V) { 139 // Look up the value to see if we already have a register for it. We 140 // cache values defined by Instructions across blocks, and other values 141 // only locally. This is because Instructions already have the SSA 142 // def-dominatess-use requirement enforced. 143 if (ValueMap.count(V)) 144 return ValueMap[V]; 145 return LocalValueMap[V]; 146} 147 148/// UpdateValueMap - Update the value map to include the new mapping for this 149/// instruction, or insert an extra copy to get the result in a previous 150/// determined register. 151/// NOTE: This is only necessary because we might select a block that uses 152/// a value before we select the block that defines the value. It might be 153/// possible to fix this by selecting blocks in reverse postorder. 154unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 155 if (!isa<Instruction>(I)) { 156 LocalValueMap[I] = Reg; 157 return Reg; 158 } 159 160 unsigned &AssignedReg = ValueMap[I]; 161 if (AssignedReg == 0) 162 AssignedReg = Reg; 163 else if (Reg != AssignedReg) { 164 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 165 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 166 Reg, RegClass, RegClass); 167 } 168 return AssignedReg; 169} 170 171unsigned FastISel::getRegForGEPIndex(Value *Idx) { 172 unsigned IdxN = getRegForValue(Idx); 173 if (IdxN == 0) 174 // Unhandled operand. Halt "fast" selection and bail. 175 return 0; 176 177 // If the index is smaller or larger than intptr_t, truncate or extend it. 178 MVT PtrVT = TLI.getPointerTy(); 179 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 180 if (IdxVT.bitsLT(PtrVT)) 181 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); 182 else if (IdxVT.bitsGT(PtrVT)) 183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); 184 return IdxN; 185} 186 187/// SelectBinaryOp - Select and emit code for a binary operator instruction, 188/// which has an opcode which directly corresponds to the given ISD opcode. 189/// 190bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) { 191 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 192 if (VT == MVT::Other || !VT.isSimple()) 193 // Unhandled type. Halt "fast" selection and bail. 194 return false; 195 196 // We only handle legal types. For example, on x86-32 the instruction 197 // selector contains all of the 64-bit instructions from x86-64, 198 // under the assumption that i64 won't be used if the target doesn't 199 // support it. 200 if (!TLI.isTypeLegal(VT)) { 201 // MVT::i1 is special. Allow AND, OR, or XOR because they 202 // don't require additional zeroing, which makes them easy. 203 if (VT == MVT::i1 && 204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 205 ISDOpcode == ISD::XOR)) 206 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 207 else 208 return false; 209 } 210 211 unsigned Op0 = getRegForValue(I->getOperand(0)); 212 if (Op0 == 0) 213 // Unhandled operand. Halt "fast" selection and bail. 214 return false; 215 216 // Check if the second operand is a constant and handle it appropriately. 217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 219 ISDOpcode, Op0, CI->getZExtValue()); 220 if (ResultReg != 0) { 221 // We successfully emitted code for the given LLVM Instruction. 222 UpdateValueMap(I, ResultReg); 223 return true; 224 } 225 } 226 227 // Check if the second operand is a constant float. 228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 230 ISDOpcode, Op0, CF); 231 if (ResultReg != 0) { 232 // We successfully emitted code for the given LLVM Instruction. 233 UpdateValueMap(I, ResultReg); 234 return true; 235 } 236 } 237 238 unsigned Op1 = getRegForValue(I->getOperand(1)); 239 if (Op1 == 0) 240 // Unhandled operand. Halt "fast" selection and bail. 241 return false; 242 243 // Now we have both operands in registers. Emit the instruction. 244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 245 ISDOpcode, Op0, Op1); 246 if (ResultReg == 0) 247 // Target-specific code wasn't able to find a machine opcode for 248 // the given ISD opcode and type. Halt "fast" selection and bail. 249 return false; 250 251 // We successfully emitted code for the given LLVM Instruction. 252 UpdateValueMap(I, ResultReg); 253 return true; 254} 255 256bool FastISel::SelectGetElementPtr(User *I) { 257 unsigned N = getRegForValue(I->getOperand(0)); 258 if (N == 0) 259 // Unhandled operand. Halt "fast" selection and bail. 260 return false; 261 262 const Type *Ty = I->getOperand(0)->getType(); 263 MVT VT = TLI.getPointerTy(); 264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 265 OI != E; ++OI) { 266 Value *Idx = *OI; 267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 269 if (Field) { 270 // N = N + Offset 271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 272 // FIXME: This can be optimized by combining the add with a 273 // subsequent one. 274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 275 if (N == 0) 276 // Unhandled operand. Halt "fast" selection and bail. 277 return false; 278 } 279 Ty = StTy->getElementType(Field); 280 } else { 281 Ty = cast<SequentialType>(Ty)->getElementType(); 282 283 // If this is a constant subscript, handle it quickly. 284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 285 if (CI->getZExtValue() == 0) continue; 286 uint64_t Offs = 287 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 289 if (N == 0) 290 // Unhandled operand. Halt "fast" selection and bail. 291 return false; 292 continue; 293 } 294 295 // N = N + Idx * ElementSize; 296 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 297 unsigned IdxN = getRegForGEPIndex(Idx); 298 if (IdxN == 0) 299 // Unhandled operand. Halt "fast" selection and bail. 300 return false; 301 302 if (ElementSize != 1) { 303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 304 if (IdxN == 0) 305 // Unhandled operand. Halt "fast" selection and bail. 306 return false; 307 } 308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 309 if (N == 0) 310 // Unhandled operand. Halt "fast" selection and bail. 311 return false; 312 } 313 } 314 315 // We successfully emitted code for the given LLVM Instruction. 316 UpdateValueMap(I, N); 317 return true; 318} 319 320bool FastISel::SelectCall(User *I) { 321 Function *F = cast<CallInst>(I)->getCalledFunction(); 322 if (!F) return false; 323 324 unsigned IID = F->getIntrinsicID(); 325 switch (IID) { 326 default: break; 327 case Intrinsic::dbg_declare: { 328 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 329 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW 330 || !DW->ShouldEmitDwarfDebug()) 331 return true; 332 333 Value *Address = DI->getAddress(); 334 if (!Address) 335 return true; 336 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 337 // Don't handle byval struct arguments or VLAs, for example. 338 if (!AI) break; 339 DenseMap<const AllocaInst*, int>::iterator SI = 340 StaticAllocaMap.find(AI); 341 if (SI == StaticAllocaMap.end()) break; // VLAs. 342 int FI = SI->second; 343 if (MDNode *Dbg = DI->getDbgMetadata()) 344 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg); 345 346 // Building the map above is target independent. Generating DBG_VALUE 347 // inline is target dependent; do this now. 348 (void)TargetSelectInstruction(cast<Instruction>(I)); 349 return true; 350 } 351 case Intrinsic::dbg_value: { 352 // This requires target support, but right now X86 is the only Fast target. 353 DbgValueInst *DI = cast<DbgValueInst>(I); 354 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 355 Value *V = DI->getValue(); 356 if (!V) { 357 // Currently the optimizer can produce this; insert an undef to 358 // help debugging. Probably the optimizer should not do this. 359 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 360 addMetadata(DI->getVariable()); 361 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 362 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()). 363 addMetadata(DI->getVariable()); 364 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 365 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()). 366 addMetadata(DI->getVariable()); 367 } else if (unsigned Reg = lookUpRegForValue(V)) { 368 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()). 369 addMetadata(DI->getVariable()); 370 } else { 371 // We can't yet handle anything else here because it would require 372 // generating code, thus altering codegen because of debug info. 373 // Insert an undef so we can see what we dropped. 374 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 375 addMetadata(DI->getVariable()); 376 } 377 return true; 378 } 379 case Intrinsic::eh_exception: { 380 EVT VT = TLI.getValueType(I->getType()); 381 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 382 default: break; 383 case TargetLowering::Expand: { 384 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 385 unsigned Reg = TLI.getExceptionAddressRegister(); 386 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 387 unsigned ResultReg = createResultReg(RC); 388 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 389 Reg, RC, RC); 390 assert(InsertedCopy && "Can't copy address registers!"); 391 InsertedCopy = InsertedCopy; 392 UpdateValueMap(I, ResultReg); 393 return true; 394 } 395 } 396 break; 397 } 398 case Intrinsic::eh_selector: { 399 EVT VT = TLI.getValueType(I->getType()); 400 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 401 default: break; 402 case TargetLowering::Expand: { 403 if (MMI) { 404 if (MBB->isLandingPad()) 405 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 406 else { 407#ifndef NDEBUG 408 CatchInfoLost.insert(cast<CallInst>(I)); 409#endif 410 // FIXME: Mark exception selector register as live in. Hack for PR1508. 411 unsigned Reg = TLI.getExceptionSelectorRegister(); 412 if (Reg) MBB->addLiveIn(Reg); 413 } 414 415 unsigned Reg = TLI.getExceptionSelectorRegister(); 416 EVT SrcVT = TLI.getPointerTy(); 417 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 418 unsigned ResultReg = createResultReg(RC); 419 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 420 RC, RC); 421 assert(InsertedCopy && "Can't copy address registers!"); 422 InsertedCopy = InsertedCopy; 423 424 // Cast the register to the type of the selector. 425 if (SrcVT.bitsGT(MVT::i32)) 426 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 427 ResultReg); 428 else if (SrcVT.bitsLT(MVT::i32)) 429 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 430 ISD::SIGN_EXTEND, ResultReg); 431 if (ResultReg == 0) 432 // Unhandled operand. Halt "fast" selection and bail. 433 return false; 434 435 UpdateValueMap(I, ResultReg); 436 } else { 437 unsigned ResultReg = 438 getRegForValue(Constant::getNullValue(I->getType())); 439 UpdateValueMap(I, ResultReg); 440 } 441 return true; 442 } 443 } 444 break; 445 } 446 } 447 return false; 448} 449 450bool FastISel::SelectCast(User *I, unsigned Opcode) { 451 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 452 EVT DstVT = TLI.getValueType(I->getType()); 453 454 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 455 DstVT == MVT::Other || !DstVT.isSimple()) 456 // Unhandled type. Halt "fast" selection and bail. 457 return false; 458 459 // Check if the destination type is legal. Or as a special case, 460 // it may be i1 if we're doing a truncate because that's 461 // easy and somewhat common. 462 if (!TLI.isTypeLegal(DstVT)) 463 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 464 // Unhandled type. Halt "fast" selection and bail. 465 return false; 466 467 // Check if the source operand is legal. Or as a special case, 468 // it may be i1 if we're doing zero-extension because that's 469 // easy and somewhat common. 470 if (!TLI.isTypeLegal(SrcVT)) 471 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 472 // Unhandled type. Halt "fast" selection and bail. 473 return false; 474 475 unsigned InputReg = getRegForValue(I->getOperand(0)); 476 if (!InputReg) 477 // Unhandled operand. Halt "fast" selection and bail. 478 return false; 479 480 // If the operand is i1, arrange for the high bits in the register to be zero. 481 if (SrcVT == MVT::i1) { 482 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 483 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 484 if (!InputReg) 485 return false; 486 } 487 // If the result is i1, truncate to the target's type for i1 first. 488 if (DstVT == MVT::i1) 489 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 490 491 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 492 DstVT.getSimpleVT(), 493 Opcode, 494 InputReg); 495 if (!ResultReg) 496 return false; 497 498 UpdateValueMap(I, ResultReg); 499 return true; 500} 501 502bool FastISel::SelectBitCast(User *I) { 503 // If the bitcast doesn't change the type, just use the operand value. 504 if (I->getType() == I->getOperand(0)->getType()) { 505 unsigned Reg = getRegForValue(I->getOperand(0)); 506 if (Reg == 0) 507 return false; 508 UpdateValueMap(I, Reg); 509 return true; 510 } 511 512 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 513 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 514 EVT DstVT = TLI.getValueType(I->getType()); 515 516 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 517 DstVT == MVT::Other || !DstVT.isSimple() || 518 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 519 // Unhandled type. Halt "fast" selection and bail. 520 return false; 521 522 unsigned Op0 = getRegForValue(I->getOperand(0)); 523 if (Op0 == 0) 524 // Unhandled operand. Halt "fast" selection and bail. 525 return false; 526 527 // First, try to perform the bitcast by inserting a reg-reg copy. 528 unsigned ResultReg = 0; 529 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 530 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 531 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 532 ResultReg = createResultReg(DstClass); 533 534 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 535 Op0, DstClass, SrcClass); 536 if (!InsertedCopy) 537 ResultReg = 0; 538 } 539 540 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 541 if (!ResultReg) 542 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 543 ISD::BIT_CONVERT, Op0); 544 545 if (!ResultReg) 546 return false; 547 548 UpdateValueMap(I, ResultReg); 549 return true; 550} 551 552bool 553FastISel::SelectInstruction(Instruction *I) { 554 // First, try doing target-independent selection. 555 if (SelectOperator(I, I->getOpcode())) 556 return true; 557 558 // Next, try calling the target to attempt to handle the instruction. 559 if (TargetSelectInstruction(I)) 560 return true; 561 562 return false; 563} 564 565/// FastEmitBranch - Emit an unconditional branch to the given block, 566/// unless it is the immediate (fall-through) successor, and update 567/// the CFG. 568void 569FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 570 if (MBB->isLayoutSuccessor(MSucc)) { 571 // The unconditional fall-through case, which needs no instructions. 572 } else { 573 // The unconditional branch case. 574 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 575 } 576 MBB->addSuccessor(MSucc); 577} 578 579/// SelectFNeg - Emit an FNeg operation. 580/// 581bool 582FastISel::SelectFNeg(User *I) { 583 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 584 if (OpReg == 0) return false; 585 586 // If the target has ISD::FNEG, use it. 587 EVT VT = TLI.getValueType(I->getType()); 588 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 589 ISD::FNEG, OpReg); 590 if (ResultReg != 0) { 591 UpdateValueMap(I, ResultReg); 592 return true; 593 } 594 595 // Bitcast the value to integer, twiddle the sign bit with xor, 596 // and then bitcast it back to floating-point. 597 if (VT.getSizeInBits() > 64) return false; 598 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 599 if (!TLI.isTypeLegal(IntVT)) 600 return false; 601 602 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 603 ISD::BIT_CONVERT, OpReg); 604 if (IntReg == 0) 605 return false; 606 607 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, 608 UINT64_C(1) << (VT.getSizeInBits()-1), 609 IntVT.getSimpleVT()); 610 if (IntResultReg == 0) 611 return false; 612 613 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 614 ISD::BIT_CONVERT, IntResultReg); 615 if (ResultReg == 0) 616 return false; 617 618 UpdateValueMap(I, ResultReg); 619 return true; 620} 621 622bool 623FastISel::SelectOperator(User *I, unsigned Opcode) { 624 switch (Opcode) { 625 case Instruction::Add: 626 return SelectBinaryOp(I, ISD::ADD); 627 case Instruction::FAdd: 628 return SelectBinaryOp(I, ISD::FADD); 629 case Instruction::Sub: 630 return SelectBinaryOp(I, ISD::SUB); 631 case Instruction::FSub: 632 // FNeg is currently represented in LLVM IR as a special case of FSub. 633 if (BinaryOperator::isFNeg(I)) 634 return SelectFNeg(I); 635 return SelectBinaryOp(I, ISD::FSUB); 636 case Instruction::Mul: 637 return SelectBinaryOp(I, ISD::MUL); 638 case Instruction::FMul: 639 return SelectBinaryOp(I, ISD::FMUL); 640 case Instruction::SDiv: 641 return SelectBinaryOp(I, ISD::SDIV); 642 case Instruction::UDiv: 643 return SelectBinaryOp(I, ISD::UDIV); 644 case Instruction::FDiv: 645 return SelectBinaryOp(I, ISD::FDIV); 646 case Instruction::SRem: 647 return SelectBinaryOp(I, ISD::SREM); 648 case Instruction::URem: 649 return SelectBinaryOp(I, ISD::UREM); 650 case Instruction::FRem: 651 return SelectBinaryOp(I, ISD::FREM); 652 case Instruction::Shl: 653 return SelectBinaryOp(I, ISD::SHL); 654 case Instruction::LShr: 655 return SelectBinaryOp(I, ISD::SRL); 656 case Instruction::AShr: 657 return SelectBinaryOp(I, ISD::SRA); 658 case Instruction::And: 659 return SelectBinaryOp(I, ISD::AND); 660 case Instruction::Or: 661 return SelectBinaryOp(I, ISD::OR); 662 case Instruction::Xor: 663 return SelectBinaryOp(I, ISD::XOR); 664 665 case Instruction::GetElementPtr: 666 return SelectGetElementPtr(I); 667 668 case Instruction::Br: { 669 BranchInst *BI = cast<BranchInst>(I); 670 671 if (BI->isUnconditional()) { 672 BasicBlock *LLVMSucc = BI->getSuccessor(0); 673 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 674 FastEmitBranch(MSucc); 675 return true; 676 } 677 678 // Conditional branches are not handed yet. 679 // Halt "fast" selection and bail. 680 return false; 681 } 682 683 case Instruction::Unreachable: 684 // Nothing to emit. 685 return true; 686 687 case Instruction::PHI: 688 // PHI nodes are already emitted. 689 return true; 690 691 case Instruction::Alloca: 692 // FunctionLowering has the static-sized case covered. 693 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 694 return true; 695 696 // Dynamic-sized alloca is not handled yet. 697 return false; 698 699 case Instruction::Call: 700 return SelectCall(I); 701 702 case Instruction::BitCast: 703 return SelectBitCast(I); 704 705 case Instruction::FPToSI: 706 return SelectCast(I, ISD::FP_TO_SINT); 707 case Instruction::ZExt: 708 return SelectCast(I, ISD::ZERO_EXTEND); 709 case Instruction::SExt: 710 return SelectCast(I, ISD::SIGN_EXTEND); 711 case Instruction::Trunc: 712 return SelectCast(I, ISD::TRUNCATE); 713 case Instruction::SIToFP: 714 return SelectCast(I, ISD::SINT_TO_FP); 715 716 case Instruction::IntToPtr: // Deliberate fall-through. 717 case Instruction::PtrToInt: { 718 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 719 EVT DstVT = TLI.getValueType(I->getType()); 720 if (DstVT.bitsGT(SrcVT)) 721 return SelectCast(I, ISD::ZERO_EXTEND); 722 if (DstVT.bitsLT(SrcVT)) 723 return SelectCast(I, ISD::TRUNCATE); 724 unsigned Reg = getRegForValue(I->getOperand(0)); 725 if (Reg == 0) return false; 726 UpdateValueMap(I, Reg); 727 return true; 728 } 729 730 default: 731 // Unhandled instruction. Halt "fast" selection and bail. 732 return false; 733 } 734} 735 736FastISel::FastISel(MachineFunction &mf, 737 MachineModuleInfo *mmi, 738 DwarfWriter *dw, 739 DenseMap<const Value *, unsigned> &vm, 740 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 741 DenseMap<const AllocaInst *, int> &am 742#ifndef NDEBUG 743 , SmallSet<Instruction*, 8> &cil 744#endif 745 ) 746 : MBB(0), 747 ValueMap(vm), 748 MBBMap(bm), 749 StaticAllocaMap(am), 750#ifndef NDEBUG 751 CatchInfoLost(cil), 752#endif 753 MF(mf), 754 MMI(mmi), 755 DW(dw), 756 MRI(MF.getRegInfo()), 757 MFI(*MF.getFrameInfo()), 758 MCP(*MF.getConstantPool()), 759 TM(MF.getTarget()), 760 TD(*TM.getTargetData()), 761 TII(*TM.getInstrInfo()), 762 TLI(*TM.getTargetLowering()) { 763} 764 765FastISel::~FastISel() {} 766 767unsigned FastISel::FastEmit_(MVT, MVT, 768 unsigned) { 769 return 0; 770} 771 772unsigned FastISel::FastEmit_r(MVT, MVT, 773 unsigned, unsigned /*Op0*/) { 774 return 0; 775} 776 777unsigned FastISel::FastEmit_rr(MVT, MVT, 778 unsigned, unsigned /*Op0*/, 779 unsigned /*Op0*/) { 780 return 0; 781} 782 783unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 784 return 0; 785} 786 787unsigned FastISel::FastEmit_f(MVT, MVT, 788 unsigned, ConstantFP * /*FPImm*/) { 789 return 0; 790} 791 792unsigned FastISel::FastEmit_ri(MVT, MVT, 793 unsigned, unsigned /*Op0*/, 794 uint64_t /*Imm*/) { 795 return 0; 796} 797 798unsigned FastISel::FastEmit_rf(MVT, MVT, 799 unsigned, unsigned /*Op0*/, 800 ConstantFP * /*FPImm*/) { 801 return 0; 802} 803 804unsigned FastISel::FastEmit_rri(MVT, MVT, 805 unsigned, 806 unsigned /*Op0*/, unsigned /*Op1*/, 807 uint64_t /*Imm*/) { 808 return 0; 809} 810 811/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 812/// to emit an instruction with an immediate operand using FastEmit_ri. 813/// If that fails, it materializes the immediate into a register and try 814/// FastEmit_rr instead. 815unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 816 unsigned Op0, uint64_t Imm, 817 MVT ImmType) { 818 // First check if immediate type is legal. If not, we can't use the ri form. 819 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 820 if (ResultReg != 0) 821 return ResultReg; 822 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 823 if (MaterialReg == 0) 824 return 0; 825 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 826} 827 828/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 829/// to emit an instruction with a floating-point immediate operand using 830/// FastEmit_rf. If that fails, it materializes the immediate into a register 831/// and try FastEmit_rr instead. 832unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 833 unsigned Op0, ConstantFP *FPImm, 834 MVT ImmType) { 835 // First check if immediate type is legal. If not, we can't use the rf form. 836 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 837 if (ResultReg != 0) 838 return ResultReg; 839 840 // Materialize the constant in a register. 841 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 842 if (MaterialReg == 0) { 843 // If the target doesn't have a way to directly enter a floating-point 844 // value into a register, use an alternate approach. 845 // TODO: The current approach only supports floating-point constants 846 // that can be constructed by conversion from integer values. This should 847 // be replaced by code that creates a load from a constant-pool entry, 848 // which will require some target-specific work. 849 const APFloat &Flt = FPImm->getValueAPF(); 850 EVT IntVT = TLI.getPointerTy(); 851 852 uint64_t x[2]; 853 uint32_t IntBitWidth = IntVT.getSizeInBits(); 854 bool isExact; 855 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 856 APFloat::rmTowardZero, &isExact); 857 if (!isExact) 858 return 0; 859 APInt IntVal(IntBitWidth, 2, x); 860 861 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 862 ISD::Constant, IntVal.getZExtValue()); 863 if (IntegerReg == 0) 864 return 0; 865 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 866 ISD::SINT_TO_FP, IntegerReg); 867 if (MaterialReg == 0) 868 return 0; 869 } 870 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 871} 872 873unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 874 return MRI.createVirtualRegister(RC); 875} 876 877unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 878 const TargetRegisterClass* RC) { 879 unsigned ResultReg = createResultReg(RC); 880 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 881 882 BuildMI(MBB, DL, II, ResultReg); 883 return ResultReg; 884} 885 886unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 887 const TargetRegisterClass *RC, 888 unsigned Op0) { 889 unsigned ResultReg = createResultReg(RC); 890 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 891 892 if (II.getNumDefs() >= 1) 893 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 894 else { 895 BuildMI(MBB, DL, II).addReg(Op0); 896 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 897 II.ImplicitDefs[0], RC, RC); 898 if (!InsertedCopy) 899 ResultReg = 0; 900 } 901 902 return ResultReg; 903} 904 905unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 906 const TargetRegisterClass *RC, 907 unsigned Op0, unsigned Op1) { 908 unsigned ResultReg = createResultReg(RC); 909 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 910 911 if (II.getNumDefs() >= 1) 912 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 913 else { 914 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 915 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 916 II.ImplicitDefs[0], RC, RC); 917 if (!InsertedCopy) 918 ResultReg = 0; 919 } 920 return ResultReg; 921} 922 923unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 924 const TargetRegisterClass *RC, 925 unsigned Op0, uint64_t Imm) { 926 unsigned ResultReg = createResultReg(RC); 927 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 928 929 if (II.getNumDefs() >= 1) 930 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 931 else { 932 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 933 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 934 II.ImplicitDefs[0], RC, RC); 935 if (!InsertedCopy) 936 ResultReg = 0; 937 } 938 return ResultReg; 939} 940 941unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 942 const TargetRegisterClass *RC, 943 unsigned Op0, ConstantFP *FPImm) { 944 unsigned ResultReg = createResultReg(RC); 945 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 946 947 if (II.getNumDefs() >= 1) 948 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 949 else { 950 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 951 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 952 II.ImplicitDefs[0], RC, RC); 953 if (!InsertedCopy) 954 ResultReg = 0; 955 } 956 return ResultReg; 957} 958 959unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 960 const TargetRegisterClass *RC, 961 unsigned Op0, unsigned Op1, uint64_t Imm) { 962 unsigned ResultReg = createResultReg(RC); 963 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 964 965 if (II.getNumDefs() >= 1) 966 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 967 else { 968 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 969 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 970 II.ImplicitDefs[0], RC, RC); 971 if (!InsertedCopy) 972 ResultReg = 0; 973 } 974 return ResultReg; 975} 976 977unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 978 const TargetRegisterClass *RC, 979 uint64_t Imm) { 980 unsigned ResultReg = createResultReg(RC); 981 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 982 983 if (II.getNumDefs() >= 1) 984 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 985 else { 986 BuildMI(MBB, DL, II).addImm(Imm); 987 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 988 II.ImplicitDefs[0], RC, RC); 989 if (!InsertedCopy) 990 ResultReg = 0; 991 } 992 return ResultReg; 993} 994 995unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 996 unsigned Op0, uint32_t Idx) { 997 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 998 999 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1000 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG); 1001 1002 if (II.getNumDefs() >= 1) 1003 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 1004 else { 1005 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1006 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1007 II.ImplicitDefs[0], RC, RC); 1008 if (!InsertedCopy) 1009 ResultReg = 0; 1010 } 1011 return ResultReg; 1012} 1013 1014/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1015/// with all but the least significant bit set to zero. 1016unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) { 1017 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1018} 1019