FastISel.cpp revision 0c41264d8ca7e8bd4bab0413891e7fb1aa22d864
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DebugLoc.h" 51#include "llvm/CodeGen/DwarfWriter.h" 52#include "llvm/Analysis/DebugInfo.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "SelectionDAGBuild.h" 58using namespace llvm; 59 60unsigned FastISel::getRegForValue(Value *V) { 61 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 62 // Don't handle non-simple values in FastISel. 63 if (!RealVT.isSimple()) 64 return 0; 65 66 // Ignore illegal types. We must do this before looking up the value 67 // in ValueMap because Arguments are given virtual registers regardless 68 // of whether FastISel can handle them. 69 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 70 if (!TLI.isTypeLegal(VT)) { 71 // Promote MVT::i1 to a legal type though, because it's common and easy. 72 if (VT == MVT::i1) 73 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 74 else 75 return 0; 76 } 77 78 // Look up the value to see if we already have a register for it. We 79 // cache values defined by Instructions across blocks, and other values 80 // only locally. This is because Instructions already have the SSA 81 // def-dominatess-use requirement enforced. 82 if (ValueMap.count(V)) 83 return ValueMap[V]; 84 unsigned Reg = LocalValueMap[V]; 85 if (Reg != 0) 86 return Reg; 87 88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 89 if (CI->getValue().getActiveBits() <= 64) 90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 91 } else if (isa<AllocaInst>(V)) { 92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 93 } else if (isa<ConstantPointerNull>(V)) { 94 // Translate this as an integer zero so that it can be 95 // local-CSE'd with actual integer zeros. 96 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 99 100 if (!Reg) { 101 const APFloat &Flt = CF->getValueAPF(); 102 MVT IntVT = TLI.getPointerTy(); 103 104 uint64_t x[2]; 105 uint32_t IntBitWidth = IntVT.getSizeInBits(); 106 bool isExact; 107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 108 APFloat::rmTowardZero, &isExact); 109 if (isExact) { 110 APInt IntVal(IntBitWidth, 2, x); 111 112 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 113 if (IntegerReg != 0) 114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 115 } 116 } 117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 118 if (!SelectOperator(CE, CE->getOpcode())) return 0; 119 Reg = LocalValueMap[CE]; 120 } else if (isa<UndefValue>(V)) { 121 Reg = createResultReg(TLI.getRegClassFor(VT)); 122 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 123 } 124 125 // If target-independent code couldn't handle the value, give target-specific 126 // code a try. 127 if (!Reg && isa<Constant>(V)) 128 Reg = TargetMaterializeConstant(cast<Constant>(V)); 129 130 // Don't cache constant materializations in the general ValueMap. 131 // To do so would require tracking what uses they dominate. 132 if (Reg != 0) 133 LocalValueMap[V] = Reg; 134 return Reg; 135} 136 137unsigned FastISel::lookUpRegForValue(Value *V) { 138 // Look up the value to see if we already have a register for it. We 139 // cache values defined by Instructions across blocks, and other values 140 // only locally. This is because Instructions already have the SSA 141 // def-dominatess-use requirement enforced. 142 if (ValueMap.count(V)) 143 return ValueMap[V]; 144 return LocalValueMap[V]; 145} 146 147/// UpdateValueMap - Update the value map to include the new mapping for this 148/// instruction, or insert an extra copy to get the result in a previous 149/// determined register. 150/// NOTE: This is only necessary because we might select a block that uses 151/// a value before we select the block that defines the value. It might be 152/// possible to fix this by selecting blocks in reverse postorder. 153unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 154 if (!isa<Instruction>(I)) { 155 LocalValueMap[I] = Reg; 156 return Reg; 157 } 158 159 unsigned &AssignedReg = ValueMap[I]; 160 if (AssignedReg == 0) 161 AssignedReg = Reg; 162 else if (Reg != AssignedReg) { 163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 165 Reg, RegClass, RegClass); 166 } 167 return AssignedReg; 168} 169 170unsigned FastISel::getRegForGEPIndex(Value *Idx) { 171 unsigned IdxN = getRegForValue(Idx); 172 if (IdxN == 0) 173 // Unhandled operand. Halt "fast" selection and bail. 174 return 0; 175 176 // If the index is smaller or larger than intptr_t, truncate or extend it. 177 MVT PtrVT = TLI.getPointerTy(); 178 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 179 if (IdxVT.bitsLT(PtrVT)) 180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 181 ISD::SIGN_EXTEND, IdxN); 182 else if (IdxVT.bitsGT(PtrVT)) 183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 184 ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 192 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 unsigned IID = F->getIntrinsicID(); 326 switch (IID) { 327 default: break; 328 case Intrinsic::dbg_stoppoint: { 329 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 330 if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) { 331 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 332 unsigned Line = SPI->getLine(); 333 unsigned Col = SPI->getColumn(); 334 unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), 335 DbgScopeTrack.getCurScope(), 336 Line, Col); 337 setCurDebugLoc(DebugLoc::get(Idx)); 338 } 339 return true; 340 } 341 case Intrinsic::dbg_region_start: { 342 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 343 if (!DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None)) 344 return true; 345 346 GlobalVariable *Rgn = cast<GlobalVariable>(RSI->getContext()); 347 DbgScopeTrack.EnterDebugScope(Rgn, MF); 348 if (DW && DW->ShouldEmitDwarfDebug()) { 349 unsigned ID = DW->RecordRegionStart(Rgn); 350 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 351 BuildMI(MBB, DL, II).addImm(ID); 352 } 353 return true; 354 } 355 case Intrinsic::dbg_region_end: { 356 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 357 if (!DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None)) 358 return true; 359 360 GlobalVariable *Rgn = cast<GlobalVariable>(REI->getContext()); 361 DbgScopeTrack.ExitDebugScope(Rgn, MF); 362 if (DW && DW->ShouldEmitDwarfDebug()) { 363 unsigned ID = 0; 364 DISubprogram Subprogram(Rgn); 365 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { 366 // This is end of an inlined function. 367 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 368 ID = DW->RecordInlinedFnEnd(Subprogram); 369 if (ID) 370 // Returned ID is 0 if this is unbalanced "end of inlined 371 // scope". This could happen if optimizer eats dbg intrinsics 372 // or "beginning of inlined scope" is not recoginized due to 373 // missing location info. In such cases, do ignore this region.end. 374 BuildMI(MBB, DL, II).addImm(ID); 375 } else { 376 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 377 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 378 BuildMI(MBB, DL, II).addImm(ID); 379 } 380 } 381 return true; 382 } 383 case Intrinsic::dbg_func_start: { 384 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 385 Value *SP = FSI->getSubprogram(); 386 if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None)) 387 return true; 388 389 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 390 // (most?) gdb expects. 391 DebugLoc PrevLoc = DL; 392 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 393 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 394 DbgScopeTrack.EnterDebugScope(Subprogram.getGV(), MF); 395 396 if (!Subprogram.describes(MF.getFunction())) { 397 // This is a beginning of an inlined function. 398 399 // If llvm.dbg.func.start is seen in a new block before any 400 // llvm.dbg.stoppoint intrinsic then the location info is unknown. 401 // FIXME : Why DebugLoc is reset at the beginning of each block ? 402 if (PrevLoc.isUnknown()) 403 return true; 404 // Record the source line. 405 unsigned Line = Subprogram.getLineNumber(); 406 setCurDebugLoc( 407 DebugLoc::get(MF.getOrCreateDebugLocID(CompileUnit.getGV(), 408 DbgScopeTrack.getCurScope(), 409 Line, 0))); 410 411 if (DW && DW->ShouldEmitDwarfDebug()) { 412 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc); 413 unsigned LabelID = DW->RecordInlinedFnStart(Subprogram, 414 DICompileUnit(PrevLocTpl.CompileUnit), 415 PrevLocTpl.Line, 416 PrevLocTpl.Col); 417 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 418 BuildMI(MBB, DL, II).addImm(LabelID); 419 } 420 } else { 421 // Record the source line. 422 unsigned Line = Subprogram.getLineNumber(); 423 MF.setDefaultDebugLoc( 424 DebugLoc::get(MF.getOrCreateDebugLocID(CompileUnit.getGV(), 425 DbgScopeTrack.getCurScope(), 426 Line, 0))); 427 if (DW && DW->ShouldEmitDwarfDebug()) { 428 // llvm.dbg.func_start also defines beginning of function scope. 429 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 430 } 431 } 432 433 return true; 434 } 435 case Intrinsic::dbg_declare: { 436 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 437 Value *Variable = DI->getVariable(); 438 if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) && 439 DW && DW->ShouldEmitDwarfDebug()) { 440 // Determine the address of the declared object. 441 Value *Address = DI->getAddress(); 442 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 443 Address = BCI->getOperand(0); 444 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 445 // Don't handle byval struct arguments or VLAs, for example. 446 if (!AI) break; 447 DenseMap<const AllocaInst*, int>::iterator SI = 448 StaticAllocaMap.find(AI); 449 if (SI == StaticAllocaMap.end()) break; // VLAs. 450 int FI = SI->second; 451 452 // Determine the debug globalvariable. 453 GlobalValue *GV = cast<GlobalVariable>(Variable); 454 455 // Build the DECLARE instruction. 456 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 457 MachineInstr *DeclareMI 458 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 459 DIVariable DV(cast<GlobalVariable>(GV)); 460 if (!DV.isNull()) { 461 // This is a local variable 462 DW->RecordVariableScope(DV, DeclareMI); 463 } 464 } 465 return true; 466 } 467 case Intrinsic::eh_exception: { 468 MVT VT = TLI.getValueType(I->getType()); 469 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 470 default: break; 471 case TargetLowering::Expand: { 472 if (!MBB->isLandingPad()) { 473 // FIXME: Mark exception register as live in. Hack for PR1508. 474 unsigned Reg = TLI.getExceptionAddressRegister(); 475 if (Reg) MBB->addLiveIn(Reg); 476 } 477 unsigned Reg = TLI.getExceptionAddressRegister(); 478 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 479 unsigned ResultReg = createResultReg(RC); 480 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 481 Reg, RC, RC); 482 assert(InsertedCopy && "Can't copy address registers!"); 483 InsertedCopy = InsertedCopy; 484 UpdateValueMap(I, ResultReg); 485 return true; 486 } 487 } 488 break; 489 } 490 case Intrinsic::eh_selector_i32: 491 case Intrinsic::eh_selector_i64: { 492 MVT VT = TLI.getValueType(I->getType()); 493 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 494 default: break; 495 case TargetLowering::Expand: { 496 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 497 MVT::i32 : MVT::i64); 498 499 if (MMI) { 500 if (MBB->isLandingPad()) 501 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 502 else { 503#ifndef NDEBUG 504 CatchInfoLost.insert(cast<CallInst>(I)); 505#endif 506 // FIXME: Mark exception selector register as live in. Hack for PR1508. 507 unsigned Reg = TLI.getExceptionSelectorRegister(); 508 if (Reg) MBB->addLiveIn(Reg); 509 } 510 511 unsigned Reg = TLI.getExceptionSelectorRegister(); 512 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 513 unsigned ResultReg = createResultReg(RC); 514 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 515 Reg, RC, RC); 516 assert(InsertedCopy && "Can't copy address registers!"); 517 InsertedCopy = InsertedCopy; 518 UpdateValueMap(I, ResultReg); 519 } else { 520 unsigned ResultReg = 521 getRegForValue(Constant::getNullValue(I->getType())); 522 UpdateValueMap(I, ResultReg); 523 } 524 return true; 525 } 526 } 527 break; 528 } 529 } 530 return false; 531} 532 533bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 534 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 535 MVT DstVT = TLI.getValueType(I->getType()); 536 537 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 538 DstVT == MVT::Other || !DstVT.isSimple()) 539 // Unhandled type. Halt "fast" selection and bail. 540 return false; 541 542 // Check if the destination type is legal. Or as a special case, 543 // it may be i1 if we're doing a truncate because that's 544 // easy and somewhat common. 545 if (!TLI.isTypeLegal(DstVT)) 546 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 547 // Unhandled type. Halt "fast" selection and bail. 548 return false; 549 550 // Check if the source operand is legal. Or as a special case, 551 // it may be i1 if we're doing zero-extension because that's 552 // easy and somewhat common. 553 if (!TLI.isTypeLegal(SrcVT)) 554 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 555 // Unhandled type. Halt "fast" selection and bail. 556 return false; 557 558 unsigned InputReg = getRegForValue(I->getOperand(0)); 559 if (!InputReg) 560 // Unhandled operand. Halt "fast" selection and bail. 561 return false; 562 563 // If the operand is i1, arrange for the high bits in the register to be zero. 564 if (SrcVT == MVT::i1) { 565 SrcVT = TLI.getTypeToTransformTo(SrcVT); 566 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 567 if (!InputReg) 568 return false; 569 } 570 // If the result is i1, truncate to the target's type for i1 first. 571 if (DstVT == MVT::i1) 572 DstVT = TLI.getTypeToTransformTo(DstVT); 573 574 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 575 DstVT.getSimpleVT(), 576 Opcode, 577 InputReg); 578 if (!ResultReg) 579 return false; 580 581 UpdateValueMap(I, ResultReg); 582 return true; 583} 584 585bool FastISel::SelectBitCast(User *I) { 586 // If the bitcast doesn't change the type, just use the operand value. 587 if (I->getType() == I->getOperand(0)->getType()) { 588 unsigned Reg = getRegForValue(I->getOperand(0)); 589 if (Reg == 0) 590 return false; 591 UpdateValueMap(I, Reg); 592 return true; 593 } 594 595 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 596 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 597 MVT DstVT = TLI.getValueType(I->getType()); 598 599 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 600 DstVT == MVT::Other || !DstVT.isSimple() || 601 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 602 // Unhandled type. Halt "fast" selection and bail. 603 return false; 604 605 unsigned Op0 = getRegForValue(I->getOperand(0)); 606 if (Op0 == 0) 607 // Unhandled operand. Halt "fast" selection and bail. 608 return false; 609 610 // First, try to perform the bitcast by inserting a reg-reg copy. 611 unsigned ResultReg = 0; 612 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 613 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 614 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 615 ResultReg = createResultReg(DstClass); 616 617 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 618 Op0, DstClass, SrcClass); 619 if (!InsertedCopy) 620 ResultReg = 0; 621 } 622 623 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 624 if (!ResultReg) 625 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 626 ISD::BIT_CONVERT, Op0); 627 628 if (!ResultReg) 629 return false; 630 631 UpdateValueMap(I, ResultReg); 632 return true; 633} 634 635bool 636FastISel::SelectInstruction(Instruction *I) { 637 return SelectOperator(I, I->getOpcode()); 638} 639 640/// FastEmitBranch - Emit an unconditional branch to the given block, 641/// unless it is the immediate (fall-through) successor, and update 642/// the CFG. 643void 644FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 645 MachineFunction::iterator NextMBB = 646 next(MachineFunction::iterator(MBB)); 647 648 if (MBB->isLayoutSuccessor(MSucc)) { 649 // The unconditional fall-through case, which needs no instructions. 650 } else { 651 // The unconditional branch case. 652 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 653 } 654 MBB->addSuccessor(MSucc); 655} 656 657bool 658FastISel::SelectOperator(User *I, unsigned Opcode) { 659 switch (Opcode) { 660 case Instruction::Add: { 661 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 662 return SelectBinaryOp(I, Opc); 663 } 664 case Instruction::Sub: { 665 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 666 return SelectBinaryOp(I, Opc); 667 } 668 case Instruction::Mul: { 669 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 670 return SelectBinaryOp(I, Opc); 671 } 672 case Instruction::SDiv: 673 return SelectBinaryOp(I, ISD::SDIV); 674 case Instruction::UDiv: 675 return SelectBinaryOp(I, ISD::UDIV); 676 case Instruction::FDiv: 677 return SelectBinaryOp(I, ISD::FDIV); 678 case Instruction::SRem: 679 return SelectBinaryOp(I, ISD::SREM); 680 case Instruction::URem: 681 return SelectBinaryOp(I, ISD::UREM); 682 case Instruction::FRem: 683 return SelectBinaryOp(I, ISD::FREM); 684 case Instruction::Shl: 685 return SelectBinaryOp(I, ISD::SHL); 686 case Instruction::LShr: 687 return SelectBinaryOp(I, ISD::SRL); 688 case Instruction::AShr: 689 return SelectBinaryOp(I, ISD::SRA); 690 case Instruction::And: 691 return SelectBinaryOp(I, ISD::AND); 692 case Instruction::Or: 693 return SelectBinaryOp(I, ISD::OR); 694 case Instruction::Xor: 695 return SelectBinaryOp(I, ISD::XOR); 696 697 case Instruction::GetElementPtr: 698 return SelectGetElementPtr(I); 699 700 case Instruction::Br: { 701 BranchInst *BI = cast<BranchInst>(I); 702 703 if (BI->isUnconditional()) { 704 BasicBlock *LLVMSucc = BI->getSuccessor(0); 705 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 706 FastEmitBranch(MSucc); 707 return true; 708 } 709 710 // Conditional branches are not handed yet. 711 // Halt "fast" selection and bail. 712 return false; 713 } 714 715 case Instruction::Unreachable: 716 // Nothing to emit. 717 return true; 718 719 case Instruction::PHI: 720 // PHI nodes are already emitted. 721 return true; 722 723 case Instruction::Alloca: 724 // FunctionLowering has the static-sized case covered. 725 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 726 return true; 727 728 // Dynamic-sized alloca is not handled yet. 729 return false; 730 731 case Instruction::Call: 732 return SelectCall(I); 733 734 case Instruction::BitCast: 735 return SelectBitCast(I); 736 737 case Instruction::FPToSI: 738 return SelectCast(I, ISD::FP_TO_SINT); 739 case Instruction::ZExt: 740 return SelectCast(I, ISD::ZERO_EXTEND); 741 case Instruction::SExt: 742 return SelectCast(I, ISD::SIGN_EXTEND); 743 case Instruction::Trunc: 744 return SelectCast(I, ISD::TRUNCATE); 745 case Instruction::SIToFP: 746 return SelectCast(I, ISD::SINT_TO_FP); 747 748 case Instruction::IntToPtr: // Deliberate fall-through. 749 case Instruction::PtrToInt: { 750 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 751 MVT DstVT = TLI.getValueType(I->getType()); 752 if (DstVT.bitsGT(SrcVT)) 753 return SelectCast(I, ISD::ZERO_EXTEND); 754 if (DstVT.bitsLT(SrcVT)) 755 return SelectCast(I, ISD::TRUNCATE); 756 unsigned Reg = getRegForValue(I->getOperand(0)); 757 if (Reg == 0) return false; 758 UpdateValueMap(I, Reg); 759 return true; 760 } 761 762 default: 763 // Unhandled instruction. Halt "fast" selection and bail. 764 return false; 765 } 766} 767 768FastISel::FastISel(MachineFunction &mf, 769 MachineModuleInfo *mmi, 770 DwarfWriter *dw, 771 DenseMap<const Value *, unsigned> &vm, 772 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 773 DenseMap<const AllocaInst *, int> &am 774#ifndef NDEBUG 775 , SmallSet<Instruction*, 8> &cil 776#endif 777 ) 778 : MBB(0), 779 ValueMap(vm), 780 MBBMap(bm), 781 StaticAllocaMap(am), 782#ifndef NDEBUG 783 CatchInfoLost(cil), 784#endif 785 MF(mf), 786 MMI(mmi), 787 DW(dw), 788 MRI(MF.getRegInfo()), 789 MFI(*MF.getFrameInfo()), 790 MCP(*MF.getConstantPool()), 791 TM(MF.getTarget()), 792 TD(*TM.getTargetData()), 793 TII(*TM.getInstrInfo()), 794 TLI(*TM.getTargetLowering()) { 795} 796 797FastISel::~FastISel() {} 798 799unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 800 ISD::NodeType) { 801 return 0; 802} 803 804unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 805 ISD::NodeType, unsigned /*Op0*/) { 806 return 0; 807} 808 809unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 810 ISD::NodeType, unsigned /*Op0*/, 811 unsigned /*Op0*/) { 812 return 0; 813} 814 815unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 816 ISD::NodeType, uint64_t /*Imm*/) { 817 return 0; 818} 819 820unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 821 ISD::NodeType, ConstantFP * /*FPImm*/) { 822 return 0; 823} 824 825unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 826 ISD::NodeType, unsigned /*Op0*/, 827 uint64_t /*Imm*/) { 828 return 0; 829} 830 831unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 832 ISD::NodeType, unsigned /*Op0*/, 833 ConstantFP * /*FPImm*/) { 834 return 0; 835} 836 837unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 838 ISD::NodeType, 839 unsigned /*Op0*/, unsigned /*Op1*/, 840 uint64_t /*Imm*/) { 841 return 0; 842} 843 844/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 845/// to emit an instruction with an immediate operand using FastEmit_ri. 846/// If that fails, it materializes the immediate into a register and try 847/// FastEmit_rr instead. 848unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 849 unsigned Op0, uint64_t Imm, 850 MVT::SimpleValueType ImmType) { 851 // First check if immediate type is legal. If not, we can't use the ri form. 852 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 853 if (ResultReg != 0) 854 return ResultReg; 855 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 856 if (MaterialReg == 0) 857 return 0; 858 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 859} 860 861/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 862/// to emit an instruction with a floating-point immediate operand using 863/// FastEmit_rf. If that fails, it materializes the immediate into a register 864/// and try FastEmit_rr instead. 865unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 866 unsigned Op0, ConstantFP *FPImm, 867 MVT::SimpleValueType ImmType) { 868 // First check if immediate type is legal. If not, we can't use the rf form. 869 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 870 if (ResultReg != 0) 871 return ResultReg; 872 873 // Materialize the constant in a register. 874 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 875 if (MaterialReg == 0) { 876 // If the target doesn't have a way to directly enter a floating-point 877 // value into a register, use an alternate approach. 878 // TODO: The current approach only supports floating-point constants 879 // that can be constructed by conversion from integer values. This should 880 // be replaced by code that creates a load from a constant-pool entry, 881 // which will require some target-specific work. 882 const APFloat &Flt = FPImm->getValueAPF(); 883 MVT IntVT = TLI.getPointerTy(); 884 885 uint64_t x[2]; 886 uint32_t IntBitWidth = IntVT.getSizeInBits(); 887 bool isExact; 888 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 889 APFloat::rmTowardZero, &isExact); 890 if (!isExact) 891 return 0; 892 APInt IntVal(IntBitWidth, 2, x); 893 894 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 895 ISD::Constant, IntVal.getZExtValue()); 896 if (IntegerReg == 0) 897 return 0; 898 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 899 ISD::SINT_TO_FP, IntegerReg); 900 if (MaterialReg == 0) 901 return 0; 902 } 903 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 904} 905 906unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 907 return MRI.createVirtualRegister(RC); 908} 909 910unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 911 const TargetRegisterClass* RC) { 912 unsigned ResultReg = createResultReg(RC); 913 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 914 915 BuildMI(MBB, DL, II, ResultReg); 916 return ResultReg; 917} 918 919unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 920 const TargetRegisterClass *RC, 921 unsigned Op0) { 922 unsigned ResultReg = createResultReg(RC); 923 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 924 925 if (II.getNumDefs() >= 1) 926 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 927 else { 928 BuildMI(MBB, DL, II).addReg(Op0); 929 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 930 II.ImplicitDefs[0], RC, RC); 931 if (!InsertedCopy) 932 ResultReg = 0; 933 } 934 935 return ResultReg; 936} 937 938unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 939 const TargetRegisterClass *RC, 940 unsigned Op0, unsigned Op1) { 941 unsigned ResultReg = createResultReg(RC); 942 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 943 944 if (II.getNumDefs() >= 1) 945 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 946 else { 947 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 948 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 949 II.ImplicitDefs[0], RC, RC); 950 if (!InsertedCopy) 951 ResultReg = 0; 952 } 953 return ResultReg; 954} 955 956unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 957 const TargetRegisterClass *RC, 958 unsigned Op0, uint64_t Imm) { 959 unsigned ResultReg = createResultReg(RC); 960 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 961 962 if (II.getNumDefs() >= 1) 963 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 964 else { 965 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 966 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 967 II.ImplicitDefs[0], RC, RC); 968 if (!InsertedCopy) 969 ResultReg = 0; 970 } 971 return ResultReg; 972} 973 974unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 975 const TargetRegisterClass *RC, 976 unsigned Op0, ConstantFP *FPImm) { 977 unsigned ResultReg = createResultReg(RC); 978 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 979 980 if (II.getNumDefs() >= 1) 981 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 982 else { 983 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 984 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 985 II.ImplicitDefs[0], RC, RC); 986 if (!InsertedCopy) 987 ResultReg = 0; 988 } 989 return ResultReg; 990} 991 992unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 993 const TargetRegisterClass *RC, 994 unsigned Op0, unsigned Op1, uint64_t Imm) { 995 unsigned ResultReg = createResultReg(RC); 996 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 997 998 if (II.getNumDefs() >= 1) 999 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 1000 else { 1001 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 1002 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1003 II.ImplicitDefs[0], RC, RC); 1004 if (!InsertedCopy) 1005 ResultReg = 0; 1006 } 1007 return ResultReg; 1008} 1009 1010unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1011 const TargetRegisterClass *RC, 1012 uint64_t Imm) { 1013 unsigned ResultReg = createResultReg(RC); 1014 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1015 1016 if (II.getNumDefs() >= 1) 1017 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 1018 else { 1019 BuildMI(MBB, DL, II).addImm(Imm); 1020 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1021 II.ImplicitDefs[0], RC, RC); 1022 if (!InsertedCopy) 1023 ResultReg = 0; 1024 } 1025 return ResultReg; 1026} 1027 1028unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 1029 unsigned Op0, uint32_t Idx) { 1030 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 1031 1032 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1033 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 1034 1035 if (II.getNumDefs() >= 1) 1036 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 1037 else { 1038 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1039 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1040 II.ImplicitDefs[0], RC, RC); 1041 if (!InsertedCopy) 1042 ResultReg = 0; 1043 } 1044 return ResultReg; 1045} 1046 1047/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1048/// with all but the least significant bit set to zero. 1049unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 1050 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1051} 1052