FastISel.cpp revision 12e528beb5b91114ccdc12e7ff1b6e6597202321
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DebugLoc.h" 51#include "llvm/CodeGen/DwarfWriter.h" 52#include "llvm/Analysis/DebugInfo.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "SelectionDAGBuild.h" 58using namespace llvm; 59 60unsigned FastISel::getRegForValue(Value *V) { 61 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 62 // Don't handle non-simple values in FastISel. 63 if (!RealVT.isSimple()) 64 return 0; 65 66 // Ignore illegal types. We must do this before looking up the value 67 // in ValueMap because Arguments are given virtual registers regardless 68 // of whether FastISel can handle them. 69 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 70 if (!TLI.isTypeLegal(VT)) { 71 // Promote MVT::i1 to a legal type though, because it's common and easy. 72 if (VT == MVT::i1) 73 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 74 else 75 return 0; 76 } 77 78 // Look up the value to see if we already have a register for it. We 79 // cache values defined by Instructions across blocks, and other values 80 // only locally. This is because Instructions already have the SSA 81 // def-dominatess-use requirement enforced. 82 if (ValueMap.count(V)) 83 return ValueMap[V]; 84 unsigned Reg = LocalValueMap[V]; 85 if (Reg != 0) 86 return Reg; 87 88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 89 if (CI->getValue().getActiveBits() <= 64) 90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 91 } else if (isa<AllocaInst>(V)) { 92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 93 } else if (isa<ConstantPointerNull>(V)) { 94 // Translate this as an integer zero so that it can be 95 // local-CSE'd with actual integer zeros. 96 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 99 100 if (!Reg) { 101 const APFloat &Flt = CF->getValueAPF(); 102 MVT IntVT = TLI.getPointerTy(); 103 104 uint64_t x[2]; 105 uint32_t IntBitWidth = IntVT.getSizeInBits(); 106 bool isExact; 107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 108 APFloat::rmTowardZero, &isExact); 109 if (isExact) { 110 APInt IntVal(IntBitWidth, 2, x); 111 112 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 113 if (IntegerReg != 0) 114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 115 } 116 } 117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 118 if (!SelectOperator(CE, CE->getOpcode())) return 0; 119 Reg = LocalValueMap[CE]; 120 } else if (isa<UndefValue>(V)) { 121 Reg = createResultReg(TLI.getRegClassFor(VT)); 122 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 123 } 124 125 // If target-independent code couldn't handle the value, give target-specific 126 // code a try. 127 if (!Reg && isa<Constant>(V)) 128 Reg = TargetMaterializeConstant(cast<Constant>(V)); 129 130 // Don't cache constant materializations in the general ValueMap. 131 // To do so would require tracking what uses they dominate. 132 if (Reg != 0) 133 LocalValueMap[V] = Reg; 134 return Reg; 135} 136 137unsigned FastISel::lookUpRegForValue(Value *V) { 138 // Look up the value to see if we already have a register for it. We 139 // cache values defined by Instructions across blocks, and other values 140 // only locally. This is because Instructions already have the SSA 141 // def-dominatess-use requirement enforced. 142 if (ValueMap.count(V)) 143 return ValueMap[V]; 144 return LocalValueMap[V]; 145} 146 147/// UpdateValueMap - Update the value map to include the new mapping for this 148/// instruction, or insert an extra copy to get the result in a previous 149/// determined register. 150/// NOTE: This is only necessary because we might select a block that uses 151/// a value before we select the block that defines the value. It might be 152/// possible to fix this by selecting blocks in reverse postorder. 153unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 154 if (!isa<Instruction>(I)) { 155 LocalValueMap[I] = Reg; 156 return Reg; 157 } 158 159 unsigned &AssignedReg = ValueMap[I]; 160 if (AssignedReg == 0) 161 AssignedReg = Reg; 162 else if (Reg != AssignedReg) { 163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 165 Reg, RegClass, RegClass); 166 } 167 return AssignedReg; 168} 169 170unsigned FastISel::getRegForGEPIndex(Value *Idx) { 171 unsigned IdxN = getRegForValue(Idx); 172 if (IdxN == 0) 173 // Unhandled operand. Halt "fast" selection and bail. 174 return 0; 175 176 // If the index is smaller or larger than intptr_t, truncate or extend it. 177 MVT PtrVT = TLI.getPointerTy(); 178 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 179 if (IdxVT.bitsLT(PtrVT)) 180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 181 ISD::SIGN_EXTEND, IdxN); 182 else if (IdxVT.bitsGT(PtrVT)) 183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 184 ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 192 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypePaddedSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 unsigned IID = F->getIntrinsicID(); 326 switch (IID) { 327 default: break; 328 case Intrinsic::dbg_stoppoint: { 329 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 330 if (DW && DW->ValidDebugInfo(SPI->getContext(), true)) { 331 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 332 std::string Dir, FN; 333 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), 334 CU.getFilename(FN)); 335 unsigned Line = SPI->getLine(); 336 unsigned Col = SPI->getColumn(); 337 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 338 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); 339 setCurDebugLoc(DebugLoc::get(Idx)); 340 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 341 BuildMI(MBB, DL, II).addImm(ID); 342 } 343 return true; 344 } 345 case Intrinsic::dbg_region_start: { 346 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 347 if (DW && DW->ValidDebugInfo(RSI->getContext(), true)) { 348 unsigned ID = 349 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 350 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 351 BuildMI(MBB, DL, II).addImm(ID); 352 } 353 return true; 354 } 355 case Intrinsic::dbg_region_end: { 356 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 357 if (DW && DW->ValidDebugInfo(REI->getContext(), true)) { 358 unsigned ID = 0; 359 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); 360 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { 361 // This is end of an inlined function. 362 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 363 ID = DW->RecordInlinedFnEnd(Subprogram); 364 if (ID) 365 // If ID is 0 then this was not an end of inlined region. 366 BuildMI(MBB, DL, II).addImm(ID); 367 } else { 368 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 369 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 370 BuildMI(MBB, DL, II).addImm(ID); 371 } 372 } 373 return true; 374 } 375 case Intrinsic::dbg_func_start: { 376 if (!DW) return true; 377 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 378 Value *SP = FSI->getSubprogram(); 379 380 if (DW->ValidDebugInfo(SP, true)) { 381 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 382 // (most?) gdb expects. 383 DebugLoc PrevLoc = DL; 384 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 385 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 386 std::string Dir, FN; 387 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir), 388 CompileUnit.getFilename(FN)); 389 390 // Record the source line. 391 unsigned Line = Subprogram.getLineNumber(); 392 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); 393 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); 394 if (!Subprogram.describes(MF.getFunction())) { 395 // This is a beginning of an inlined function. 396 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 397 BuildMI(MBB, DL, II).addImm(LabelID); 398 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc); 399 DW->RecordInlinedFnStart(FSI, Subprogram, LabelID, 400 PrevLocTpl.Src, 401 PrevLocTpl.Line, 402 PrevLocTpl.Col); 403 } else { 404 // llvm.dbg.func_start also defines beginning of function scope. 405 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 406 } 407 } 408 409 return true; 410 } 411 case Intrinsic::dbg_declare: { 412 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 413 Value *Variable = DI->getVariable(); 414 if (DW && DW->ValidDebugInfo(Variable, true)) { 415 // Determine the address of the declared object. 416 Value *Address = DI->getAddress(); 417 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 418 Address = BCI->getOperand(0); 419 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 420 // Don't handle byval struct arguments or VLAs, for example. 421 if (!AI) break; 422 DenseMap<const AllocaInst*, int>::iterator SI = 423 StaticAllocaMap.find(AI); 424 if (SI == StaticAllocaMap.end()) break; // VLAs. 425 int FI = SI->second; 426 427 // Determine the debug globalvariable. 428 GlobalValue *GV = cast<GlobalVariable>(Variable); 429 430 // Build the DECLARE instruction. 431 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 432 MachineInstr *DeclareMI 433 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 434 DIVariable DV(cast<GlobalVariable>(GV)); 435 if (!DV.isNull()) { 436 // This is a local variable 437 DW->RecordVariableScope(DV, DeclareMI); 438 } 439 } 440 return true; 441 } 442 case Intrinsic::eh_exception: { 443 MVT VT = TLI.getValueType(I->getType()); 444 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 445 default: break; 446 case TargetLowering::Expand: { 447 if (!MBB->isLandingPad()) { 448 // FIXME: Mark exception register as live in. Hack for PR1508. 449 unsigned Reg = TLI.getExceptionAddressRegister(); 450 if (Reg) MBB->addLiveIn(Reg); 451 } 452 unsigned Reg = TLI.getExceptionAddressRegister(); 453 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 454 unsigned ResultReg = createResultReg(RC); 455 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 456 Reg, RC, RC); 457 assert(InsertedCopy && "Can't copy address registers!"); 458 InsertedCopy = InsertedCopy; 459 UpdateValueMap(I, ResultReg); 460 return true; 461 } 462 } 463 break; 464 } 465 case Intrinsic::eh_selector_i32: 466 case Intrinsic::eh_selector_i64: { 467 MVT VT = TLI.getValueType(I->getType()); 468 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 469 default: break; 470 case TargetLowering::Expand: { 471 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 472 MVT::i32 : MVT::i64); 473 474 if (MMI) { 475 if (MBB->isLandingPad()) 476 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 477 else { 478#ifndef NDEBUG 479 CatchInfoLost.insert(cast<CallInst>(I)); 480#endif 481 // FIXME: Mark exception selector register as live in. Hack for PR1508. 482 unsigned Reg = TLI.getExceptionSelectorRegister(); 483 if (Reg) MBB->addLiveIn(Reg); 484 } 485 486 unsigned Reg = TLI.getExceptionSelectorRegister(); 487 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 488 unsigned ResultReg = createResultReg(RC); 489 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 490 Reg, RC, RC); 491 assert(InsertedCopy && "Can't copy address registers!"); 492 InsertedCopy = InsertedCopy; 493 UpdateValueMap(I, ResultReg); 494 } else { 495 unsigned ResultReg = 496 getRegForValue(Constant::getNullValue(I->getType())); 497 UpdateValueMap(I, ResultReg); 498 } 499 return true; 500 } 501 } 502 break; 503 } 504 } 505 return false; 506} 507 508bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 509 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 510 MVT DstVT = TLI.getValueType(I->getType()); 511 512 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 513 DstVT == MVT::Other || !DstVT.isSimple()) 514 // Unhandled type. Halt "fast" selection and bail. 515 return false; 516 517 // Check if the destination type is legal. Or as a special case, 518 // it may be i1 if we're doing a truncate because that's 519 // easy and somewhat common. 520 if (!TLI.isTypeLegal(DstVT)) 521 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 522 // Unhandled type. Halt "fast" selection and bail. 523 return false; 524 525 // Check if the source operand is legal. Or as a special case, 526 // it may be i1 if we're doing zero-extension because that's 527 // easy and somewhat common. 528 if (!TLI.isTypeLegal(SrcVT)) 529 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 530 // Unhandled type. Halt "fast" selection and bail. 531 return false; 532 533 unsigned InputReg = getRegForValue(I->getOperand(0)); 534 if (!InputReg) 535 // Unhandled operand. Halt "fast" selection and bail. 536 return false; 537 538 // If the operand is i1, arrange for the high bits in the register to be zero. 539 if (SrcVT == MVT::i1) { 540 SrcVT = TLI.getTypeToTransformTo(SrcVT); 541 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 542 if (!InputReg) 543 return false; 544 } 545 // If the result is i1, truncate to the target's type for i1 first. 546 if (DstVT == MVT::i1) 547 DstVT = TLI.getTypeToTransformTo(DstVT); 548 549 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 550 DstVT.getSimpleVT(), 551 Opcode, 552 InputReg); 553 if (!ResultReg) 554 return false; 555 556 UpdateValueMap(I, ResultReg); 557 return true; 558} 559 560bool FastISel::SelectBitCast(User *I) { 561 // If the bitcast doesn't change the type, just use the operand value. 562 if (I->getType() == I->getOperand(0)->getType()) { 563 unsigned Reg = getRegForValue(I->getOperand(0)); 564 if (Reg == 0) 565 return false; 566 UpdateValueMap(I, Reg); 567 return true; 568 } 569 570 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 571 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 572 MVT DstVT = TLI.getValueType(I->getType()); 573 574 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 575 DstVT == MVT::Other || !DstVT.isSimple() || 576 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 577 // Unhandled type. Halt "fast" selection and bail. 578 return false; 579 580 unsigned Op0 = getRegForValue(I->getOperand(0)); 581 if (Op0 == 0) 582 // Unhandled operand. Halt "fast" selection and bail. 583 return false; 584 585 // First, try to perform the bitcast by inserting a reg-reg copy. 586 unsigned ResultReg = 0; 587 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 588 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 589 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 590 ResultReg = createResultReg(DstClass); 591 592 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 593 Op0, DstClass, SrcClass); 594 if (!InsertedCopy) 595 ResultReg = 0; 596 } 597 598 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 599 if (!ResultReg) 600 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 601 ISD::BIT_CONVERT, Op0); 602 603 if (!ResultReg) 604 return false; 605 606 UpdateValueMap(I, ResultReg); 607 return true; 608} 609 610bool 611FastISel::SelectInstruction(Instruction *I) { 612 return SelectOperator(I, I->getOpcode()); 613} 614 615/// FastEmitBranch - Emit an unconditional branch to the given block, 616/// unless it is the immediate (fall-through) successor, and update 617/// the CFG. 618void 619FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 620 MachineFunction::iterator NextMBB = 621 next(MachineFunction::iterator(MBB)); 622 623 if (MBB->isLayoutSuccessor(MSucc)) { 624 // The unconditional fall-through case, which needs no instructions. 625 } else { 626 // The unconditional branch case. 627 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 628 } 629 MBB->addSuccessor(MSucc); 630} 631 632bool 633FastISel::SelectOperator(User *I, unsigned Opcode) { 634 switch (Opcode) { 635 case Instruction::Add: { 636 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 637 return SelectBinaryOp(I, Opc); 638 } 639 case Instruction::Sub: { 640 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 641 return SelectBinaryOp(I, Opc); 642 } 643 case Instruction::Mul: { 644 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 645 return SelectBinaryOp(I, Opc); 646 } 647 case Instruction::SDiv: 648 return SelectBinaryOp(I, ISD::SDIV); 649 case Instruction::UDiv: 650 return SelectBinaryOp(I, ISD::UDIV); 651 case Instruction::FDiv: 652 return SelectBinaryOp(I, ISD::FDIV); 653 case Instruction::SRem: 654 return SelectBinaryOp(I, ISD::SREM); 655 case Instruction::URem: 656 return SelectBinaryOp(I, ISD::UREM); 657 case Instruction::FRem: 658 return SelectBinaryOp(I, ISD::FREM); 659 case Instruction::Shl: 660 return SelectBinaryOp(I, ISD::SHL); 661 case Instruction::LShr: 662 return SelectBinaryOp(I, ISD::SRL); 663 case Instruction::AShr: 664 return SelectBinaryOp(I, ISD::SRA); 665 case Instruction::And: 666 return SelectBinaryOp(I, ISD::AND); 667 case Instruction::Or: 668 return SelectBinaryOp(I, ISD::OR); 669 case Instruction::Xor: 670 return SelectBinaryOp(I, ISD::XOR); 671 672 case Instruction::GetElementPtr: 673 return SelectGetElementPtr(I); 674 675 case Instruction::Br: { 676 BranchInst *BI = cast<BranchInst>(I); 677 678 if (BI->isUnconditional()) { 679 BasicBlock *LLVMSucc = BI->getSuccessor(0); 680 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 681 FastEmitBranch(MSucc); 682 return true; 683 } 684 685 // Conditional branches are not handed yet. 686 // Halt "fast" selection and bail. 687 return false; 688 } 689 690 case Instruction::Unreachable: 691 // Nothing to emit. 692 return true; 693 694 case Instruction::PHI: 695 // PHI nodes are already emitted. 696 return true; 697 698 case Instruction::Alloca: 699 // FunctionLowering has the static-sized case covered. 700 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 701 return true; 702 703 // Dynamic-sized alloca is not handled yet. 704 return false; 705 706 case Instruction::Call: 707 return SelectCall(I); 708 709 case Instruction::BitCast: 710 return SelectBitCast(I); 711 712 case Instruction::FPToSI: 713 return SelectCast(I, ISD::FP_TO_SINT); 714 case Instruction::ZExt: 715 return SelectCast(I, ISD::ZERO_EXTEND); 716 case Instruction::SExt: 717 return SelectCast(I, ISD::SIGN_EXTEND); 718 case Instruction::Trunc: 719 return SelectCast(I, ISD::TRUNCATE); 720 case Instruction::SIToFP: 721 return SelectCast(I, ISD::SINT_TO_FP); 722 723 case Instruction::IntToPtr: // Deliberate fall-through. 724 case Instruction::PtrToInt: { 725 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 726 MVT DstVT = TLI.getValueType(I->getType()); 727 if (DstVT.bitsGT(SrcVT)) 728 return SelectCast(I, ISD::ZERO_EXTEND); 729 if (DstVT.bitsLT(SrcVT)) 730 return SelectCast(I, ISD::TRUNCATE); 731 unsigned Reg = getRegForValue(I->getOperand(0)); 732 if (Reg == 0) return false; 733 UpdateValueMap(I, Reg); 734 return true; 735 } 736 737 default: 738 // Unhandled instruction. Halt "fast" selection and bail. 739 return false; 740 } 741} 742 743FastISel::FastISel(MachineFunction &mf, 744 MachineModuleInfo *mmi, 745 DwarfWriter *dw, 746 DenseMap<const Value *, unsigned> &vm, 747 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 748 DenseMap<const AllocaInst *, int> &am 749#ifndef NDEBUG 750 , SmallSet<Instruction*, 8> &cil 751#endif 752 ) 753 : MBB(0), 754 ValueMap(vm), 755 MBBMap(bm), 756 StaticAllocaMap(am), 757#ifndef NDEBUG 758 CatchInfoLost(cil), 759#endif 760 MF(mf), 761 MMI(mmi), 762 DW(dw), 763 MRI(MF.getRegInfo()), 764 MFI(*MF.getFrameInfo()), 765 MCP(*MF.getConstantPool()), 766 TM(MF.getTarget()), 767 TD(*TM.getTargetData()), 768 TII(*TM.getInstrInfo()), 769 TLI(*TM.getTargetLowering()) { 770} 771 772FastISel::~FastISel() {} 773 774unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 775 ISD::NodeType) { 776 return 0; 777} 778 779unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 780 ISD::NodeType, unsigned /*Op0*/) { 781 return 0; 782} 783 784unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 785 ISD::NodeType, unsigned /*Op0*/, 786 unsigned /*Op0*/) { 787 return 0; 788} 789 790unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 791 ISD::NodeType, uint64_t /*Imm*/) { 792 return 0; 793} 794 795unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 796 ISD::NodeType, ConstantFP * /*FPImm*/) { 797 return 0; 798} 799 800unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 801 ISD::NodeType, unsigned /*Op0*/, 802 uint64_t /*Imm*/) { 803 return 0; 804} 805 806unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 807 ISD::NodeType, unsigned /*Op0*/, 808 ConstantFP * /*FPImm*/) { 809 return 0; 810} 811 812unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 813 ISD::NodeType, 814 unsigned /*Op0*/, unsigned /*Op1*/, 815 uint64_t /*Imm*/) { 816 return 0; 817} 818 819/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 820/// to emit an instruction with an immediate operand using FastEmit_ri. 821/// If that fails, it materializes the immediate into a register and try 822/// FastEmit_rr instead. 823unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 824 unsigned Op0, uint64_t Imm, 825 MVT::SimpleValueType ImmType) { 826 // First check if immediate type is legal. If not, we can't use the ri form. 827 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 828 if (ResultReg != 0) 829 return ResultReg; 830 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 831 if (MaterialReg == 0) 832 return 0; 833 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 834} 835 836/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 837/// to emit an instruction with a floating-point immediate operand using 838/// FastEmit_rf. If that fails, it materializes the immediate into a register 839/// and try FastEmit_rr instead. 840unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 841 unsigned Op0, ConstantFP *FPImm, 842 MVT::SimpleValueType ImmType) { 843 // First check if immediate type is legal. If not, we can't use the rf form. 844 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 845 if (ResultReg != 0) 846 return ResultReg; 847 848 // Materialize the constant in a register. 849 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 850 if (MaterialReg == 0) { 851 // If the target doesn't have a way to directly enter a floating-point 852 // value into a register, use an alternate approach. 853 // TODO: The current approach only supports floating-point constants 854 // that can be constructed by conversion from integer values. This should 855 // be replaced by code that creates a load from a constant-pool entry, 856 // which will require some target-specific work. 857 const APFloat &Flt = FPImm->getValueAPF(); 858 MVT IntVT = TLI.getPointerTy(); 859 860 uint64_t x[2]; 861 uint32_t IntBitWidth = IntVT.getSizeInBits(); 862 bool isExact; 863 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 864 APFloat::rmTowardZero, &isExact); 865 if (!isExact) 866 return 0; 867 APInt IntVal(IntBitWidth, 2, x); 868 869 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 870 ISD::Constant, IntVal.getZExtValue()); 871 if (IntegerReg == 0) 872 return 0; 873 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 874 ISD::SINT_TO_FP, IntegerReg); 875 if (MaterialReg == 0) 876 return 0; 877 } 878 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 879} 880 881unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 882 return MRI.createVirtualRegister(RC); 883} 884 885unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 886 const TargetRegisterClass* RC) { 887 unsigned ResultReg = createResultReg(RC); 888 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 889 890 BuildMI(MBB, DL, II, ResultReg); 891 return ResultReg; 892} 893 894unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 895 const TargetRegisterClass *RC, 896 unsigned Op0) { 897 unsigned ResultReg = createResultReg(RC); 898 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 899 900 if (II.getNumDefs() >= 1) 901 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 902 else { 903 BuildMI(MBB, DL, II).addReg(Op0); 904 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 905 II.ImplicitDefs[0], RC, RC); 906 if (!InsertedCopy) 907 ResultReg = 0; 908 } 909 910 return ResultReg; 911} 912 913unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 914 const TargetRegisterClass *RC, 915 unsigned Op0, unsigned Op1) { 916 unsigned ResultReg = createResultReg(RC); 917 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 918 919 if (II.getNumDefs() >= 1) 920 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 921 else { 922 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 923 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 924 II.ImplicitDefs[0], RC, RC); 925 if (!InsertedCopy) 926 ResultReg = 0; 927 } 928 return ResultReg; 929} 930 931unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 932 const TargetRegisterClass *RC, 933 unsigned Op0, uint64_t Imm) { 934 unsigned ResultReg = createResultReg(RC); 935 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 936 937 if (II.getNumDefs() >= 1) 938 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 939 else { 940 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 941 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 942 II.ImplicitDefs[0], RC, RC); 943 if (!InsertedCopy) 944 ResultReg = 0; 945 } 946 return ResultReg; 947} 948 949unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 950 const TargetRegisterClass *RC, 951 unsigned Op0, ConstantFP *FPImm) { 952 unsigned ResultReg = createResultReg(RC); 953 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 954 955 if (II.getNumDefs() >= 1) 956 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 957 else { 958 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 959 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 960 II.ImplicitDefs[0], RC, RC); 961 if (!InsertedCopy) 962 ResultReg = 0; 963 } 964 return ResultReg; 965} 966 967unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 968 const TargetRegisterClass *RC, 969 unsigned Op0, unsigned Op1, uint64_t Imm) { 970 unsigned ResultReg = createResultReg(RC); 971 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 972 973 if (II.getNumDefs() >= 1) 974 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 975 else { 976 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 977 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 978 II.ImplicitDefs[0], RC, RC); 979 if (!InsertedCopy) 980 ResultReg = 0; 981 } 982 return ResultReg; 983} 984 985unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 986 const TargetRegisterClass *RC, 987 uint64_t Imm) { 988 unsigned ResultReg = createResultReg(RC); 989 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 990 991 if (II.getNumDefs() >= 1) 992 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 993 else { 994 BuildMI(MBB, DL, II).addImm(Imm); 995 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 996 II.ImplicitDefs[0], RC, RC); 997 if (!InsertedCopy) 998 ResultReg = 0; 999 } 1000 return ResultReg; 1001} 1002 1003unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 1004 unsigned Op0, uint32_t Idx) { 1005 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 1006 1007 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1008 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 1009 1010 if (II.getNumDefs() >= 1) 1011 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 1012 else { 1013 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1014 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1015 II.ImplicitDefs[0], RC, RC); 1016 if (!InsertedCopy) 1017 ResultReg = 0; 1018 } 1019 return ResultReg; 1020} 1021 1022/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1023/// with all but the least significant bit set to zero. 1024unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 1025 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1026} 1027