FastISel.cpp revision 2057532679fc1045cfeb38b477ac9e749e6b1dd8
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuild.h" 57using namespace llvm; 58 59unsigned FastISel::getRegForValue(Value *V) { 60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 61 // Don't handle non-simple values in FastISel. 62 if (!RealVT.isSimple()) 63 return 0; 64 65 // Ignore illegal types. We must do this before looking up the value 66 // in ValueMap because Arguments are given virtual registers regardless 67 // of whether FastISel can handle them. 68 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 69 if (!TLI.isTypeLegal(VT)) { 70 // Promote MVT::i1 to a legal type though, because it's common and easy. 71 if (VT == MVT::i1) 72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 73 else 74 return 0; 75 } 76 77 // Look up the value to see if we already have a register for it. We 78 // cache values defined by Instructions across blocks, and other values 79 // only locally. This is because Instructions already have the SSA 80 // def-dominatess-use requirement enforced. 81 if (ValueMap.count(V)) 82 return ValueMap[V]; 83 unsigned Reg = LocalValueMap[V]; 84 if (Reg != 0) 85 return Reg; 86 87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 88 if (CI->getValue().getActiveBits() <= 64) 89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 90 } else if (isa<AllocaInst>(V)) { 91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 92 } else if (isa<ConstantPointerNull>(V)) { 93 // Translate this as an integer zero so that it can be 94 // local-CSE'd with actual integer zeros. 95 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 98 99 if (!Reg) { 100 const APFloat &Flt = CF->getValueAPF(); 101 MVT IntVT = TLI.getPointerTy(); 102 103 uint64_t x[2]; 104 uint32_t IntBitWidth = IntVT.getSizeInBits(); 105 bool isExact; 106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 107 APFloat::rmTowardZero, &isExact); 108 if (isExact) { 109 APInt IntVal(IntBitWidth, 2, x); 110 111 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 112 if (IntegerReg != 0) 113 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 114 } 115 } 116 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 117 if (!SelectOperator(CE, CE->getOpcode())) return 0; 118 Reg = LocalValueMap[CE]; 119 } else if (isa<UndefValue>(V)) { 120 Reg = createResultReg(TLI.getRegClassFor(VT)); 121 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 122 } 123 124 // If target-independent code couldn't handle the value, give target-specific 125 // code a try. 126 if (!Reg && isa<Constant>(V)) 127 Reg = TargetMaterializeConstant(cast<Constant>(V)); 128 129 // Don't cache constant materializations in the general ValueMap. 130 // To do so would require tracking what uses they dominate. 131 if (Reg != 0) 132 LocalValueMap[V] = Reg; 133 return Reg; 134} 135 136unsigned FastISel::lookUpRegForValue(Value *V) { 137 // Look up the value to see if we already have a register for it. We 138 // cache values defined by Instructions across blocks, and other values 139 // only locally. This is because Instructions already have the SSA 140 // def-dominatess-use requirement enforced. 141 if (ValueMap.count(V)) 142 return ValueMap[V]; 143 return LocalValueMap[V]; 144} 145 146/// UpdateValueMap - Update the value map to include the new mapping for this 147/// instruction, or insert an extra copy to get the result in a previous 148/// determined register. 149/// NOTE: This is only necessary because we might select a block that uses 150/// a value before we select the block that defines the value. It might be 151/// possible to fix this by selecting blocks in reverse postorder. 152void FastISel::UpdateValueMap(Value* I, unsigned Reg) { 153 if (!isa<Instruction>(I)) { 154 LocalValueMap[I] = Reg; 155 return; 156 } 157 if (!ValueMap.count(I)) 158 ValueMap[I] = Reg; 159 else 160 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I], 161 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg)); 162} 163 164unsigned FastISel::getRegForGEPIndex(Value *Idx) { 165 unsigned IdxN = getRegForValue(Idx); 166 if (IdxN == 0) 167 // Unhandled operand. Halt "fast" selection and bail. 168 return 0; 169 170 // If the index is smaller or larger than intptr_t, truncate or extend it. 171 MVT PtrVT = TLI.getPointerTy(); 172 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 173 if (IdxVT.bitsLT(PtrVT)) 174 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 175 ISD::SIGN_EXTEND, IdxN); 176 else if (IdxVT.bitsGT(PtrVT)) 177 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 178 ISD::TRUNCATE, IdxN); 179 return IdxN; 180} 181 182/// SelectBinaryOp - Select and emit code for a binary operator instruction, 183/// which has an opcode which directly corresponds to the given ISD opcode. 184/// 185bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 186 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 187 if (VT == MVT::Other || !VT.isSimple()) 188 // Unhandled type. Halt "fast" selection and bail. 189 return false; 190 191 // We only handle legal types. For example, on x86-32 the instruction 192 // selector contains all of the 64-bit instructions from x86-64, 193 // under the assumption that i64 won't be used if the target doesn't 194 // support it. 195 if (!TLI.isTypeLegal(VT)) { 196 // MVT::i1 is special. Allow AND, OR, or XOR because they 197 // don't require additional zeroing, which makes them easy. 198 if (VT == MVT::i1 && 199 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 200 ISDOpcode == ISD::XOR)) 201 VT = TLI.getTypeToTransformTo(VT); 202 else 203 return false; 204 } 205 206 unsigned Op0 = getRegForValue(I->getOperand(0)); 207 if (Op0 == 0) 208 // Unhandled operand. Halt "fast" selection and bail. 209 return false; 210 211 // Check if the second operand is a constant and handle it appropriately. 212 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 213 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 214 ISDOpcode, Op0, CI->getZExtValue()); 215 if (ResultReg != 0) { 216 // We successfully emitted code for the given LLVM Instruction. 217 UpdateValueMap(I, ResultReg); 218 return true; 219 } 220 } 221 222 // Check if the second operand is a constant float. 223 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 224 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 225 ISDOpcode, Op0, CF); 226 if (ResultReg != 0) { 227 // We successfully emitted code for the given LLVM Instruction. 228 UpdateValueMap(I, ResultReg); 229 return true; 230 } 231 } 232 233 unsigned Op1 = getRegForValue(I->getOperand(1)); 234 if (Op1 == 0) 235 // Unhandled operand. Halt "fast" selection and bail. 236 return false; 237 238 // Now we have both operands in registers. Emit the instruction. 239 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 240 ISDOpcode, Op0, Op1); 241 if (ResultReg == 0) 242 // Target-specific code wasn't able to find a machine opcode for 243 // the given ISD opcode and type. Halt "fast" selection and bail. 244 return false; 245 246 // We successfully emitted code for the given LLVM Instruction. 247 UpdateValueMap(I, ResultReg); 248 return true; 249} 250 251bool FastISel::SelectGetElementPtr(User *I) { 252 unsigned N = getRegForValue(I->getOperand(0)); 253 if (N == 0) 254 // Unhandled operand. Halt "fast" selection and bail. 255 return false; 256 257 const Type *Ty = I->getOperand(0)->getType(); 258 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 259 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 260 OI != E; ++OI) { 261 Value *Idx = *OI; 262 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 263 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 264 if (Field) { 265 // N = N + Offset 266 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 267 // FIXME: This can be optimized by combining the add with a 268 // subsequent one. 269 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 270 if (N == 0) 271 // Unhandled operand. Halt "fast" selection and bail. 272 return false; 273 } 274 Ty = StTy->getElementType(Field); 275 } else { 276 Ty = cast<SequentialType>(Ty)->getElementType(); 277 278 // If this is a constant subscript, handle it quickly. 279 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 280 if (CI->getZExtValue() == 0) continue; 281 uint64_t Offs = 282 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 283 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 284 if (N == 0) 285 // Unhandled operand. Halt "fast" selection and bail. 286 return false; 287 continue; 288 } 289 290 // N = N + Idx * ElementSize; 291 uint64_t ElementSize = TD.getTypePaddedSize(Ty); 292 unsigned IdxN = getRegForGEPIndex(Idx); 293 if (IdxN == 0) 294 // Unhandled operand. Halt "fast" selection and bail. 295 return false; 296 297 if (ElementSize != 1) { 298 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 } 303 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 304 if (N == 0) 305 // Unhandled operand. Halt "fast" selection and bail. 306 return false; 307 } 308 } 309 310 // We successfully emitted code for the given LLVM Instruction. 311 UpdateValueMap(I, N); 312 return true; 313} 314 315bool FastISel::SelectCall(User *I) { 316 Function *F = cast<CallInst>(I)->getCalledFunction(); 317 if (!F) return false; 318 319 unsigned IID = F->getIntrinsicID(); 320 switch (IID) { 321 default: break; 322 case Intrinsic::dbg_stoppoint: { 323 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 324 if (DW && DW->ValidDebugInfo(SPI->getContext())) { 325 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 326 std::string Dir, FN; 327 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir), 328 CU.getFilename(FN)); 329 unsigned Line = SPI->getLine(); 330 unsigned Col = SPI->getColumn(); 331 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 332 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); 333 setCurDebugLoc(DebugLoc::get(Idx)); 334 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 335 BuildMI(MBB, DL, II).addImm(ID); 336 } 337 return true; 338 } 339 case Intrinsic::dbg_region_start: { 340 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 341 if (DW && DW->ValidDebugInfo(RSI->getContext())) { 342 unsigned ID = 343 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 344 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 345 BuildMI(MBB, DL, II).addImm(ID); 346 } 347 return true; 348 } 349 case Intrinsic::dbg_region_end: { 350 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 351 if (DW && DW->ValidDebugInfo(REI->getContext())) { 352 unsigned ID = 353 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 354 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 355 BuildMI(MBB, DL, II).addImm(ID); 356 } 357 return true; 358 } 359 case Intrinsic::dbg_func_start: { 360 if (!DW) return true; 361 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 362 Value *SP = FSI->getSubprogram(); 363 364 if (DW->ValidDebugInfo(SP)) { 365 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 366 // (most?) gdb expects. 367 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 368 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 369 std::string Dir, FN; 370 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir), 371 CompileUnit.getFilename(FN)); 372 373 // Record the source line. 374 unsigned Line = Subprogram.getLineNumber(); 375 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); 376 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); 377 378 std::string SPName; 379 Subprogram.getLinkageName(SPName); 380 if (!SPName.empty() 381 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) { 382 // This is a beginning of inlined function. 383 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()), 384 LabelID); 385 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 386 BuildMI(MBB, DL, II).addImm(LabelID); 387 DW->RecordInlineInfo(Subprogram.getGV(), LabelID); 388 } else { 389 // llvm.dbg.func_start also defines beginning of function scope. 390 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 391 } 392 } 393 394 return true; 395 } 396 case Intrinsic::dbg_declare: { 397 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 398 Value *Variable = DI->getVariable(); 399 if (DW && DW->ValidDebugInfo(Variable)) { 400 // Determine the address of the declared object. 401 Value *Address = DI->getAddress(); 402 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 403 Address = BCI->getOperand(0); 404 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 405 // Don't handle byval struct arguments or VLAs, for example. 406 if (!AI) break; 407 DenseMap<const AllocaInst*, int>::iterator SI = 408 StaticAllocaMap.find(AI); 409 if (SI == StaticAllocaMap.end()) break; // VLAs. 410 int FI = SI->second; 411 412 // Determine the debug globalvariable. 413 GlobalValue *GV = cast<GlobalVariable>(Variable); 414 415 // Build the DECLARE instruction. 416 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 417 BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 418 } 419 return true; 420 } 421 case Intrinsic::eh_exception: { 422 MVT VT = TLI.getValueType(I->getType()); 423 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 424 default: break; 425 case TargetLowering::Expand: { 426 if (!MBB->isLandingPad()) { 427 // FIXME: Mark exception register as live in. Hack for PR1508. 428 unsigned Reg = TLI.getExceptionAddressRegister(); 429 if (Reg) MBB->addLiveIn(Reg); 430 } 431 unsigned Reg = TLI.getExceptionAddressRegister(); 432 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 433 unsigned ResultReg = createResultReg(RC); 434 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 435 Reg, RC, RC); 436 assert(InsertedCopy && "Can't copy address registers!"); 437 InsertedCopy = InsertedCopy; 438 UpdateValueMap(I, ResultReg); 439 return true; 440 } 441 } 442 break; 443 } 444 case Intrinsic::eh_selector_i32: 445 case Intrinsic::eh_selector_i64: { 446 MVT VT = TLI.getValueType(I->getType()); 447 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 448 default: break; 449 case TargetLowering::Expand: { 450 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 451 MVT::i32 : MVT::i64); 452 453 if (MMI) { 454 if (MBB->isLandingPad()) 455 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 456 else { 457#ifndef NDEBUG 458 CatchInfoLost.insert(cast<CallInst>(I)); 459#endif 460 // FIXME: Mark exception selector register as live in. Hack for PR1508. 461 unsigned Reg = TLI.getExceptionSelectorRegister(); 462 if (Reg) MBB->addLiveIn(Reg); 463 } 464 465 unsigned Reg = TLI.getExceptionSelectorRegister(); 466 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 467 unsigned ResultReg = createResultReg(RC); 468 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 469 Reg, RC, RC); 470 assert(InsertedCopy && "Can't copy address registers!"); 471 InsertedCopy = InsertedCopy; 472 UpdateValueMap(I, ResultReg); 473 } else { 474 unsigned ResultReg = 475 getRegForValue(Constant::getNullValue(I->getType())); 476 UpdateValueMap(I, ResultReg); 477 } 478 return true; 479 } 480 } 481 break; 482 } 483 } 484 return false; 485} 486 487bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 488 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 489 MVT DstVT = TLI.getValueType(I->getType()); 490 491 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 492 DstVT == MVT::Other || !DstVT.isSimple()) 493 // Unhandled type. Halt "fast" selection and bail. 494 return false; 495 496 // Check if the destination type is legal. Or as a special case, 497 // it may be i1 if we're doing a truncate because that's 498 // easy and somewhat common. 499 if (!TLI.isTypeLegal(DstVT)) 500 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 501 // Unhandled type. Halt "fast" selection and bail. 502 return false; 503 504 // Check if the source operand is legal. Or as a special case, 505 // it may be i1 if we're doing zero-extension because that's 506 // easy and somewhat common. 507 if (!TLI.isTypeLegal(SrcVT)) 508 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 509 // Unhandled type. Halt "fast" selection and bail. 510 return false; 511 512 unsigned InputReg = getRegForValue(I->getOperand(0)); 513 if (!InputReg) 514 // Unhandled operand. Halt "fast" selection and bail. 515 return false; 516 517 // If the operand is i1, arrange for the high bits in the register to be zero. 518 if (SrcVT == MVT::i1) { 519 SrcVT = TLI.getTypeToTransformTo(SrcVT); 520 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 521 if (!InputReg) 522 return false; 523 } 524 // If the result is i1, truncate to the target's type for i1 first. 525 if (DstVT == MVT::i1) 526 DstVT = TLI.getTypeToTransformTo(DstVT); 527 528 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 529 DstVT.getSimpleVT(), 530 Opcode, 531 InputReg); 532 if (!ResultReg) 533 return false; 534 535 UpdateValueMap(I, ResultReg); 536 return true; 537} 538 539bool FastISel::SelectBitCast(User *I) { 540 // If the bitcast doesn't change the type, just use the operand value. 541 if (I->getType() == I->getOperand(0)->getType()) { 542 unsigned Reg = getRegForValue(I->getOperand(0)); 543 if (Reg == 0) 544 return false; 545 UpdateValueMap(I, Reg); 546 return true; 547 } 548 549 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 550 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 551 MVT DstVT = TLI.getValueType(I->getType()); 552 553 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 554 DstVT == MVT::Other || !DstVT.isSimple() || 555 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 556 // Unhandled type. Halt "fast" selection and bail. 557 return false; 558 559 unsigned Op0 = getRegForValue(I->getOperand(0)); 560 if (Op0 == 0) 561 // Unhandled operand. Halt "fast" selection and bail. 562 return false; 563 564 // First, try to perform the bitcast by inserting a reg-reg copy. 565 unsigned ResultReg = 0; 566 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 567 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 568 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 569 ResultReg = createResultReg(DstClass); 570 571 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 572 Op0, DstClass, SrcClass); 573 if (!InsertedCopy) 574 ResultReg = 0; 575 } 576 577 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 578 if (!ResultReg) 579 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 580 ISD::BIT_CONVERT, Op0); 581 582 if (!ResultReg) 583 return false; 584 585 UpdateValueMap(I, ResultReg); 586 return true; 587} 588 589bool 590FastISel::SelectInstruction(Instruction *I) { 591 return SelectOperator(I, I->getOpcode()); 592} 593 594/// FastEmitBranch - Emit an unconditional branch to the given block, 595/// unless it is the immediate (fall-through) successor, and update 596/// the CFG. 597void 598FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 599 MachineFunction::iterator NextMBB = 600 next(MachineFunction::iterator(MBB)); 601 602 if (MBB->isLayoutSuccessor(MSucc)) { 603 // The unconditional fall-through case, which needs no instructions. 604 } else { 605 // The unconditional branch case. 606 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 607 } 608 MBB->addSuccessor(MSucc); 609} 610 611bool 612FastISel::SelectOperator(User *I, unsigned Opcode) { 613 switch (Opcode) { 614 case Instruction::Add: { 615 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 616 return SelectBinaryOp(I, Opc); 617 } 618 case Instruction::Sub: { 619 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 620 return SelectBinaryOp(I, Opc); 621 } 622 case Instruction::Mul: { 623 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 624 return SelectBinaryOp(I, Opc); 625 } 626 case Instruction::SDiv: 627 return SelectBinaryOp(I, ISD::SDIV); 628 case Instruction::UDiv: 629 return SelectBinaryOp(I, ISD::UDIV); 630 case Instruction::FDiv: 631 return SelectBinaryOp(I, ISD::FDIV); 632 case Instruction::SRem: 633 return SelectBinaryOp(I, ISD::SREM); 634 case Instruction::URem: 635 return SelectBinaryOp(I, ISD::UREM); 636 case Instruction::FRem: 637 return SelectBinaryOp(I, ISD::FREM); 638 case Instruction::Shl: 639 return SelectBinaryOp(I, ISD::SHL); 640 case Instruction::LShr: 641 return SelectBinaryOp(I, ISD::SRL); 642 case Instruction::AShr: 643 return SelectBinaryOp(I, ISD::SRA); 644 case Instruction::And: 645 return SelectBinaryOp(I, ISD::AND); 646 case Instruction::Or: 647 return SelectBinaryOp(I, ISD::OR); 648 case Instruction::Xor: 649 return SelectBinaryOp(I, ISD::XOR); 650 651 case Instruction::GetElementPtr: 652 return SelectGetElementPtr(I); 653 654 case Instruction::Br: { 655 BranchInst *BI = cast<BranchInst>(I); 656 657 if (BI->isUnconditional()) { 658 BasicBlock *LLVMSucc = BI->getSuccessor(0); 659 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 660 FastEmitBranch(MSucc); 661 return true; 662 } 663 664 // Conditional branches are not handed yet. 665 // Halt "fast" selection and bail. 666 return false; 667 } 668 669 case Instruction::Unreachable: 670 // Nothing to emit. 671 return true; 672 673 case Instruction::PHI: 674 // PHI nodes are already emitted. 675 return true; 676 677 case Instruction::Alloca: 678 // FunctionLowering has the static-sized case covered. 679 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 680 return true; 681 682 // Dynamic-sized alloca is not handled yet. 683 return false; 684 685 case Instruction::Call: 686 return SelectCall(I); 687 688 case Instruction::BitCast: 689 return SelectBitCast(I); 690 691 case Instruction::FPToSI: 692 return SelectCast(I, ISD::FP_TO_SINT); 693 case Instruction::ZExt: 694 return SelectCast(I, ISD::ZERO_EXTEND); 695 case Instruction::SExt: 696 return SelectCast(I, ISD::SIGN_EXTEND); 697 case Instruction::Trunc: 698 return SelectCast(I, ISD::TRUNCATE); 699 case Instruction::SIToFP: 700 return SelectCast(I, ISD::SINT_TO_FP); 701 702 case Instruction::IntToPtr: // Deliberate fall-through. 703 case Instruction::PtrToInt: { 704 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 705 MVT DstVT = TLI.getValueType(I->getType()); 706 if (DstVT.bitsGT(SrcVT)) 707 return SelectCast(I, ISD::ZERO_EXTEND); 708 if (DstVT.bitsLT(SrcVT)) 709 return SelectCast(I, ISD::TRUNCATE); 710 unsigned Reg = getRegForValue(I->getOperand(0)); 711 if (Reg == 0) return false; 712 UpdateValueMap(I, Reg); 713 return true; 714 } 715 716 default: 717 // Unhandled instruction. Halt "fast" selection and bail. 718 return false; 719 } 720} 721 722FastISel::FastISel(MachineFunction &mf, 723 MachineModuleInfo *mmi, 724 DwarfWriter *dw, 725 DenseMap<const Value *, unsigned> &vm, 726 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 727 DenseMap<const AllocaInst *, int> &am 728#ifndef NDEBUG 729 , SmallSet<Instruction*, 8> &cil 730#endif 731 ) 732 : MBB(0), 733 ValueMap(vm), 734 MBBMap(bm), 735 StaticAllocaMap(am), 736#ifndef NDEBUG 737 CatchInfoLost(cil), 738#endif 739 MF(mf), 740 MMI(mmi), 741 DW(dw), 742 MRI(MF.getRegInfo()), 743 MFI(*MF.getFrameInfo()), 744 MCP(*MF.getConstantPool()), 745 TM(MF.getTarget()), 746 TD(*TM.getTargetData()), 747 TII(*TM.getInstrInfo()), 748 TLI(*TM.getTargetLowering()) { 749} 750 751FastISel::~FastISel() {} 752 753unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 754 ISD::NodeType) { 755 return 0; 756} 757 758unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 759 ISD::NodeType, unsigned /*Op0*/) { 760 return 0; 761} 762 763unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 764 ISD::NodeType, unsigned /*Op0*/, 765 unsigned /*Op0*/) { 766 return 0; 767} 768 769unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 770 ISD::NodeType, uint64_t /*Imm*/) { 771 return 0; 772} 773 774unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 775 ISD::NodeType, ConstantFP * /*FPImm*/) { 776 return 0; 777} 778 779unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 780 ISD::NodeType, unsigned /*Op0*/, 781 uint64_t /*Imm*/) { 782 return 0; 783} 784 785unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 786 ISD::NodeType, unsigned /*Op0*/, 787 ConstantFP * /*FPImm*/) { 788 return 0; 789} 790 791unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 792 ISD::NodeType, 793 unsigned /*Op0*/, unsigned /*Op1*/, 794 uint64_t /*Imm*/) { 795 return 0; 796} 797 798/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 799/// to emit an instruction with an immediate operand using FastEmit_ri. 800/// If that fails, it materializes the immediate into a register and try 801/// FastEmit_rr instead. 802unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 803 unsigned Op0, uint64_t Imm, 804 MVT::SimpleValueType ImmType) { 805 // First check if immediate type is legal. If not, we can't use the ri form. 806 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 807 if (ResultReg != 0) 808 return ResultReg; 809 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 810 if (MaterialReg == 0) 811 return 0; 812 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 813} 814 815/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 816/// to emit an instruction with a floating-point immediate operand using 817/// FastEmit_rf. If that fails, it materializes the immediate into a register 818/// and try FastEmit_rr instead. 819unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 820 unsigned Op0, ConstantFP *FPImm, 821 MVT::SimpleValueType ImmType) { 822 // First check if immediate type is legal. If not, we can't use the rf form. 823 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 824 if (ResultReg != 0) 825 return ResultReg; 826 827 // Materialize the constant in a register. 828 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 829 if (MaterialReg == 0) { 830 // If the target doesn't have a way to directly enter a floating-point 831 // value into a register, use an alternate approach. 832 // TODO: The current approach only supports floating-point constants 833 // that can be constructed by conversion from integer values. This should 834 // be replaced by code that creates a load from a constant-pool entry, 835 // which will require some target-specific work. 836 const APFloat &Flt = FPImm->getValueAPF(); 837 MVT IntVT = TLI.getPointerTy(); 838 839 uint64_t x[2]; 840 uint32_t IntBitWidth = IntVT.getSizeInBits(); 841 bool isExact; 842 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 843 APFloat::rmTowardZero, &isExact); 844 if (!isExact) 845 return 0; 846 APInt IntVal(IntBitWidth, 2, x); 847 848 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 849 ISD::Constant, IntVal.getZExtValue()); 850 if (IntegerReg == 0) 851 return 0; 852 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 853 ISD::SINT_TO_FP, IntegerReg); 854 if (MaterialReg == 0) 855 return 0; 856 } 857 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 858} 859 860unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 861 return MRI.createVirtualRegister(RC); 862} 863 864unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 865 const TargetRegisterClass* RC) { 866 unsigned ResultReg = createResultReg(RC); 867 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 868 869 BuildMI(MBB, DL, II, ResultReg); 870 return ResultReg; 871} 872 873unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 874 const TargetRegisterClass *RC, 875 unsigned Op0) { 876 unsigned ResultReg = createResultReg(RC); 877 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 878 879 if (II.getNumDefs() >= 1) 880 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 881 else { 882 BuildMI(MBB, DL, II).addReg(Op0); 883 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 884 II.ImplicitDefs[0], RC, RC); 885 if (!InsertedCopy) 886 ResultReg = 0; 887 } 888 889 return ResultReg; 890} 891 892unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 893 const TargetRegisterClass *RC, 894 unsigned Op0, unsigned Op1) { 895 unsigned ResultReg = createResultReg(RC); 896 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 897 898 if (II.getNumDefs() >= 1) 899 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 900 else { 901 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 902 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 903 II.ImplicitDefs[0], RC, RC); 904 if (!InsertedCopy) 905 ResultReg = 0; 906 } 907 return ResultReg; 908} 909 910unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 911 const TargetRegisterClass *RC, 912 unsigned Op0, uint64_t Imm) { 913 unsigned ResultReg = createResultReg(RC); 914 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 915 916 if (II.getNumDefs() >= 1) 917 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 918 else { 919 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 920 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 921 II.ImplicitDefs[0], RC, RC); 922 if (!InsertedCopy) 923 ResultReg = 0; 924 } 925 return ResultReg; 926} 927 928unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 929 const TargetRegisterClass *RC, 930 unsigned Op0, ConstantFP *FPImm) { 931 unsigned ResultReg = createResultReg(RC); 932 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 933 934 if (II.getNumDefs() >= 1) 935 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 936 else { 937 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 938 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 939 II.ImplicitDefs[0], RC, RC); 940 if (!InsertedCopy) 941 ResultReg = 0; 942 } 943 return ResultReg; 944} 945 946unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 947 const TargetRegisterClass *RC, 948 unsigned Op0, unsigned Op1, uint64_t Imm) { 949 unsigned ResultReg = createResultReg(RC); 950 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 951 952 if (II.getNumDefs() >= 1) 953 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 954 else { 955 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 956 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 957 II.ImplicitDefs[0], RC, RC); 958 if (!InsertedCopy) 959 ResultReg = 0; 960 } 961 return ResultReg; 962} 963 964unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 965 const TargetRegisterClass *RC, 966 uint64_t Imm) { 967 unsigned ResultReg = createResultReg(RC); 968 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 969 970 if (II.getNumDefs() >= 1) 971 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 972 else { 973 BuildMI(MBB, DL, II).addImm(Imm); 974 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 975 II.ImplicitDefs[0], RC, RC); 976 if (!InsertedCopy) 977 ResultReg = 0; 978 } 979 return ResultReg; 980} 981 982unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 983 unsigned Op0, uint32_t Idx) { 984 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 985 986 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 987 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 988 989 if (II.getNumDefs() >= 1) 990 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 991 else { 992 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 993 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 994 II.ImplicitDefs[0], RC, RC); 995 if (!InsertedCopy) 996 ResultReg = 0; 997 } 998 return ResultReg; 999} 1000 1001/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1002/// with all but the least significant bit set to zero. 1003unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 1004 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1005} 1006