FastISel.cpp revision 2565734a60b19b69d83ca44e4a07d14e9ecb59b7
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DebugLoc.h" 51#include "llvm/CodeGen/DwarfWriter.h" 52#include "llvm/Analysis/DebugInfo.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "SelectionDAGBuild.h" 58using namespace llvm; 59 60unsigned FastISel::getRegForValue(Value *V) { 61 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 62 // Don't handle non-simple values in FastISel. 63 if (!RealVT.isSimple()) 64 return 0; 65 66 // Ignore illegal types. We must do this before looking up the value 67 // in ValueMap because Arguments are given virtual registers regardless 68 // of whether FastISel can handle them. 69 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 70 if (!TLI.isTypeLegal(VT)) { 71 // Promote MVT::i1 to a legal type though, because it's common and easy. 72 if (VT == MVT::i1) 73 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 74 else 75 return 0; 76 } 77 78 // Look up the value to see if we already have a register for it. We 79 // cache values defined by Instructions across blocks, and other values 80 // only locally. This is because Instructions already have the SSA 81 // def-dominatess-use requirement enforced. 82 if (ValueMap.count(V)) 83 return ValueMap[V]; 84 unsigned Reg = LocalValueMap[V]; 85 if (Reg != 0) 86 return Reg; 87 88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 89 if (CI->getValue().getActiveBits() <= 64) 90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 91 } else if (isa<AllocaInst>(V)) { 92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 93 } else if (isa<ConstantPointerNull>(V)) { 94 // Translate this as an integer zero so that it can be 95 // local-CSE'd with actual integer zeros. 96 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 99 100 if (!Reg) { 101 const APFloat &Flt = CF->getValueAPF(); 102 MVT IntVT = TLI.getPointerTy(); 103 104 uint64_t x[2]; 105 uint32_t IntBitWidth = IntVT.getSizeInBits(); 106 bool isExact; 107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 108 APFloat::rmTowardZero, &isExact); 109 if (isExact) { 110 APInt IntVal(IntBitWidth, 2, x); 111 112 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 113 if (IntegerReg != 0) 114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 115 } 116 } 117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 118 if (!SelectOperator(CE, CE->getOpcode())) return 0; 119 Reg = LocalValueMap[CE]; 120 } else if (isa<UndefValue>(V)) { 121 Reg = createResultReg(TLI.getRegClassFor(VT)); 122 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 123 } 124 125 // If target-independent code couldn't handle the value, give target-specific 126 // code a try. 127 if (!Reg && isa<Constant>(V)) 128 Reg = TargetMaterializeConstant(cast<Constant>(V)); 129 130 // Don't cache constant materializations in the general ValueMap. 131 // To do so would require tracking what uses they dominate. 132 if (Reg != 0) 133 LocalValueMap[V] = Reg; 134 return Reg; 135} 136 137unsigned FastISel::lookUpRegForValue(Value *V) { 138 // Look up the value to see if we already have a register for it. We 139 // cache values defined by Instructions across blocks, and other values 140 // only locally. This is because Instructions already have the SSA 141 // def-dominatess-use requirement enforced. 142 if (ValueMap.count(V)) 143 return ValueMap[V]; 144 return LocalValueMap[V]; 145} 146 147/// UpdateValueMap - Update the value map to include the new mapping for this 148/// instruction, or insert an extra copy to get the result in a previous 149/// determined register. 150/// NOTE: This is only necessary because we might select a block that uses 151/// a value before we select the block that defines the value. It might be 152/// possible to fix this by selecting blocks in reverse postorder. 153unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 154 if (!isa<Instruction>(I)) { 155 LocalValueMap[I] = Reg; 156 return Reg; 157 } 158 159 unsigned &AssignedReg = ValueMap[I]; 160 if (AssignedReg == 0) 161 AssignedReg = Reg; 162 else if (Reg != AssignedReg) { 163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 165 Reg, RegClass, RegClass); 166 } 167 return AssignedReg; 168} 169 170unsigned FastISel::getRegForGEPIndex(Value *Idx) { 171 unsigned IdxN = getRegForValue(Idx); 172 if (IdxN == 0) 173 // Unhandled operand. Halt "fast" selection and bail. 174 return 0; 175 176 // If the index is smaller or larger than intptr_t, truncate or extend it. 177 MVT PtrVT = TLI.getPointerTy(); 178 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 179 if (IdxVT.bitsLT(PtrVT)) 180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 181 ISD::SIGN_EXTEND, IdxN); 182 else if (IdxVT.bitsGT(PtrVT)) 183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 184 ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 192 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypePaddedSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 unsigned IID = F->getIntrinsicID(); 326 switch (IID) { 327 default: break; 328 case Intrinsic::dbg_stoppoint: { 329 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 330 if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) { 331 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 332 unsigned Line = SPI->getLine(); 333 unsigned Col = SPI->getColumn(); 334 unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col); 335 setCurDebugLoc(DebugLoc::get(Idx)); 336 if (DW && DW->ShouldEmitDwarfDebug()) { 337 unsigned ID = DW->RecordSourceLine(Line, Col, CU); 338 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 339 BuildMI(MBB, DL, II).addImm(ID); 340 } 341 } 342 return true; 343 } 344 case Intrinsic::dbg_region_start: { 345 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 346 if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) && 347 DW && DW->ShouldEmitDwarfDebug()) { 348 unsigned ID = 349 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 350 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 351 BuildMI(MBB, DL, II).addImm(ID); 352 } 353 return true; 354 } 355 case Intrinsic::dbg_region_end: { 356 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 357 if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) && 358 DW && DW->ShouldEmitDwarfDebug()) { 359 unsigned ID = 0; 360 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); 361 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { 362 // This is end of an inlined function. 363 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 364 ID = DW->RecordInlinedFnEnd(Subprogram); 365 if (ID) 366 // Returned ID is 0 if this is unbalanced "end of inlined 367 // scope". This could happen if optimizer eats dbg intrinsics 368 // or "beginning of inlined scope" is not recoginized due to 369 // missing location info. In such cases, do ignore this region.end. 370 BuildMI(MBB, DL, II).addImm(ID); 371 } else { 372 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 373 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 374 BuildMI(MBB, DL, II).addImm(ID); 375 } 376 } 377 return true; 378 } 379 case Intrinsic::dbg_func_start: { 380 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 381 Value *SP = FSI->getSubprogram(); 382 if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None)) 383 return true; 384 385 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 386 // (most?) gdb expects. 387 DebugLoc PrevLoc = DL; 388 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 389 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 390 391 if (!Subprogram.describes(MF.getFunction())) { 392 // This is a beginning of an inlined function. 393 394 // If llvm.dbg.func.start is seen in a new block before any 395 // llvm.dbg.stoppoint intrinsic then the location info is unknown. 396 // FIXME : Why DebugLoc is reset at the beginning of each block ? 397 if (PrevLoc.isUnknown()) 398 return true; 399 // Record the source line. 400 unsigned Line = Subprogram.getLineNumber(); 401 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID( 402 CompileUnit.getGV(), Line, 0))); 403 404 if (DW && DW->ShouldEmitDwarfDebug()) { 405 unsigned LabelID = DW->RecordSourceLine(Line, 0, CompileUnit); 406 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 407 BuildMI(MBB, DL, II).addImm(LabelID); 408 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc); 409 DW->RecordInlinedFnStart(FSI, Subprogram, LabelID, 410 DICompileUnit(PrevLocTpl.CompileUnit), 411 PrevLocTpl.Line, 412 PrevLocTpl.Col); 413 } 414 } else { 415 // Record the source line. 416 unsigned Line = Subprogram.getLineNumber(); 417 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID( 418 CompileUnit.getGV(), Line, 0))); 419 if (DW && DW->ShouldEmitDwarfDebug()) { 420 DW->RecordSourceLine(Line, 0, CompileUnit); 421 // llvm.dbg.func_start also defines beginning of function scope. 422 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 423 } 424 } 425 426 return true; 427 } 428 case Intrinsic::dbg_declare: { 429 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 430 Value *Variable = DI->getVariable(); 431 if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) && 432 DW && DW->ShouldEmitDwarfDebug()) { 433 // Determine the address of the declared object. 434 Value *Address = DI->getAddress(); 435 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 436 Address = BCI->getOperand(0); 437 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 438 // Don't handle byval struct arguments or VLAs, for example. 439 if (!AI) break; 440 DenseMap<const AllocaInst*, int>::iterator SI = 441 StaticAllocaMap.find(AI); 442 if (SI == StaticAllocaMap.end()) break; // VLAs. 443 int FI = SI->second; 444 445 // Determine the debug globalvariable. 446 GlobalValue *GV = cast<GlobalVariable>(Variable); 447 448 // Build the DECLARE instruction. 449 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 450 MachineInstr *DeclareMI 451 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 452 DIVariable DV(cast<GlobalVariable>(GV)); 453 if (!DV.isNull()) { 454 // This is a local variable 455 DW->RecordVariableScope(DV, DeclareMI); 456 } 457 } 458 return true; 459 } 460 case Intrinsic::eh_exception: { 461 MVT VT = TLI.getValueType(I->getType()); 462 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 463 default: break; 464 case TargetLowering::Expand: { 465 if (!MBB->isLandingPad()) { 466 // FIXME: Mark exception register as live in. Hack for PR1508. 467 unsigned Reg = TLI.getExceptionAddressRegister(); 468 if (Reg) MBB->addLiveIn(Reg); 469 } 470 unsigned Reg = TLI.getExceptionAddressRegister(); 471 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 472 unsigned ResultReg = createResultReg(RC); 473 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 474 Reg, RC, RC); 475 assert(InsertedCopy && "Can't copy address registers!"); 476 InsertedCopy = InsertedCopy; 477 UpdateValueMap(I, ResultReg); 478 return true; 479 } 480 } 481 break; 482 } 483 case Intrinsic::eh_selector_i32: 484 case Intrinsic::eh_selector_i64: { 485 MVT VT = TLI.getValueType(I->getType()); 486 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 487 default: break; 488 case TargetLowering::Expand: { 489 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 490 MVT::i32 : MVT::i64); 491 492 if (MMI) { 493 if (MBB->isLandingPad()) 494 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 495 else { 496#ifndef NDEBUG 497 CatchInfoLost.insert(cast<CallInst>(I)); 498#endif 499 // FIXME: Mark exception selector register as live in. Hack for PR1508. 500 unsigned Reg = TLI.getExceptionSelectorRegister(); 501 if (Reg) MBB->addLiveIn(Reg); 502 } 503 504 unsigned Reg = TLI.getExceptionSelectorRegister(); 505 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 506 unsigned ResultReg = createResultReg(RC); 507 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 508 Reg, RC, RC); 509 assert(InsertedCopy && "Can't copy address registers!"); 510 InsertedCopy = InsertedCopy; 511 UpdateValueMap(I, ResultReg); 512 } else { 513 unsigned ResultReg = 514 getRegForValue(Constant::getNullValue(I->getType())); 515 UpdateValueMap(I, ResultReg); 516 } 517 return true; 518 } 519 } 520 break; 521 } 522 } 523 return false; 524} 525 526bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 527 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 528 MVT DstVT = TLI.getValueType(I->getType()); 529 530 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 531 DstVT == MVT::Other || !DstVT.isSimple()) 532 // Unhandled type. Halt "fast" selection and bail. 533 return false; 534 535 // Check if the destination type is legal. Or as a special case, 536 // it may be i1 if we're doing a truncate because that's 537 // easy and somewhat common. 538 if (!TLI.isTypeLegal(DstVT)) 539 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 540 // Unhandled type. Halt "fast" selection and bail. 541 return false; 542 543 // Check if the source operand is legal. Or as a special case, 544 // it may be i1 if we're doing zero-extension because that's 545 // easy and somewhat common. 546 if (!TLI.isTypeLegal(SrcVT)) 547 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 548 // Unhandled type. Halt "fast" selection and bail. 549 return false; 550 551 unsigned InputReg = getRegForValue(I->getOperand(0)); 552 if (!InputReg) 553 // Unhandled operand. Halt "fast" selection and bail. 554 return false; 555 556 // If the operand is i1, arrange for the high bits in the register to be zero. 557 if (SrcVT == MVT::i1) { 558 SrcVT = TLI.getTypeToTransformTo(SrcVT); 559 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 560 if (!InputReg) 561 return false; 562 } 563 // If the result is i1, truncate to the target's type for i1 first. 564 if (DstVT == MVT::i1) 565 DstVT = TLI.getTypeToTransformTo(DstVT); 566 567 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 568 DstVT.getSimpleVT(), 569 Opcode, 570 InputReg); 571 if (!ResultReg) 572 return false; 573 574 UpdateValueMap(I, ResultReg); 575 return true; 576} 577 578bool FastISel::SelectBitCast(User *I) { 579 // If the bitcast doesn't change the type, just use the operand value. 580 if (I->getType() == I->getOperand(0)->getType()) { 581 unsigned Reg = getRegForValue(I->getOperand(0)); 582 if (Reg == 0) 583 return false; 584 UpdateValueMap(I, Reg); 585 return true; 586 } 587 588 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 589 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 590 MVT DstVT = TLI.getValueType(I->getType()); 591 592 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 593 DstVT == MVT::Other || !DstVT.isSimple() || 594 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 595 // Unhandled type. Halt "fast" selection and bail. 596 return false; 597 598 unsigned Op0 = getRegForValue(I->getOperand(0)); 599 if (Op0 == 0) 600 // Unhandled operand. Halt "fast" selection and bail. 601 return false; 602 603 // First, try to perform the bitcast by inserting a reg-reg copy. 604 unsigned ResultReg = 0; 605 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 606 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 607 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 608 ResultReg = createResultReg(DstClass); 609 610 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 611 Op0, DstClass, SrcClass); 612 if (!InsertedCopy) 613 ResultReg = 0; 614 } 615 616 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 617 if (!ResultReg) 618 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 619 ISD::BIT_CONVERT, Op0); 620 621 if (!ResultReg) 622 return false; 623 624 UpdateValueMap(I, ResultReg); 625 return true; 626} 627 628bool 629FastISel::SelectInstruction(Instruction *I) { 630 return SelectOperator(I, I->getOpcode()); 631} 632 633/// FastEmitBranch - Emit an unconditional branch to the given block, 634/// unless it is the immediate (fall-through) successor, and update 635/// the CFG. 636void 637FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 638 MachineFunction::iterator NextMBB = 639 next(MachineFunction::iterator(MBB)); 640 641 if (MBB->isLayoutSuccessor(MSucc)) { 642 // The unconditional fall-through case, which needs no instructions. 643 } else { 644 // The unconditional branch case. 645 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 646 } 647 MBB->addSuccessor(MSucc); 648} 649 650bool 651FastISel::SelectOperator(User *I, unsigned Opcode) { 652 switch (Opcode) { 653 case Instruction::Add: { 654 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 655 return SelectBinaryOp(I, Opc); 656 } 657 case Instruction::Sub: { 658 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 659 return SelectBinaryOp(I, Opc); 660 } 661 case Instruction::Mul: { 662 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 663 return SelectBinaryOp(I, Opc); 664 } 665 case Instruction::SDiv: 666 return SelectBinaryOp(I, ISD::SDIV); 667 case Instruction::UDiv: 668 return SelectBinaryOp(I, ISD::UDIV); 669 case Instruction::FDiv: 670 return SelectBinaryOp(I, ISD::FDIV); 671 case Instruction::SRem: 672 return SelectBinaryOp(I, ISD::SREM); 673 case Instruction::URem: 674 return SelectBinaryOp(I, ISD::UREM); 675 case Instruction::FRem: 676 return SelectBinaryOp(I, ISD::FREM); 677 case Instruction::Shl: 678 return SelectBinaryOp(I, ISD::SHL); 679 case Instruction::LShr: 680 return SelectBinaryOp(I, ISD::SRL); 681 case Instruction::AShr: 682 return SelectBinaryOp(I, ISD::SRA); 683 case Instruction::And: 684 return SelectBinaryOp(I, ISD::AND); 685 case Instruction::Or: 686 return SelectBinaryOp(I, ISD::OR); 687 case Instruction::Xor: 688 return SelectBinaryOp(I, ISD::XOR); 689 690 case Instruction::GetElementPtr: 691 return SelectGetElementPtr(I); 692 693 case Instruction::Br: { 694 BranchInst *BI = cast<BranchInst>(I); 695 696 if (BI->isUnconditional()) { 697 BasicBlock *LLVMSucc = BI->getSuccessor(0); 698 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 699 FastEmitBranch(MSucc); 700 return true; 701 } 702 703 // Conditional branches are not handed yet. 704 // Halt "fast" selection and bail. 705 return false; 706 } 707 708 case Instruction::Unreachable: 709 // Nothing to emit. 710 return true; 711 712 case Instruction::PHI: 713 // PHI nodes are already emitted. 714 return true; 715 716 case Instruction::Alloca: 717 // FunctionLowering has the static-sized case covered. 718 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 719 return true; 720 721 // Dynamic-sized alloca is not handled yet. 722 return false; 723 724 case Instruction::Call: 725 return SelectCall(I); 726 727 case Instruction::BitCast: 728 return SelectBitCast(I); 729 730 case Instruction::FPToSI: 731 return SelectCast(I, ISD::FP_TO_SINT); 732 case Instruction::ZExt: 733 return SelectCast(I, ISD::ZERO_EXTEND); 734 case Instruction::SExt: 735 return SelectCast(I, ISD::SIGN_EXTEND); 736 case Instruction::Trunc: 737 return SelectCast(I, ISD::TRUNCATE); 738 case Instruction::SIToFP: 739 return SelectCast(I, ISD::SINT_TO_FP); 740 741 case Instruction::IntToPtr: // Deliberate fall-through. 742 case Instruction::PtrToInt: { 743 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 744 MVT DstVT = TLI.getValueType(I->getType()); 745 if (DstVT.bitsGT(SrcVT)) 746 return SelectCast(I, ISD::ZERO_EXTEND); 747 if (DstVT.bitsLT(SrcVT)) 748 return SelectCast(I, ISD::TRUNCATE); 749 unsigned Reg = getRegForValue(I->getOperand(0)); 750 if (Reg == 0) return false; 751 UpdateValueMap(I, Reg); 752 return true; 753 } 754 755 default: 756 // Unhandled instruction. Halt "fast" selection and bail. 757 return false; 758 } 759} 760 761FastISel::FastISel(MachineFunction &mf, 762 MachineModuleInfo *mmi, 763 DwarfWriter *dw, 764 DenseMap<const Value *, unsigned> &vm, 765 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 766 DenseMap<const AllocaInst *, int> &am 767#ifndef NDEBUG 768 , SmallSet<Instruction*, 8> &cil 769#endif 770 ) 771 : MBB(0), 772 ValueMap(vm), 773 MBBMap(bm), 774 StaticAllocaMap(am), 775#ifndef NDEBUG 776 CatchInfoLost(cil), 777#endif 778 MF(mf), 779 MMI(mmi), 780 DW(dw), 781 MRI(MF.getRegInfo()), 782 MFI(*MF.getFrameInfo()), 783 MCP(*MF.getConstantPool()), 784 TM(MF.getTarget()), 785 TD(*TM.getTargetData()), 786 TII(*TM.getInstrInfo()), 787 TLI(*TM.getTargetLowering()) { 788} 789 790FastISel::~FastISel() {} 791 792unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 793 ISD::NodeType) { 794 return 0; 795} 796 797unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 798 ISD::NodeType, unsigned /*Op0*/) { 799 return 0; 800} 801 802unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 803 ISD::NodeType, unsigned /*Op0*/, 804 unsigned /*Op0*/) { 805 return 0; 806} 807 808unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 809 ISD::NodeType, uint64_t /*Imm*/) { 810 return 0; 811} 812 813unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 814 ISD::NodeType, ConstantFP * /*FPImm*/) { 815 return 0; 816} 817 818unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 819 ISD::NodeType, unsigned /*Op0*/, 820 uint64_t /*Imm*/) { 821 return 0; 822} 823 824unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 825 ISD::NodeType, unsigned /*Op0*/, 826 ConstantFP * /*FPImm*/) { 827 return 0; 828} 829 830unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 831 ISD::NodeType, 832 unsigned /*Op0*/, unsigned /*Op1*/, 833 uint64_t /*Imm*/) { 834 return 0; 835} 836 837/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 838/// to emit an instruction with an immediate operand using FastEmit_ri. 839/// If that fails, it materializes the immediate into a register and try 840/// FastEmit_rr instead. 841unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 842 unsigned Op0, uint64_t Imm, 843 MVT::SimpleValueType ImmType) { 844 // First check if immediate type is legal. If not, we can't use the ri form. 845 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 846 if (ResultReg != 0) 847 return ResultReg; 848 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 849 if (MaterialReg == 0) 850 return 0; 851 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 852} 853 854/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 855/// to emit an instruction with a floating-point immediate operand using 856/// FastEmit_rf. If that fails, it materializes the immediate into a register 857/// and try FastEmit_rr instead. 858unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 859 unsigned Op0, ConstantFP *FPImm, 860 MVT::SimpleValueType ImmType) { 861 // First check if immediate type is legal. If not, we can't use the rf form. 862 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 863 if (ResultReg != 0) 864 return ResultReg; 865 866 // Materialize the constant in a register. 867 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 868 if (MaterialReg == 0) { 869 // If the target doesn't have a way to directly enter a floating-point 870 // value into a register, use an alternate approach. 871 // TODO: The current approach only supports floating-point constants 872 // that can be constructed by conversion from integer values. This should 873 // be replaced by code that creates a load from a constant-pool entry, 874 // which will require some target-specific work. 875 const APFloat &Flt = FPImm->getValueAPF(); 876 MVT IntVT = TLI.getPointerTy(); 877 878 uint64_t x[2]; 879 uint32_t IntBitWidth = IntVT.getSizeInBits(); 880 bool isExact; 881 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 882 APFloat::rmTowardZero, &isExact); 883 if (!isExact) 884 return 0; 885 APInt IntVal(IntBitWidth, 2, x); 886 887 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 888 ISD::Constant, IntVal.getZExtValue()); 889 if (IntegerReg == 0) 890 return 0; 891 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 892 ISD::SINT_TO_FP, IntegerReg); 893 if (MaterialReg == 0) 894 return 0; 895 } 896 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 897} 898 899unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 900 return MRI.createVirtualRegister(RC); 901} 902 903unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 904 const TargetRegisterClass* RC) { 905 unsigned ResultReg = createResultReg(RC); 906 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 907 908 BuildMI(MBB, DL, II, ResultReg); 909 return ResultReg; 910} 911 912unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 913 const TargetRegisterClass *RC, 914 unsigned Op0) { 915 unsigned ResultReg = createResultReg(RC); 916 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 917 918 if (II.getNumDefs() >= 1) 919 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 920 else { 921 BuildMI(MBB, DL, II).addReg(Op0); 922 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 923 II.ImplicitDefs[0], RC, RC); 924 if (!InsertedCopy) 925 ResultReg = 0; 926 } 927 928 return ResultReg; 929} 930 931unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 932 const TargetRegisterClass *RC, 933 unsigned Op0, unsigned Op1) { 934 unsigned ResultReg = createResultReg(RC); 935 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 936 937 if (II.getNumDefs() >= 1) 938 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 939 else { 940 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 941 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 942 II.ImplicitDefs[0], RC, RC); 943 if (!InsertedCopy) 944 ResultReg = 0; 945 } 946 return ResultReg; 947} 948 949unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 950 const TargetRegisterClass *RC, 951 unsigned Op0, uint64_t Imm) { 952 unsigned ResultReg = createResultReg(RC); 953 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 954 955 if (II.getNumDefs() >= 1) 956 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 957 else { 958 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 959 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 960 II.ImplicitDefs[0], RC, RC); 961 if (!InsertedCopy) 962 ResultReg = 0; 963 } 964 return ResultReg; 965} 966 967unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 968 const TargetRegisterClass *RC, 969 unsigned Op0, ConstantFP *FPImm) { 970 unsigned ResultReg = createResultReg(RC); 971 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 972 973 if (II.getNumDefs() >= 1) 974 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 975 else { 976 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 977 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 978 II.ImplicitDefs[0], RC, RC); 979 if (!InsertedCopy) 980 ResultReg = 0; 981 } 982 return ResultReg; 983} 984 985unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 986 const TargetRegisterClass *RC, 987 unsigned Op0, unsigned Op1, uint64_t Imm) { 988 unsigned ResultReg = createResultReg(RC); 989 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 990 991 if (II.getNumDefs() >= 1) 992 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 993 else { 994 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 995 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 996 II.ImplicitDefs[0], RC, RC); 997 if (!InsertedCopy) 998 ResultReg = 0; 999 } 1000 return ResultReg; 1001} 1002 1003unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1004 const TargetRegisterClass *RC, 1005 uint64_t Imm) { 1006 unsigned ResultReg = createResultReg(RC); 1007 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1008 1009 if (II.getNumDefs() >= 1) 1010 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 1011 else { 1012 BuildMI(MBB, DL, II).addImm(Imm); 1013 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1014 II.ImplicitDefs[0], RC, RC); 1015 if (!InsertedCopy) 1016 ResultReg = 0; 1017 } 1018 return ResultReg; 1019} 1020 1021unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 1022 unsigned Op0, uint32_t Idx) { 1023 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 1024 1025 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1026 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 1027 1028 if (II.getNumDefs() >= 1) 1029 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 1030 else { 1031 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1032 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1033 II.ImplicitDefs[0], RC, RC); 1034 if (!InsertedCopy) 1035 ResultReg = 0; 1036 } 1037 return ResultReg; 1038} 1039 1040/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1041/// with all but the least significant bit set to zero. 1042unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 1043 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1044} 1045