FastISel.cpp revision 3087240477f138ba016975e1205b375e79393122
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Instructions.h" 15#include "llvm/CodeGen/FastISel.h" 16#include "llvm/CodeGen/MachineInstrBuilder.h" 17#include "llvm/CodeGen/MachineRegisterInfo.h" 18#include "llvm/Target/TargetData.h" 19#include "llvm/Target/TargetInstrInfo.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetMachine.h" 22using namespace llvm; 23 24/// SelectBinaryOp - Select and emit code for a binary operator instruction, 25/// which has an opcode which directly corresponds to the given ISD opcode. 26/// 27bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode, 28 DenseMap<const Value*, unsigned> &ValueMap) { 29 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 30 if (VT == MVT::Other || !VT.isSimple()) 31 // Unhandled type. Halt "fast" selection and bail. 32 return false; 33 // We only handle legal types. For example, on x86-32 the instruction 34 // selector contains all of the 64-bit instructions from x86-64, 35 // under the assumption that i64 won't be used if the target doesn't 36 // support it. 37 if (!TLI.isTypeLegal(VT)) 38 return false; 39 40 unsigned Op0 = ValueMap[I->getOperand(0)]; 41 if (Op0 == 0) 42 // Unhandled operand. Halt "fast" selection and bail. 43 return false; 44 45 // Check if the second operand is a constant and handle it appropriately. 46 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 47 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 48 CI->getZExtValue(), VT.getSimpleVT()); 49 if (ResultReg == 0) 50 // Target-specific code wasn't able to find a machine opcode for 51 // the given ISD opcode and type. Halt "fast" selection and bail. 52 return false; 53 54 // We successfully emitted code for the given LLVM Instruction. 55 ValueMap[I] = ResultReg; 56 return true; 57 } 58 59 // Check if the second operand is a constant float. 60 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 61 unsigned ResultReg = FastEmit_rf_(VT.getSimpleVT(), ISDOpcode, Op0, 62 CF, VT.getSimpleVT()); 63 if (ResultReg == 0) 64 // Target-specific code wasn't able to find a machine opcode for 65 // the given ISD opcode and type. Halt "fast" selection and bail. 66 return false; 67 68 // We successfully emitted code for the given LLVM Instruction. 69 ValueMap[I] = ResultReg; 70 return true; 71 } 72 73 unsigned Op1 = ValueMap[I->getOperand(1)]; 74 if (Op1 == 0) 75 // Unhandled operand. Halt "fast" selection and bail. 76 return false; 77 78 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 79 ISDOpcode, Op0, Op1); 80 if (ResultReg == 0) 81 // Target-specific code wasn't able to find a machine opcode for 82 // the given ISD opcode and type. Halt "fast" selection and bail. 83 return false; 84 85 // We successfully emitted code for the given LLVM Instruction. 86 ValueMap[I] = ResultReg; 87 return true; 88} 89 90bool FastISel::SelectGetElementPtr(Instruction *I, 91 DenseMap<const Value*, unsigned> &ValueMap) { 92 unsigned N = ValueMap[I->getOperand(0)]; 93 if (N == 0) 94 // Unhandled operand. Halt "fast" selection and bail. 95 return false; 96 97 const Type *Ty = I->getOperand(0)->getType(); 98 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 99 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 100 OI != E; ++OI) { 101 Value *Idx = *OI; 102 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 103 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 104 if (Field) { 105 // N = N + Offset 106 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 107 // FIXME: This can be optimized by combining the add with a 108 // subsequent one. 109 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 110 if (N == 0) 111 // Unhandled operand. Halt "fast" selection and bail. 112 return false; 113 } 114 Ty = StTy->getElementType(Field); 115 } else { 116 Ty = cast<SequentialType>(Ty)->getElementType(); 117 118 // If this is a constant subscript, handle it quickly. 119 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 120 if (CI->getZExtValue() == 0) continue; 121 uint64_t Offs = 122 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 123 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 124 if (N == 0) 125 // Unhandled operand. Halt "fast" selection and bail. 126 return false; 127 continue; 128 } 129 130 // N = N + Idx * ElementSize; 131 uint64_t ElementSize = TD.getABITypeSize(Ty); 132 unsigned IdxN = ValueMap[Idx]; 133 if (IdxN == 0) 134 // Unhandled operand. Halt "fast" selection and bail. 135 return false; 136 137 // If the index is smaller or larger than intptr_t, truncate or extend 138 // it. 139 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 140 if (IdxVT.bitsLT(VT)) 141 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN); 142 else if (IdxVT.bitsGT(VT)) 143 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN); 144 if (IdxN == 0) 145 // Unhandled operand. Halt "fast" selection and bail. 146 return false; 147 148 if (ElementSize != 1) { 149 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 150 if (IdxN == 0) 151 // Unhandled operand. Halt "fast" selection and bail. 152 return false; 153 } 154 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 155 if (N == 0) 156 // Unhandled operand. Halt "fast" selection and bail. 157 return false; 158 } 159 } 160 161 // We successfully emitted code for the given LLVM Instruction. 162 ValueMap[I] = N; 163 return true; 164} 165 166bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode, 167 DenseMap<const Value*, unsigned> &ValueMap) { 168 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType()); 169 MVT DstVT = MVT::getMVT(I->getType()); 170 171 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 172 DstVT == MVT::Other || !DstVT.isSimple() || 173 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 174 // Unhandled type. Halt "fast" selection and bail. 175 return false; 176 177 unsigned InputReg = ValueMap[I->getOperand(0)]; 178 if (!InputReg) 179 // Unhandled operand. Halt "fast" selection and bail. 180 return false; 181 182 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 183 DstVT.getSimpleVT(), 184 Opcode, 185 InputReg); 186 if (!ResultReg) 187 return false; 188 189 ValueMap[I] = ResultReg; 190 return true; 191} 192 193bool FastISel::SelectConstantCast(Instruction* I, ISD::NodeType Opcode, 194 DenseMap<const Value*, unsigned> &ValueMap) { 195 // Materialize constant and convert. 196 ConstantInt* CI = cast<ConstantInt>(I->getOperand(0)); 197 MVT SrcVT = MVT::getMVT(CI->getType()); 198 MVT DstVT = MVT::getMVT(I->getType()); 199 200 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 201 DstVT == MVT::Other || !DstVT.isSimple() || 202 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 203 // Unhandled type. Halt "fast" selection and bail. 204 return false; 205 206 unsigned ResultReg1 = FastEmit_i(SrcVT.getSimpleVT(), 207 SrcVT.getSimpleVT(), 208 ISD::Constant, CI->getZExtValue()); 209 if (!ResultReg1) 210 return false; 211 212 unsigned ResultReg2 = FastEmit_r(SrcVT.getSimpleVT(), 213 DstVT.getSimpleVT(), 214 Opcode, 215 ResultReg1); 216 if (!ResultReg2) 217 return false; 218 219 ValueMap[I] = ResultReg2; 220 return true; 221} 222 223bool FastISel::SelectConstantFPCast(Instruction* I, ISD::NodeType Opcode, 224 DenseMap<const Value*, unsigned> &ValueMap) { 225 // TODO: Implement casting of FP constants by materialization 226 // followed by conversion. 227 return false; 228} 229 230bool FastISel::SelectBitCast(Instruction *I, 231 DenseMap<const Value*, unsigned> &ValueMap) { 232 // BitCast consists of either an immediate to register move 233 // or a register to register move. 234 if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) { 235 if (I->getType()->isInteger()) { 236 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false); 237 unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(), 238 ISD::Constant, 239 CI->getZExtValue()); 240 if (!result) 241 return false; 242 243 ValueMap[I] = result; 244 return true; 245 } 246 247 // TODO: Support vector and fp constants. 248 return false; 249 } 250 251 if (!isa<Constant>(I->getOperand(0))) { 252 // Bitcasts of non-constant values become reg-reg copies. 253 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType()); 254 MVT DstVT = MVT::getMVT(I->getType()); 255 256 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 257 DstVT == MVT::Other || !DstVT.isSimple() || 258 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 259 // Unhandled type. Halt "fast" selection and bail. 260 return false; 261 262 unsigned Op0 = ValueMap[I->getOperand(0)]; 263 if (Op0 == 0) 264 // Unhandled operand. Halt "fast" selection and bail. 265 return false; 266 267 // First, try to perform the bitcast by inserting a reg-reg copy. 268 unsigned ResultReg = 0; 269 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 270 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 271 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 272 ResultReg = createResultReg(DstClass); 273 274 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 275 Op0, DstClass, SrcClass); 276 if (!InsertedCopy) 277 ResultReg = 0; 278 } 279 280 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 281 if (!ResultReg) 282 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 283 ISD::BIT_CONVERT, Op0); 284 285 if (!ResultReg) 286 return false; 287 288 ValueMap[I] = ResultReg; 289 return true; 290 } 291 292 // TODO: Casting a non-integral constant? 293 return false; 294} 295 296BasicBlock::iterator 297FastISel::SelectInstructions(BasicBlock::iterator Begin, 298 BasicBlock::iterator End, 299 DenseMap<const Value*, unsigned> &ValueMap, 300 DenseMap<const BasicBlock*, 301 MachineBasicBlock *> &MBBMap, 302 MachineBasicBlock *mbb) { 303 MBB = mbb; 304 BasicBlock::iterator I = Begin; 305 306 for (; I != End; ++I) { 307 switch (I->getOpcode()) { 308 case Instruction::Add: { 309 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 310 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break; 311 } 312 case Instruction::Sub: { 313 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 314 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break; 315 } 316 case Instruction::Mul: { 317 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 318 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break; 319 } 320 case Instruction::SDiv: 321 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break; 322 case Instruction::UDiv: 323 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break; 324 case Instruction::FDiv: 325 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break; 326 case Instruction::SRem: 327 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break; 328 case Instruction::URem: 329 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break; 330 case Instruction::FRem: 331 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break; 332 case Instruction::Shl: 333 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break; 334 case Instruction::LShr: 335 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break; 336 case Instruction::AShr: 337 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break; 338 case Instruction::And: 339 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break; 340 case Instruction::Or: 341 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break; 342 case Instruction::Xor: 343 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break; 344 345 case Instruction::GetElementPtr: 346 if (!SelectGetElementPtr(I, ValueMap)) return I; 347 break; 348 349 case Instruction::Br: { 350 BranchInst *BI = cast<BranchInst>(I); 351 352 if (BI->isUnconditional()) { 353 MachineFunction::iterator NextMBB = 354 next(MachineFunction::iterator(MBB)); 355 BasicBlock *LLVMSucc = BI->getSuccessor(0); 356 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 357 358 if (NextMBB != MF.end() && MSucc == NextMBB) { 359 // The unconditional fall-through case, which needs no instructions. 360 } else { 361 // The unconditional branch case. 362 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 363 } 364 MBB->addSuccessor(MSucc); 365 break; 366 } 367 368 // Conditional branches are not handed yet. 369 // Halt "fast" selection and bail. 370 return I; 371 } 372 373 case Instruction::PHI: 374 // PHI nodes are already emitted. 375 break; 376 377 case Instruction::BitCast: 378 if (!SelectBitCast(I, ValueMap)) return I; break; 379 380 case Instruction::FPToSI: 381 if (!isa<ConstantFP>(I->getOperand(0))) { 382 if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I; 383 } else 384 if (!SelectConstantFPCast(I, ISD::FP_TO_SINT, ValueMap)) return I; 385 break; 386 case Instruction::ZExt: 387 if (!isa<ConstantInt>(I->getOperand(0))) { 388 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I; 389 } else 390 if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I; 391 break; 392 case Instruction::SExt: 393 if (!isa<ConstantInt>(I->getOperand(0))) { 394 if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I; 395 } else 396 if (!SelectConstantCast(I, ISD::SIGN_EXTEND, ValueMap)) return I; 397 break; 398 case Instruction::SIToFP: 399 if (!isa<ConstantInt>(I->getOperand(0))) { 400 if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I; 401 } else 402 if (!SelectConstantCast(I, ISD::SINT_TO_FP, ValueMap)) return I; 403 break; 404 405 case Instruction::IntToPtr: // Deliberate fall-through. 406 case Instruction::PtrToInt: { 407 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 408 MVT DstVT = TLI.getValueType(I->getType()); 409 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 410 if (ValueMap[I->getOperand(0)]) { 411 ValueMap[I] = ValueMap[I->getOperand(0)]; 412 break; 413 } else 414 // Unhandled operand 415 return I; 416 } else if (DstVT.bitsGT(SrcVT)) { 417 if (!isa<ConstantInt>(I->getOperand(0))) { 418 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I; 419 } else 420 if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I; 421 break; 422 } else { 423 // TODO: Handle SrcVT > DstVT, where truncation is needed. 424 return I; 425 } 426 } 427 428 default: 429 // Unhandled instruction. Halt "fast" selection and bail. 430 return I; 431 } 432 } 433 434 return I; 435} 436 437FastISel::FastISel(MachineFunction &mf) 438 : MF(mf), 439 MRI(mf.getRegInfo()), 440 TM(mf.getTarget()), 441 TD(*TM.getTargetData()), 442 TII(*TM.getInstrInfo()), 443 TLI(*TM.getTargetLowering()) { 444} 445 446FastISel::~FastISel() {} 447 448unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) { 449 return 0; 450} 451 452unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 453 ISD::NodeType, unsigned /*Op0*/) { 454 return 0; 455} 456 457unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 458 ISD::NodeType, unsigned /*Op0*/, 459 unsigned /*Op0*/) { 460 return 0; 461} 462 463unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 464 ISD::NodeType, uint64_t /*Imm*/) { 465 return 0; 466} 467 468unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 469 ISD::NodeType, ConstantFP * /*FPImm*/) { 470 return 0; 471} 472 473unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 474 ISD::NodeType, unsigned /*Op0*/, 475 uint64_t /*Imm*/) { 476 return 0; 477} 478 479unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 480 ISD::NodeType, unsigned /*Op0*/, 481 ConstantFP * /*FPImm*/) { 482 return 0; 483} 484 485unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 486 ISD::NodeType, 487 unsigned /*Op0*/, unsigned /*Op1*/, 488 uint64_t /*Imm*/) { 489 return 0; 490} 491 492/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 493/// to emit an instruction with an immediate operand using FastEmit_ri. 494/// If that fails, it materializes the immediate into a register and try 495/// FastEmit_rr instead. 496unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 497 unsigned Op0, uint64_t Imm, 498 MVT::SimpleValueType ImmType) { 499 unsigned ResultReg = 0; 500 // First check if immediate type is legal. If not, we can't use the ri form. 501 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal) 502 ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 503 if (ResultReg != 0) 504 return ResultReg; 505 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 506 if (MaterialReg == 0) 507 return 0; 508 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 509} 510 511/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 512/// to emit an instruction with a floating-point immediate operand using 513/// FastEmit_rf. If that fails, it materializes the immediate into a register 514/// and try FastEmit_rr instead. 515unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 516 unsigned Op0, ConstantFP *FPImm, 517 MVT::SimpleValueType ImmType) { 518 unsigned ResultReg = 0; 519 // First check if immediate type is legal. If not, we can't use the rf form. 520 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal) 521 ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 522 if (ResultReg != 0) 523 return ResultReg; 524 525 // Materialize the constant in a register. 526 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 527 if (MaterialReg == 0) { 528 // If the target doesn't have a way to directly enter a floating-point 529 // value into a register, use an alternate approach. 530 // TODO: The current approach only supports floating-point constants 531 // that can be constructed by conversion from integer values. This should 532 // be replaced by code that creates a load from a constant-pool entry, 533 // which will require some target-specific work. 534 const APFloat &Flt = FPImm->getValueAPF(); 535 MVT IntVT = TLI.getPointerTy(); 536 537 uint64_t x[2]; 538 uint32_t IntBitWidth = IntVT.getSizeInBits(); 539 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 540 APFloat::rmTowardZero) != APFloat::opOK) 541 return 0; 542 APInt IntVal(IntBitWidth, 2, x); 543 544 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 545 ISD::Constant, IntVal.getZExtValue()); 546 if (IntegerReg == 0) 547 return 0; 548 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 549 ISD::SINT_TO_FP, IntegerReg); 550 if (MaterialReg == 0) 551 return 0; 552 } 553 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 554} 555 556unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 557 return MRI.createVirtualRegister(RC); 558} 559 560unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 561 const TargetRegisterClass* RC) { 562 unsigned ResultReg = createResultReg(RC); 563 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 564 565 BuildMI(MBB, II, ResultReg); 566 return ResultReg; 567} 568 569unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 570 const TargetRegisterClass *RC, 571 unsigned Op0) { 572 unsigned ResultReg = createResultReg(RC); 573 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 574 575 BuildMI(MBB, II, ResultReg).addReg(Op0); 576 return ResultReg; 577} 578 579unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 580 const TargetRegisterClass *RC, 581 unsigned Op0, unsigned Op1) { 582 unsigned ResultReg = createResultReg(RC); 583 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 584 585 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1); 586 return ResultReg; 587} 588 589unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 590 const TargetRegisterClass *RC, 591 unsigned Op0, uint64_t Imm) { 592 unsigned ResultReg = createResultReg(RC); 593 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 594 595 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm); 596 return ResultReg; 597} 598 599unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 600 const TargetRegisterClass *RC, 601 unsigned Op0, ConstantFP *FPImm) { 602 unsigned ResultReg = createResultReg(RC); 603 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 604 605 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm); 606 return ResultReg; 607} 608 609unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 610 const TargetRegisterClass *RC, 611 unsigned Op0, unsigned Op1, uint64_t Imm) { 612 unsigned ResultReg = createResultReg(RC); 613 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 614 615 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 616 return ResultReg; 617} 618 619unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 620 const TargetRegisterClass *RC, 621 uint64_t Imm) { 622 unsigned ResultReg = createResultReg(RC); 623 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 624 625 BuildMI(MBB, II, ResultReg).addImm(Imm); 626 return ResultReg; 627} 628