FastISel.cpp revision 39bd365ee957d1ebb886dc77c4a251610bf3b83d
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuild.h" 57using namespace llvm; 58 59unsigned FastISel::getRegForValue(Value *V) { 60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 61 // Don't handle non-simple values in FastISel. 62 if (!RealVT.isSimple()) 63 return 0; 64 65 // Ignore illegal types. We must do this before looking up the value 66 // in ValueMap because Arguments are given virtual registers regardless 67 // of whether FastISel can handle them. 68 MVT::SimpleValueType VT = RealVT.getSimpleVT(); 69 if (!TLI.isTypeLegal(VT)) { 70 // Promote MVT::i1 to a legal type though, because it's common and easy. 71 if (VT == MVT::i1) 72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 73 else 74 return 0; 75 } 76 77 // Look up the value to see if we already have a register for it. We 78 // cache values defined by Instructions across blocks, and other values 79 // only locally. This is because Instructions already have the SSA 80 // def-dominatess-use requirement enforced. 81 if (ValueMap.count(V)) 82 return ValueMap[V]; 83 unsigned Reg = LocalValueMap[V]; 84 if (Reg != 0) 85 return Reg; 86 87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 88 if (CI->getValue().getActiveBits() <= 64) 89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 90 } else if (isa<AllocaInst>(V)) { 91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 92 } else if (isa<ConstantPointerNull>(V)) { 93 // Translate this as an integer zero so that it can be 94 // local-CSE'd with actual integer zeros. 95 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 98 99 if (!Reg) { 100 const APFloat &Flt = CF->getValueAPF(); 101 MVT IntVT = TLI.getPointerTy(); 102 103 uint64_t x[2]; 104 uint32_t IntBitWidth = IntVT.getSizeInBits(); 105 bool isExact; 106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 107 APFloat::rmTowardZero, &isExact); 108 if (isExact) { 109 APInt IntVal(IntBitWidth, 2, x); 110 111 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 112 if (IntegerReg != 0) 113 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 114 } 115 } 116 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 117 if (!SelectOperator(CE, CE->getOpcode())) return 0; 118 Reg = LocalValueMap[CE]; 119 } else if (isa<UndefValue>(V)) { 120 Reg = createResultReg(TLI.getRegClassFor(VT)); 121 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 122 } 123 124 // If target-independent code couldn't handle the value, give target-specific 125 // code a try. 126 if (!Reg && isa<Constant>(V)) 127 Reg = TargetMaterializeConstant(cast<Constant>(V)); 128 129 // Don't cache constant materializations in the general ValueMap. 130 // To do so would require tracking what uses they dominate. 131 if (Reg != 0) 132 LocalValueMap[V] = Reg; 133 return Reg; 134} 135 136unsigned FastISel::lookUpRegForValue(Value *V) { 137 // Look up the value to see if we already have a register for it. We 138 // cache values defined by Instructions across blocks, and other values 139 // only locally. This is because Instructions already have the SSA 140 // def-dominatess-use requirement enforced. 141 if (ValueMap.count(V)) 142 return ValueMap[V]; 143 return LocalValueMap[V]; 144} 145 146/// UpdateValueMap - Update the value map to include the new mapping for this 147/// instruction, or insert an extra copy to get the result in a previous 148/// determined register. 149/// NOTE: This is only necessary because we might select a block that uses 150/// a value before we select the block that defines the value. It might be 151/// possible to fix this by selecting blocks in reverse postorder. 152unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 153 if (!isa<Instruction>(I)) { 154 LocalValueMap[I] = Reg; 155 return Reg; 156 } 157 158 unsigned &AssignedReg = ValueMap[I]; 159 if (AssignedReg == 0) 160 AssignedReg = Reg; 161 else if (Reg != AssignedReg) { 162 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 163 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 164 Reg, RegClass, RegClass); 165 } 166 return AssignedReg; 167} 168 169unsigned FastISel::getRegForGEPIndex(Value *Idx) { 170 unsigned IdxN = getRegForValue(Idx); 171 if (IdxN == 0) 172 // Unhandled operand. Halt "fast" selection and bail. 173 return 0; 174 175 // If the index is smaller or larger than intptr_t, truncate or extend it. 176 MVT PtrVT = TLI.getPointerTy(); 177 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 178 if (IdxVT.bitsLT(PtrVT)) 179 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 180 ISD::SIGN_EXTEND, IdxN); 181 else if (IdxVT.bitsGT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 183 ISD::TRUNCATE, IdxN); 184 return IdxN; 185} 186 187/// SelectBinaryOp - Select and emit code for a binary operator instruction, 188/// which has an opcode which directly corresponds to the given ISD opcode. 189/// 190bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 191 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 192 if (VT == MVT::Other || !VT.isSimple()) 193 // Unhandled type. Halt "fast" selection and bail. 194 return false; 195 196 // We only handle legal types. For example, on x86-32 the instruction 197 // selector contains all of the 64-bit instructions from x86-64, 198 // under the assumption that i64 won't be used if the target doesn't 199 // support it. 200 if (!TLI.isTypeLegal(VT)) { 201 // MVT::i1 is special. Allow AND, OR, or XOR because they 202 // don't require additional zeroing, which makes them easy. 203 if (VT == MVT::i1 && 204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 205 ISDOpcode == ISD::XOR)) 206 VT = TLI.getTypeToTransformTo(VT); 207 else 208 return false; 209 } 210 211 unsigned Op0 = getRegForValue(I->getOperand(0)); 212 if (Op0 == 0) 213 // Unhandled operand. Halt "fast" selection and bail. 214 return false; 215 216 // Check if the second operand is a constant and handle it appropriately. 217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 219 ISDOpcode, Op0, CI->getZExtValue()); 220 if (ResultReg != 0) { 221 // We successfully emitted code for the given LLVM Instruction. 222 UpdateValueMap(I, ResultReg); 223 return true; 224 } 225 } 226 227 // Check if the second operand is a constant float. 228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 230 ISDOpcode, Op0, CF); 231 if (ResultReg != 0) { 232 // We successfully emitted code for the given LLVM Instruction. 233 UpdateValueMap(I, ResultReg); 234 return true; 235 } 236 } 237 238 unsigned Op1 = getRegForValue(I->getOperand(1)); 239 if (Op1 == 0) 240 // Unhandled operand. Halt "fast" selection and bail. 241 return false; 242 243 // Now we have both operands in registers. Emit the instruction. 244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 245 ISDOpcode, Op0, Op1); 246 if (ResultReg == 0) 247 // Target-specific code wasn't able to find a machine opcode for 248 // the given ISD opcode and type. Halt "fast" selection and bail. 249 return false; 250 251 // We successfully emitted code for the given LLVM Instruction. 252 UpdateValueMap(I, ResultReg); 253 return true; 254} 255 256bool FastISel::SelectGetElementPtr(User *I) { 257 unsigned N = getRegForValue(I->getOperand(0)); 258 if (N == 0) 259 // Unhandled operand. Halt "fast" selection and bail. 260 return false; 261 262 const Type *Ty = I->getOperand(0)->getType(); 263 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 265 OI != E; ++OI) { 266 Value *Idx = *OI; 267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 269 if (Field) { 270 // N = N + Offset 271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 272 // FIXME: This can be optimized by combining the add with a 273 // subsequent one. 274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 275 if (N == 0) 276 // Unhandled operand. Halt "fast" selection and bail. 277 return false; 278 } 279 Ty = StTy->getElementType(Field); 280 } else { 281 Ty = cast<SequentialType>(Ty)->getElementType(); 282 283 // If this is a constant subscript, handle it quickly. 284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 285 if (CI->getZExtValue() == 0) continue; 286 uint64_t Offs = 287 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 289 if (N == 0) 290 // Unhandled operand. Halt "fast" selection and bail. 291 return false; 292 continue; 293 } 294 295 // N = N + Idx * ElementSize; 296 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 297 unsigned IdxN = getRegForGEPIndex(Idx); 298 if (IdxN == 0) 299 // Unhandled operand. Halt "fast" selection and bail. 300 return false; 301 302 if (ElementSize != 1) { 303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 304 if (IdxN == 0) 305 // Unhandled operand. Halt "fast" selection and bail. 306 return false; 307 } 308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 309 if (N == 0) 310 // Unhandled operand. Halt "fast" selection and bail. 311 return false; 312 } 313 } 314 315 // We successfully emitted code for the given LLVM Instruction. 316 UpdateValueMap(I, N); 317 return true; 318} 319 320bool FastISel::SelectCall(User *I) { 321 Function *F = cast<CallInst>(I)->getCalledFunction(); 322 if (!F) return false; 323 324 unsigned IID = F->getIntrinsicID(); 325 switch (IID) { 326 default: break; 327 case Intrinsic::dbg_stoppoint: { 328 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 329 if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) { 330 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 331 unsigned Line = SPI->getLine(); 332 unsigned Col = SPI->getColumn(); 333 unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col); 334 setCurDebugLoc(DebugLoc::get(Idx)); 335 } 336 return true; 337 } 338 case Intrinsic::dbg_region_start: { 339 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 340 if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) && 341 DW && DW->ShouldEmitDwarfDebug()) { 342 unsigned ID = 343 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 344 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 345 BuildMI(MBB, DL, II).addImm(ID); 346 } 347 return true; 348 } 349 case Intrinsic::dbg_region_end: { 350 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 351 if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) && 352 DW && DW->ShouldEmitDwarfDebug()) { 353 unsigned ID = 0; 354 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext())); 355 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) { 356 // This is end of an inlined function. 357 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 358 ID = DW->RecordInlinedFnEnd(Subprogram); 359 if (ID) 360 // Returned ID is 0 if this is unbalanced "end of inlined 361 // scope". This could happen if optimizer eats dbg intrinsics 362 // or "beginning of inlined scope" is not recoginized due to 363 // missing location info. In such cases, ignore this region.end. 364 BuildMI(MBB, DL, II).addImm(ID); 365 } else { 366 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 367 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 368 BuildMI(MBB, DL, II).addImm(ID); 369 } 370 } 371 return true; 372 } 373 case Intrinsic::dbg_func_start: { 374 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 375 Value *SP = FSI->getSubprogram(); 376 if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None)) 377 return true; 378 379 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 380 // (most?) gdb expects. 381 DebugLoc PrevLoc = DL; 382 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 383 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 384 385 if (!Subprogram.describes(MF.getFunction())) { 386 // This is a beginning of an inlined function. 387 388 // If llvm.dbg.func.start is seen in a new block before any 389 // llvm.dbg.stoppoint intrinsic then the location info is unknown. 390 // FIXME : Why DebugLoc is reset at the beginning of each block ? 391 if (PrevLoc.isUnknown()) 392 return true; 393 // Record the source line. 394 unsigned Line = Subprogram.getLineNumber(); 395 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID( 396 CompileUnit.getGV(), Line, 0))); 397 398 if (DW && DW->ShouldEmitDwarfDebug()) { 399 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc); 400 unsigned LabelID = DW->RecordInlinedFnStart(Subprogram, 401 DICompileUnit(PrevLocTpl.CompileUnit), 402 PrevLocTpl.Line, 403 PrevLocTpl.Col); 404 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 405 BuildMI(MBB, DL, II).addImm(LabelID); 406 } 407 } else { 408 // Record the source line. 409 unsigned Line = Subprogram.getLineNumber(); 410 MF.setDefaultDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID( 411 CompileUnit.getGV(), Line, 0))); 412 if (DW && DW->ShouldEmitDwarfDebug()) { 413 // llvm.dbg.func_start also defines beginning of function scope. 414 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram())); 415 } 416 } 417 418 return true; 419 } 420 case Intrinsic::dbg_declare: { 421 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 422 Value *Variable = DI->getVariable(); 423 if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) && 424 DW && DW->ShouldEmitDwarfDebug()) { 425 // Determine the address of the declared object. 426 Value *Address = DI->getAddress(); 427 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 428 Address = BCI->getOperand(0); 429 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 430 // Don't handle byval struct arguments or VLAs, for example. 431 if (!AI) break; 432 DenseMap<const AllocaInst*, int>::iterator SI = 433 StaticAllocaMap.find(AI); 434 if (SI == StaticAllocaMap.end()) break; // VLAs. 435 int FI = SI->second; 436 437 // Determine the debug globalvariable. 438 GlobalValue *GV = cast<GlobalVariable>(Variable); 439 440 // Build the DECLARE instruction. 441 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 442 MachineInstr *DeclareMI 443 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 444 DIVariable DV(cast<GlobalVariable>(GV)); 445 DW->RecordVariableScope(DV, DeclareMI); 446 } 447 return true; 448 } 449 case Intrinsic::eh_exception: { 450 MVT VT = TLI.getValueType(I->getType()); 451 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 452 default: break; 453 case TargetLowering::Expand: { 454 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 455 unsigned Reg = TLI.getExceptionAddressRegister(); 456 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 457 unsigned ResultReg = createResultReg(RC); 458 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 459 Reg, RC, RC); 460 assert(InsertedCopy && "Can't copy address registers!"); 461 InsertedCopy = InsertedCopy; 462 UpdateValueMap(I, ResultReg); 463 return true; 464 } 465 } 466 break; 467 } 468 case Intrinsic::eh_selector_i32: 469 case Intrinsic::eh_selector_i64: { 470 MVT VT = TLI.getValueType(I->getType()); 471 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 472 default: break; 473 case TargetLowering::Expand: { 474 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 475 MVT::i32 : MVT::i64); 476 477 if (MMI) { 478 if (MBB->isLandingPad()) 479 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 480 else { 481#ifndef NDEBUG 482 CatchInfoLost.insert(cast<CallInst>(I)); 483#endif 484 // FIXME: Mark exception selector register as live in. Hack for PR1508. 485 unsigned Reg = TLI.getExceptionSelectorRegister(); 486 if (Reg) MBB->addLiveIn(Reg); 487 } 488 489 unsigned Reg = TLI.getExceptionSelectorRegister(); 490 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 491 unsigned ResultReg = createResultReg(RC); 492 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 493 Reg, RC, RC); 494 assert(InsertedCopy && "Can't copy address registers!"); 495 InsertedCopy = InsertedCopy; 496 UpdateValueMap(I, ResultReg); 497 } else { 498 unsigned ResultReg = 499 getRegForValue(Constant::getNullValue(I->getType())); 500 UpdateValueMap(I, ResultReg); 501 } 502 return true; 503 } 504 } 505 break; 506 } 507 } 508 return false; 509} 510 511bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 512 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 513 MVT DstVT = TLI.getValueType(I->getType()); 514 515 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 516 DstVT == MVT::Other || !DstVT.isSimple()) 517 // Unhandled type. Halt "fast" selection and bail. 518 return false; 519 520 // Check if the destination type is legal. Or as a special case, 521 // it may be i1 if we're doing a truncate because that's 522 // easy and somewhat common. 523 if (!TLI.isTypeLegal(DstVT)) 524 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 525 // Unhandled type. Halt "fast" selection and bail. 526 return false; 527 528 // Check if the source operand is legal. Or as a special case, 529 // it may be i1 if we're doing zero-extension because that's 530 // easy and somewhat common. 531 if (!TLI.isTypeLegal(SrcVT)) 532 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 533 // Unhandled type. Halt "fast" selection and bail. 534 return false; 535 536 unsigned InputReg = getRegForValue(I->getOperand(0)); 537 if (!InputReg) 538 // Unhandled operand. Halt "fast" selection and bail. 539 return false; 540 541 // If the operand is i1, arrange for the high bits in the register to be zero. 542 if (SrcVT == MVT::i1) { 543 SrcVT = TLI.getTypeToTransformTo(SrcVT); 544 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 545 if (!InputReg) 546 return false; 547 } 548 // If the result is i1, truncate to the target's type for i1 first. 549 if (DstVT == MVT::i1) 550 DstVT = TLI.getTypeToTransformTo(DstVT); 551 552 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 553 DstVT.getSimpleVT(), 554 Opcode, 555 InputReg); 556 if (!ResultReg) 557 return false; 558 559 UpdateValueMap(I, ResultReg); 560 return true; 561} 562 563bool FastISel::SelectBitCast(User *I) { 564 // If the bitcast doesn't change the type, just use the operand value. 565 if (I->getType() == I->getOperand(0)->getType()) { 566 unsigned Reg = getRegForValue(I->getOperand(0)); 567 if (Reg == 0) 568 return false; 569 UpdateValueMap(I, Reg); 570 return true; 571 } 572 573 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 574 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 575 MVT DstVT = TLI.getValueType(I->getType()); 576 577 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 578 DstVT == MVT::Other || !DstVT.isSimple() || 579 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 580 // Unhandled type. Halt "fast" selection and bail. 581 return false; 582 583 unsigned Op0 = getRegForValue(I->getOperand(0)); 584 if (Op0 == 0) 585 // Unhandled operand. Halt "fast" selection and bail. 586 return false; 587 588 // First, try to perform the bitcast by inserting a reg-reg copy. 589 unsigned ResultReg = 0; 590 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 591 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 592 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 593 ResultReg = createResultReg(DstClass); 594 595 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 596 Op0, DstClass, SrcClass); 597 if (!InsertedCopy) 598 ResultReg = 0; 599 } 600 601 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 602 if (!ResultReg) 603 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 604 ISD::BIT_CONVERT, Op0); 605 606 if (!ResultReg) 607 return false; 608 609 UpdateValueMap(I, ResultReg); 610 return true; 611} 612 613bool 614FastISel::SelectInstruction(Instruction *I) { 615 return SelectOperator(I, I->getOpcode()); 616} 617 618/// FastEmitBranch - Emit an unconditional branch to the given block, 619/// unless it is the immediate (fall-through) successor, and update 620/// the CFG. 621void 622FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 623 MachineFunction::iterator NextMBB = 624 next(MachineFunction::iterator(MBB)); 625 626 if (MBB->isLayoutSuccessor(MSucc)) { 627 // The unconditional fall-through case, which needs no instructions. 628 } else { 629 // The unconditional branch case. 630 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 631 } 632 MBB->addSuccessor(MSucc); 633} 634 635bool 636FastISel::SelectOperator(User *I, unsigned Opcode) { 637 switch (Opcode) { 638 case Instruction::Add: 639 return SelectBinaryOp(I, ISD::ADD); 640 case Instruction::FAdd: 641 return SelectBinaryOp(I, ISD::FADD); 642 case Instruction::Sub: 643 return SelectBinaryOp(I, ISD::SUB); 644 case Instruction::FSub: 645 return SelectBinaryOp(I, ISD::FSUB); 646 case Instruction::Mul: 647 return SelectBinaryOp(I, ISD::MUL); 648 case Instruction::FMul: 649 return SelectBinaryOp(I, ISD::FMUL); 650 case Instruction::SDiv: 651 return SelectBinaryOp(I, ISD::SDIV); 652 case Instruction::UDiv: 653 return SelectBinaryOp(I, ISD::UDIV); 654 case Instruction::FDiv: 655 return SelectBinaryOp(I, ISD::FDIV); 656 case Instruction::SRem: 657 return SelectBinaryOp(I, ISD::SREM); 658 case Instruction::URem: 659 return SelectBinaryOp(I, ISD::UREM); 660 case Instruction::FRem: 661 return SelectBinaryOp(I, ISD::FREM); 662 case Instruction::Shl: 663 return SelectBinaryOp(I, ISD::SHL); 664 case Instruction::LShr: 665 return SelectBinaryOp(I, ISD::SRL); 666 case Instruction::AShr: 667 return SelectBinaryOp(I, ISD::SRA); 668 case Instruction::And: 669 return SelectBinaryOp(I, ISD::AND); 670 case Instruction::Or: 671 return SelectBinaryOp(I, ISD::OR); 672 case Instruction::Xor: 673 return SelectBinaryOp(I, ISD::XOR); 674 675 case Instruction::GetElementPtr: 676 return SelectGetElementPtr(I); 677 678 case Instruction::Br: { 679 BranchInst *BI = cast<BranchInst>(I); 680 681 if (BI->isUnconditional()) { 682 BasicBlock *LLVMSucc = BI->getSuccessor(0); 683 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 684 FastEmitBranch(MSucc); 685 return true; 686 } 687 688 // Conditional branches are not handed yet. 689 // Halt "fast" selection and bail. 690 return false; 691 } 692 693 case Instruction::Unreachable: 694 // Nothing to emit. 695 return true; 696 697 case Instruction::PHI: 698 // PHI nodes are already emitted. 699 return true; 700 701 case Instruction::Alloca: 702 // FunctionLowering has the static-sized case covered. 703 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 704 return true; 705 706 // Dynamic-sized alloca is not handled yet. 707 return false; 708 709 case Instruction::Call: 710 return SelectCall(I); 711 712 case Instruction::BitCast: 713 return SelectBitCast(I); 714 715 case Instruction::FPToSI: 716 return SelectCast(I, ISD::FP_TO_SINT); 717 case Instruction::ZExt: 718 return SelectCast(I, ISD::ZERO_EXTEND); 719 case Instruction::SExt: 720 return SelectCast(I, ISD::SIGN_EXTEND); 721 case Instruction::Trunc: 722 return SelectCast(I, ISD::TRUNCATE); 723 case Instruction::SIToFP: 724 return SelectCast(I, ISD::SINT_TO_FP); 725 726 case Instruction::IntToPtr: // Deliberate fall-through. 727 case Instruction::PtrToInt: { 728 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 729 MVT DstVT = TLI.getValueType(I->getType()); 730 if (DstVT.bitsGT(SrcVT)) 731 return SelectCast(I, ISD::ZERO_EXTEND); 732 if (DstVT.bitsLT(SrcVT)) 733 return SelectCast(I, ISD::TRUNCATE); 734 unsigned Reg = getRegForValue(I->getOperand(0)); 735 if (Reg == 0) return false; 736 UpdateValueMap(I, Reg); 737 return true; 738 } 739 740 default: 741 // Unhandled instruction. Halt "fast" selection and bail. 742 return false; 743 } 744} 745 746FastISel::FastISel(MachineFunction &mf, 747 MachineModuleInfo *mmi, 748 DwarfWriter *dw, 749 DenseMap<const Value *, unsigned> &vm, 750 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 751 DenseMap<const AllocaInst *, int> &am 752#ifndef NDEBUG 753 , SmallSet<Instruction*, 8> &cil 754#endif 755 ) 756 : MBB(0), 757 ValueMap(vm), 758 MBBMap(bm), 759 StaticAllocaMap(am), 760#ifndef NDEBUG 761 CatchInfoLost(cil), 762#endif 763 MF(mf), 764 MMI(mmi), 765 DW(dw), 766 MRI(MF.getRegInfo()), 767 MFI(*MF.getFrameInfo()), 768 MCP(*MF.getConstantPool()), 769 TM(MF.getTarget()), 770 TD(*TM.getTargetData()), 771 TII(*TM.getInstrInfo()), 772 TLI(*TM.getTargetLowering()) { 773} 774 775FastISel::~FastISel() {} 776 777unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 778 ISD::NodeType) { 779 return 0; 780} 781 782unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 783 ISD::NodeType, unsigned /*Op0*/) { 784 return 0; 785} 786 787unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 788 ISD::NodeType, unsigned /*Op0*/, 789 unsigned /*Op0*/) { 790 return 0; 791} 792 793unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 794 ISD::NodeType, uint64_t /*Imm*/) { 795 return 0; 796} 797 798unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 799 ISD::NodeType, ConstantFP * /*FPImm*/) { 800 return 0; 801} 802 803unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 804 ISD::NodeType, unsigned /*Op0*/, 805 uint64_t /*Imm*/) { 806 return 0; 807} 808 809unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 810 ISD::NodeType, unsigned /*Op0*/, 811 ConstantFP * /*FPImm*/) { 812 return 0; 813} 814 815unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 816 ISD::NodeType, 817 unsigned /*Op0*/, unsigned /*Op1*/, 818 uint64_t /*Imm*/) { 819 return 0; 820} 821 822/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 823/// to emit an instruction with an immediate operand using FastEmit_ri. 824/// If that fails, it materializes the immediate into a register and try 825/// FastEmit_rr instead. 826unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 827 unsigned Op0, uint64_t Imm, 828 MVT::SimpleValueType ImmType) { 829 // First check if immediate type is legal. If not, we can't use the ri form. 830 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 831 if (ResultReg != 0) 832 return ResultReg; 833 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 834 if (MaterialReg == 0) 835 return 0; 836 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 837} 838 839/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 840/// to emit an instruction with a floating-point immediate operand using 841/// FastEmit_rf. If that fails, it materializes the immediate into a register 842/// and try FastEmit_rr instead. 843unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 844 unsigned Op0, ConstantFP *FPImm, 845 MVT::SimpleValueType ImmType) { 846 // First check if immediate type is legal. If not, we can't use the rf form. 847 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 848 if (ResultReg != 0) 849 return ResultReg; 850 851 // Materialize the constant in a register. 852 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 853 if (MaterialReg == 0) { 854 // If the target doesn't have a way to directly enter a floating-point 855 // value into a register, use an alternate approach. 856 // TODO: The current approach only supports floating-point constants 857 // that can be constructed by conversion from integer values. This should 858 // be replaced by code that creates a load from a constant-pool entry, 859 // which will require some target-specific work. 860 const APFloat &Flt = FPImm->getValueAPF(); 861 MVT IntVT = TLI.getPointerTy(); 862 863 uint64_t x[2]; 864 uint32_t IntBitWidth = IntVT.getSizeInBits(); 865 bool isExact; 866 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 867 APFloat::rmTowardZero, &isExact); 868 if (!isExact) 869 return 0; 870 APInt IntVal(IntBitWidth, 2, x); 871 872 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 873 ISD::Constant, IntVal.getZExtValue()); 874 if (IntegerReg == 0) 875 return 0; 876 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 877 ISD::SINT_TO_FP, IntegerReg); 878 if (MaterialReg == 0) 879 return 0; 880 } 881 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 882} 883 884unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 885 return MRI.createVirtualRegister(RC); 886} 887 888unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 889 const TargetRegisterClass* RC) { 890 unsigned ResultReg = createResultReg(RC); 891 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 892 893 BuildMI(MBB, DL, II, ResultReg); 894 return ResultReg; 895} 896 897unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 898 const TargetRegisterClass *RC, 899 unsigned Op0) { 900 unsigned ResultReg = createResultReg(RC); 901 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 902 903 if (II.getNumDefs() >= 1) 904 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 905 else { 906 BuildMI(MBB, DL, II).addReg(Op0); 907 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 908 II.ImplicitDefs[0], RC, RC); 909 if (!InsertedCopy) 910 ResultReg = 0; 911 } 912 913 return ResultReg; 914} 915 916unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 917 const TargetRegisterClass *RC, 918 unsigned Op0, unsigned Op1) { 919 unsigned ResultReg = createResultReg(RC); 920 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 921 922 if (II.getNumDefs() >= 1) 923 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 924 else { 925 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 926 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 927 II.ImplicitDefs[0], RC, RC); 928 if (!InsertedCopy) 929 ResultReg = 0; 930 } 931 return ResultReg; 932} 933 934unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 935 const TargetRegisterClass *RC, 936 unsigned Op0, uint64_t Imm) { 937 unsigned ResultReg = createResultReg(RC); 938 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 939 940 if (II.getNumDefs() >= 1) 941 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 942 else { 943 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 944 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 945 II.ImplicitDefs[0], RC, RC); 946 if (!InsertedCopy) 947 ResultReg = 0; 948 } 949 return ResultReg; 950} 951 952unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 953 const TargetRegisterClass *RC, 954 unsigned Op0, ConstantFP *FPImm) { 955 unsigned ResultReg = createResultReg(RC); 956 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 957 958 if (II.getNumDefs() >= 1) 959 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 960 else { 961 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 962 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 963 II.ImplicitDefs[0], RC, RC); 964 if (!InsertedCopy) 965 ResultReg = 0; 966 } 967 return ResultReg; 968} 969 970unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 971 const TargetRegisterClass *RC, 972 unsigned Op0, unsigned Op1, uint64_t Imm) { 973 unsigned ResultReg = createResultReg(RC); 974 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 975 976 if (II.getNumDefs() >= 1) 977 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 978 else { 979 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 980 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 981 II.ImplicitDefs[0], RC, RC); 982 if (!InsertedCopy) 983 ResultReg = 0; 984 } 985 return ResultReg; 986} 987 988unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 989 const TargetRegisterClass *RC, 990 uint64_t Imm) { 991 unsigned ResultReg = createResultReg(RC); 992 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 993 994 if (II.getNumDefs() >= 1) 995 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 996 else { 997 BuildMI(MBB, DL, II).addImm(Imm); 998 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 999 II.ImplicitDefs[0], RC, RC); 1000 if (!InsertedCopy) 1001 ResultReg = 0; 1002 } 1003 return ResultReg; 1004} 1005 1006unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 1007 unsigned Op0, uint32_t Idx) { 1008 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 1009 1010 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1011 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 1012 1013 if (II.getNumDefs() >= 1) 1014 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 1015 else { 1016 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1017 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1018 II.ImplicitDefs[0], RC, RC); 1019 if (!InsertedCopy) 1020 ResultReg = 0; 1021 } 1022 return ResultReg; 1023} 1024 1025/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1026/// with all but the least significant bit set to zero. 1027unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { 1028 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1029} 1030