FastISel.cpp revision 40a468f24909792f000e3ccc1dda7a27b9c34b69 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/Target/TargetMachine.h"
22using namespace llvm;
23
24unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &ValueMap) {
25  unsigned &Reg = ValueMap[V];
26  if (Reg != 0)
27    return Reg;
28
29  MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
30  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
31    if (CI->getValue().getActiveBits() > 64)
32      return 0;
33    Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
34  } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
35    Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
36
37    if (!Reg) {
38      const APFloat &Flt = CF->getValueAPF();
39      MVT IntVT = TLI.getPointerTy();
40
41      uint64_t x[2];
42      uint32_t IntBitWidth = IntVT.getSizeInBits();
43      if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
44                               APFloat::rmTowardZero) != APFloat::opOK)
45        return 0;
46      APInt IntVal(IntBitWidth, 2, x);
47
48      unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
49                                       ISD::Constant, IntVal.getZExtValue());
50      if (IntegerReg == 0)
51        return 0;
52      Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
53      if (Reg == 0)
54        return 0;
55    }
56  }
57
58  return Reg;
59}
60
61/// SelectBinaryOp - Select and emit code for a binary operator instruction,
62/// which has an opcode which directly corresponds to the given ISD opcode.
63///
64bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
65                              DenseMap<const Value*, unsigned> &ValueMap) {
66  MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
67  if (VT == MVT::Other || !VT.isSimple())
68    // Unhandled type. Halt "fast" selection and bail.
69    return false;
70  // We only handle legal types. For example, on x86-32 the instruction
71  // selector contains all of the 64-bit instructions from x86-64,
72  // under the assumption that i64 won't be used if the target doesn't
73  // support it.
74  if (!TLI.isTypeLegal(VT))
75    return false;
76
77  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
78  if (Op0 == 0)
79    // Unhandled operand. Halt "fast" selection and bail.
80    return false;
81
82  // Check if the second operand is a constant and handle it appropriately.
83  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
84    unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
85                                     ISDOpcode, Op0, CI->getZExtValue());
86    if (ResultReg != 0) {
87      // We successfully emitted code for the given LLVM Instruction.
88      ValueMap[I] = ResultReg;
89      return true;
90    }
91  }
92
93  // Check if the second operand is a constant float.
94  if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
95    unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
96                                     ISDOpcode, Op0, CF);
97    if (ResultReg != 0) {
98      // We successfully emitted code for the given LLVM Instruction.
99      ValueMap[I] = ResultReg;
100      return true;
101    }
102  }
103
104  unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
105  if (Op1 == 0)
106    // Unhandled operand. Halt "fast" selection and bail.
107    return false;
108
109  // Now we have both operands in registers. Emit the instruction.
110  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
111                                   ISDOpcode, Op0, Op1);
112  if (ResultReg == 0)
113    // Target-specific code wasn't able to find a machine opcode for
114    // the given ISD opcode and type. Halt "fast" selection and bail.
115    return false;
116
117  // We successfully emitted code for the given LLVM Instruction.
118  ValueMap[I] = ResultReg;
119  return true;
120}
121
122bool FastISel::SelectGetElementPtr(Instruction *I,
123                                   DenseMap<const Value*, unsigned> &ValueMap) {
124  unsigned N = getRegForValue(I->getOperand(0), ValueMap);
125  if (N == 0)
126    // Unhandled operand. Halt "fast" selection and bail.
127    return false;
128
129  const Type *Ty = I->getOperand(0)->getType();
130  MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
131  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
132       OI != E; ++OI) {
133    Value *Idx = *OI;
134    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
135      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
136      if (Field) {
137        // N = N + Offset
138        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
139        // FIXME: This can be optimized by combining the add with a
140        // subsequent one.
141        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
142        if (N == 0)
143          // Unhandled operand. Halt "fast" selection and bail.
144          return false;
145      }
146      Ty = StTy->getElementType(Field);
147    } else {
148      Ty = cast<SequentialType>(Ty)->getElementType();
149
150      // If this is a constant subscript, handle it quickly.
151      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
152        if (CI->getZExtValue() == 0) continue;
153        uint64_t Offs =
154          TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
155        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
156        if (N == 0)
157          // Unhandled operand. Halt "fast" selection and bail.
158          return false;
159        continue;
160      }
161
162      // N = N + Idx * ElementSize;
163      uint64_t ElementSize = TD.getABITypeSize(Ty);
164      unsigned IdxN = getRegForValue(Idx, ValueMap);
165      if (IdxN == 0)
166        // Unhandled operand. Halt "fast" selection and bail.
167        return false;
168
169      // If the index is smaller or larger than intptr_t, truncate or extend
170      // it.
171      MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
172      if (IdxVT.bitsLT(VT))
173        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
174      else if (IdxVT.bitsGT(VT))
175        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
176      if (IdxN == 0)
177        // Unhandled operand. Halt "fast" selection and bail.
178        return false;
179
180      if (ElementSize != 1) {
181        IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
182        if (IdxN == 0)
183          // Unhandled operand. Halt "fast" selection and bail.
184          return false;
185      }
186      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
187      if (N == 0)
188        // Unhandled operand. Halt "fast" selection and bail.
189        return false;
190    }
191  }
192
193  // We successfully emitted code for the given LLVM Instruction.
194  ValueMap[I] = N;
195  return true;
196}
197
198bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
199                          DenseMap<const Value*, unsigned> &ValueMap) {
200  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
201  MVT DstVT = TLI.getValueType(I->getType());
202
203  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
204      DstVT == MVT::Other || !DstVT.isSimple() ||
205      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
206    // Unhandled type. Halt "fast" selection and bail.
207    return false;
208
209  unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
210  if (!InputReg)
211    // Unhandled operand.  Halt "fast" selection and bail.
212    return false;
213
214  unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
215                                  DstVT.getSimpleVT(),
216                                  Opcode,
217                                  InputReg);
218  if (!ResultReg)
219    return false;
220
221  ValueMap[I] = ResultReg;
222  return true;
223}
224
225bool FastISel::SelectBitCast(Instruction *I,
226                             DenseMap<const Value*, unsigned> &ValueMap) {
227  // If the bitcast doesn't change the type, just use the operand value.
228  if (I->getType() == I->getOperand(0)->getType()) {
229    unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
230    if (Reg == 0)
231      return false;
232    ValueMap[I] = Reg;
233    return true;
234  }
235
236  // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
237  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
238  MVT DstVT = TLI.getValueType(I->getType());
239
240  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
241      DstVT == MVT::Other || !DstVT.isSimple() ||
242      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
243    // Unhandled type. Halt "fast" selection and bail.
244    return false;
245
246  unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
247  if (Op0 == 0)
248    // Unhandled operand. Halt "fast" selection and bail.
249    return false;
250
251  // First, try to perform the bitcast by inserting a reg-reg copy.
252  unsigned ResultReg = 0;
253  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
254    TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
255    TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
256    ResultReg = createResultReg(DstClass);
257
258    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
259                                         Op0, DstClass, SrcClass);
260    if (!InsertedCopy)
261      ResultReg = 0;
262  }
263
264  // If the reg-reg copy failed, select a BIT_CONVERT opcode.
265  if (!ResultReg)
266    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
267                           ISD::BIT_CONVERT, Op0);
268
269  if (!ResultReg)
270    return false;
271
272  ValueMap[I] = ResultReg;
273  return true;
274}
275
276BasicBlock::iterator
277FastISel::SelectInstructions(BasicBlock::iterator Begin,
278                             BasicBlock::iterator End,
279                             DenseMap<const Value*, unsigned> &ValueMap,
280                             DenseMap<const BasicBlock*,
281                                      MachineBasicBlock *> &MBBMap,
282                             MachineBasicBlock *mbb) {
283  MBB = mbb;
284  BasicBlock::iterator I = Begin;
285
286  for (; I != End; ++I) {
287    switch (I->getOpcode()) {
288    case Instruction::Add: {
289      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
290      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
291    }
292    case Instruction::Sub: {
293      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
294      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
295    }
296    case Instruction::Mul: {
297      ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
298      if (!SelectBinaryOp(I, Opc, ValueMap))  return I; break;
299    }
300    case Instruction::SDiv:
301      if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
302    case Instruction::UDiv:
303      if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
304    case Instruction::FDiv:
305      if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
306    case Instruction::SRem:
307      if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
308    case Instruction::URem:
309      if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
310    case Instruction::FRem:
311      if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
312    case Instruction::Shl:
313      if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
314    case Instruction::LShr:
315      if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
316    case Instruction::AShr:
317      if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
318    case Instruction::And:
319      if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
320    case Instruction::Or:
321      if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
322    case Instruction::Xor:
323      if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
324
325    case Instruction::GetElementPtr:
326      if (!SelectGetElementPtr(I, ValueMap)) return I;
327      break;
328
329    case Instruction::Br: {
330      BranchInst *BI = cast<BranchInst>(I);
331
332      if (BI->isUnconditional()) {
333        MachineFunction::iterator NextMBB =
334           next(MachineFunction::iterator(MBB));
335        BasicBlock *LLVMSucc = BI->getSuccessor(0);
336        MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
337
338        if (NextMBB != MF.end() && MSucc == NextMBB) {
339          // The unconditional fall-through case, which needs no instructions.
340        } else {
341          // The unconditional branch case.
342          TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
343        }
344        MBB->addSuccessor(MSucc);
345        break;
346      }
347
348      // Conditional branches are not handed yet.
349      // Halt "fast" selection and bail.
350      return I;
351    }
352
353    case Instruction::PHI:
354      // PHI nodes are already emitted.
355      break;
356
357    case Instruction::BitCast:
358      if (!SelectBitCast(I, ValueMap)) return I; break;
359
360    case Instruction::FPToSI:
361      if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
362      break;
363    case Instruction::ZExt:
364      if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
365      break;
366    case Instruction::SExt:
367      if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
368      break;
369    case Instruction::SIToFP:
370      if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
371      break;
372
373    case Instruction::IntToPtr: // Deliberate fall-through.
374    case Instruction::PtrToInt: {
375      MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
376      MVT DstVT = TLI.getValueType(I->getType());
377      if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
378        if (ValueMap[I->getOperand(0)]) {
379          ValueMap[I] = ValueMap[I->getOperand(0)];
380          break;
381        } else
382          // Unhandled operand
383          return I;
384      } else if (DstVT.bitsGT(SrcVT)) {
385        if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
386        break;
387      } else {
388        // TODO: Handle SrcVT > DstVT, where truncation is needed.
389        return I;
390      }
391    }
392
393    default:
394      // Unhandled instruction. Halt "fast" selection and bail.
395      return I;
396    }
397  }
398
399  return I;
400}
401
402FastISel::FastISel(MachineFunction &mf)
403  : MF(mf),
404    MRI(mf.getRegInfo()),
405    TM(mf.getTarget()),
406    TD(*TM.getTargetData()),
407    TII(*TM.getInstrInfo()),
408    TLI(*TM.getTargetLowering()) {
409}
410
411FastISel::~FastISel() {}
412
413unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
414  return 0;
415}
416
417unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
418                              ISD::NodeType, unsigned /*Op0*/) {
419  return 0;
420}
421
422unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
423                               ISD::NodeType, unsigned /*Op0*/,
424                               unsigned /*Op0*/) {
425  return 0;
426}
427
428unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
429                              ISD::NodeType, uint64_t /*Imm*/) {
430  return 0;
431}
432
433unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
434                              ISD::NodeType, ConstantFP * /*FPImm*/) {
435  return 0;
436}
437
438unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
439                               ISD::NodeType, unsigned /*Op0*/,
440                               uint64_t /*Imm*/) {
441  return 0;
442}
443
444unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
445                               ISD::NodeType, unsigned /*Op0*/,
446                               ConstantFP * /*FPImm*/) {
447  return 0;
448}
449
450unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
451                                ISD::NodeType,
452                                unsigned /*Op0*/, unsigned /*Op1*/,
453                                uint64_t /*Imm*/) {
454  return 0;
455}
456
457/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
458/// to emit an instruction with an immediate operand using FastEmit_ri.
459/// If that fails, it materializes the immediate into a register and try
460/// FastEmit_rr instead.
461unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
462                                unsigned Op0, uint64_t Imm,
463                                MVT::SimpleValueType ImmType) {
464  // First check if immediate type is legal. If not, we can't use the ri form.
465  unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
466  if (ResultReg != 0)
467    return ResultReg;
468  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
469  if (MaterialReg == 0)
470    return 0;
471  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
472}
473
474/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
475/// to emit an instruction with a floating-point immediate operand using
476/// FastEmit_rf. If that fails, it materializes the immediate into a register
477/// and try FastEmit_rr instead.
478unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
479                                unsigned Op0, ConstantFP *FPImm,
480                                MVT::SimpleValueType ImmType) {
481  // First check if immediate type is legal. If not, we can't use the rf form.
482  unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
483  if (ResultReg != 0)
484    return ResultReg;
485
486  // Materialize the constant in a register.
487  unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
488  if (MaterialReg == 0) {
489    // If the target doesn't have a way to directly enter a floating-point
490    // value into a register, use an alternate approach.
491    // TODO: The current approach only supports floating-point constants
492    // that can be constructed by conversion from integer values. This should
493    // be replaced by code that creates a load from a constant-pool entry,
494    // which will require some target-specific work.
495    const APFloat &Flt = FPImm->getValueAPF();
496    MVT IntVT = TLI.getPointerTy();
497
498    uint64_t x[2];
499    uint32_t IntBitWidth = IntVT.getSizeInBits();
500    if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
501                             APFloat::rmTowardZero) != APFloat::opOK)
502      return 0;
503    APInt IntVal(IntBitWidth, 2, x);
504
505    unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
506                                     ISD::Constant, IntVal.getZExtValue());
507    if (IntegerReg == 0)
508      return 0;
509    MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
510                             ISD::SINT_TO_FP, IntegerReg);
511    if (MaterialReg == 0)
512      return 0;
513  }
514  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
515}
516
517unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
518  return MRI.createVirtualRegister(RC);
519}
520
521unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
522                                 const TargetRegisterClass* RC) {
523  unsigned ResultReg = createResultReg(RC);
524  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
525
526  BuildMI(MBB, II, ResultReg);
527  return ResultReg;
528}
529
530unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
531                                  const TargetRegisterClass *RC,
532                                  unsigned Op0) {
533  unsigned ResultReg = createResultReg(RC);
534  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
535
536  BuildMI(MBB, II, ResultReg).addReg(Op0);
537  return ResultReg;
538}
539
540unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
541                                   const TargetRegisterClass *RC,
542                                   unsigned Op0, unsigned Op1) {
543  unsigned ResultReg = createResultReg(RC);
544  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
545
546  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
547  return ResultReg;
548}
549
550unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
551                                   const TargetRegisterClass *RC,
552                                   unsigned Op0, uint64_t Imm) {
553  unsigned ResultReg = createResultReg(RC);
554  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
555
556  BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
557  return ResultReg;
558}
559
560unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
561                                   const TargetRegisterClass *RC,
562                                   unsigned Op0, ConstantFP *FPImm) {
563  unsigned ResultReg = createResultReg(RC);
564  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
565
566  BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
567  return ResultReg;
568}
569
570unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
571                                    const TargetRegisterClass *RC,
572                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
573  unsigned ResultReg = createResultReg(RC);
574  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
575
576  BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
577  return ResultReg;
578}
579
580unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
581                                  const TargetRegisterClass *RC,
582                                  uint64_t Imm) {
583  unsigned ResultReg = createResultReg(RC);
584  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
585
586  BuildMI(MBB, II, ResultReg).addImm(Imm);
587  return ResultReg;
588}
589
590unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
591  const TargetRegisterClass* RC = MRI.getRegClass(Op0);
592  const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
593
594  unsigned ResultReg = createResultReg(SRC);
595  const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
596
597  BuildMI(MBB, II, ResultReg).addReg(Op0);
598  return ResultReg;
599}
600