FastISel.cpp revision 4183e31978146ea529a87a2fc47b96aeb6cbe000
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/Analysis/DebugInfo.h" 51#include "llvm/Target/TargetData.h" 52#include "llvm/Target/TargetInstrInfo.h" 53#include "llvm/Target/TargetLowering.h" 54#include "llvm/Target/TargetMachine.h" 55#include "FunctionLoweringInfo.h" 56using namespace llvm; 57 58unsigned FastISel::getRegForValue(Value *V) { 59 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 60 // Don't handle non-simple values in FastISel. 61 if (!RealVT.isSimple()) 62 return 0; 63 64 // Ignore illegal types. We must do this before looking up the value 65 // in ValueMap because Arguments are given virtual registers regardless 66 // of whether FastISel can handle them. 67 MVT VT = RealVT.getSimpleVT(); 68 if (!TLI.isTypeLegal(VT)) { 69 // Promote MVT::i1 to a legal type though, because it's common and easy. 70 if (VT == MVT::i1) 71 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 72 else 73 return 0; 74 } 75 76 // Look up the value to see if we already have a register for it. We 77 // cache values defined by Instructions across blocks, and other values 78 // only locally. This is because Instructions already have the SSA 79 // def-dominates-use requirement enforced. 80 if (ValueMap.count(V)) 81 return ValueMap[V]; 82 unsigned Reg = LocalValueMap[V]; 83 if (Reg != 0) 84 return Reg; 85 86 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 87 if (CI->getValue().getActiveBits() <= 64) 88 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 89 } else if (isa<AllocaInst>(V)) { 90 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 91 } else if (isa<ConstantPointerNull>(V)) { 92 // Translate this as an integer zero so that it can be 93 // local-CSE'd with actual integer zeros. 94 Reg = 95 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 97 // Try to emit the constant directly. 98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 99 100 if (!Reg) { 101 // Try to emit the constant by using an integer constant with a cast. 102 const APFloat &Flt = CF->getValueAPF(); 103 EVT IntVT = TLI.getPointerTy(); 104 105 uint64_t x[2]; 106 uint32_t IntBitWidth = IntVT.getSizeInBits(); 107 bool isExact; 108 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 109 APFloat::rmTowardZero, &isExact); 110 if (isExact) { 111 APInt IntVal(IntBitWidth, 2, x); 112 113 unsigned IntegerReg = 114 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 115 if (IntegerReg != 0) 116 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 117 } 118 } 119 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 120 if (!SelectOperator(CE, CE->getOpcode())) return 0; 121 Reg = LocalValueMap[CE]; 122 } else if (isa<UndefValue>(V)) { 123 Reg = createResultReg(TLI.getRegClassFor(VT)); 124 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 125 } 126 127 // If target-independent code couldn't handle the value, give target-specific 128 // code a try. 129 if (!Reg && isa<Constant>(V)) 130 Reg = TargetMaterializeConstant(cast<Constant>(V)); 131 132 // Don't cache constant materializations in the general ValueMap. 133 // To do so would require tracking what uses they dominate. 134 if (Reg != 0) 135 LocalValueMap[V] = Reg; 136 return Reg; 137} 138 139unsigned FastISel::lookUpRegForValue(Value *V) { 140 // Look up the value to see if we already have a register for it. We 141 // cache values defined by Instructions across blocks, and other values 142 // only locally. This is because Instructions already have the SSA 143 // def-dominatess-use requirement enforced. 144 if (ValueMap.count(V)) 145 return ValueMap[V]; 146 return LocalValueMap[V]; 147} 148 149/// UpdateValueMap - Update the value map to include the new mapping for this 150/// instruction, or insert an extra copy to get the result in a previous 151/// determined register. 152/// NOTE: This is only necessary because we might select a block that uses 153/// a value before we select the block that defines the value. It might be 154/// possible to fix this by selecting blocks in reverse postorder. 155unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 156 if (!isa<Instruction>(I)) { 157 LocalValueMap[I] = Reg; 158 return Reg; 159 } 160 161 unsigned &AssignedReg = ValueMap[I]; 162 if (AssignedReg == 0) 163 AssignedReg = Reg; 164 else if (Reg != AssignedReg) { 165 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 166 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 167 Reg, RegClass, RegClass); 168 } 169 return AssignedReg; 170} 171 172unsigned FastISel::getRegForGEPIndex(Value *Idx) { 173 unsigned IdxN = getRegForValue(Idx); 174 if (IdxN == 0) 175 // Unhandled operand. Halt "fast" selection and bail. 176 return 0; 177 178 // If the index is smaller or larger than intptr_t, truncate or extend it. 179 MVT PtrVT = TLI.getPointerTy(); 180 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 181 if (IdxVT.bitsLT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); 183 else if (IdxVT.bitsGT(PtrVT)) 184 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) { 192 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT VT = TLI.getPointerTy(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 // Handle selected intrinsic function calls. 326 unsigned IID = F->getIntrinsicID(); 327 switch (IID) { 328 default: break; 329 case Intrinsic::dbg_declare: { 330 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 331 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None) || 332 !MF.getMMI().hasDebugInfo()) 333 return true; 334 335 Value *Address = DI->getAddress(); 336 if (!Address) 337 return true; 338 if (isa<UndefValue>(Address)) 339 return true; 340 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 341 // Don't handle byval struct arguments or VLAs, for example. 342 if (!AI) break; 343 DenseMap<const AllocaInst*, int>::iterator SI = 344 StaticAllocaMap.find(AI); 345 if (SI == StaticAllocaMap.end()) break; // VLAs. 346 int FI = SI->second; 347 if (!DI->getDebugLoc().isUnknown()) 348 MF.getMMI().setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc()); 349 350 // Building the map above is target independent. Generating DBG_VALUE 351 // inline is target dependent; do this now. 352 (void)TargetSelectInstruction(cast<Instruction>(I)); 353 return true; 354 } 355 case Intrinsic::dbg_value: { 356 // This form of DBG_VALUE is target-independent. 357 DbgValueInst *DI = cast<DbgValueInst>(I); 358 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 359 Value *V = DI->getValue(); 360 if (!V) { 361 // Currently the optimizer can produce this; insert an undef to 362 // help debugging. Probably the optimizer should not do this. 363 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 364 addMetadata(DI->getVariable()); 365 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 366 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()). 367 addMetadata(DI->getVariable()); 368 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 369 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()). 370 addMetadata(DI->getVariable()); 371 } else if (unsigned Reg = lookUpRegForValue(V)) { 372 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()). 373 addMetadata(DI->getVariable()); 374 } else { 375 // We can't yet handle anything else here because it would require 376 // generating code, thus altering codegen because of debug info. 377 // Insert an undef so we can see what we dropped. 378 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()). 379 addMetadata(DI->getVariable()); 380 } 381 return true; 382 } 383 case Intrinsic::eh_exception: { 384 EVT VT = TLI.getValueType(I->getType()); 385 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 386 default: break; 387 case TargetLowering::Expand: { 388 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 389 unsigned Reg = TLI.getExceptionAddressRegister(); 390 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 391 unsigned ResultReg = createResultReg(RC); 392 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 393 Reg, RC, RC); 394 assert(InsertedCopy && "Can't copy address registers!"); 395 InsertedCopy = InsertedCopy; 396 UpdateValueMap(I, ResultReg); 397 return true; 398 } 399 } 400 break; 401 } 402 case Intrinsic::eh_selector: { 403 EVT VT = TLI.getValueType(I->getType()); 404 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 405 default: break; 406 case TargetLowering::Expand: { 407 if (MBB->isLandingPad()) 408 AddCatchInfo(*cast<CallInst>(I), &MF.getMMI(), MBB); 409 else { 410#ifndef NDEBUG 411 CatchInfoLost.insert(cast<CallInst>(I)); 412#endif 413 // FIXME: Mark exception selector register as live in. Hack for PR1508. 414 unsigned Reg = TLI.getExceptionSelectorRegister(); 415 if (Reg) MBB->addLiveIn(Reg); 416 } 417 418 unsigned Reg = TLI.getExceptionSelectorRegister(); 419 EVT SrcVT = TLI.getPointerTy(); 420 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 421 unsigned ResultReg = createResultReg(RC); 422 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 423 RC, RC); 424 assert(InsertedCopy && "Can't copy address registers!"); 425 InsertedCopy = InsertedCopy; 426 427 // Cast the register to the type of the selector. 428 if (SrcVT.bitsGT(MVT::i32)) 429 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 430 ResultReg); 431 else if (SrcVT.bitsLT(MVT::i32)) 432 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 433 ISD::SIGN_EXTEND, ResultReg); 434 if (ResultReg == 0) 435 // Unhandled operand. Halt "fast" selection and bail. 436 return false; 437 438 UpdateValueMap(I, ResultReg); 439 440 return true; 441 } 442 } 443 break; 444 } 445 } 446 447 // An arbitrary call. Bail. 448 return false; 449} 450 451bool FastISel::SelectCast(User *I, unsigned Opcode) { 452 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 453 EVT DstVT = TLI.getValueType(I->getType()); 454 455 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 456 DstVT == MVT::Other || !DstVT.isSimple()) 457 // Unhandled type. Halt "fast" selection and bail. 458 return false; 459 460 // Check if the destination type is legal. Or as a special case, 461 // it may be i1 if we're doing a truncate because that's 462 // easy and somewhat common. 463 if (!TLI.isTypeLegal(DstVT)) 464 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 465 // Unhandled type. Halt "fast" selection and bail. 466 return false; 467 468 // Check if the source operand is legal. Or as a special case, 469 // it may be i1 if we're doing zero-extension because that's 470 // easy and somewhat common. 471 if (!TLI.isTypeLegal(SrcVT)) 472 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 473 // Unhandled type. Halt "fast" selection and bail. 474 return false; 475 476 unsigned InputReg = getRegForValue(I->getOperand(0)); 477 if (!InputReg) 478 // Unhandled operand. Halt "fast" selection and bail. 479 return false; 480 481 // If the operand is i1, arrange for the high bits in the register to be zero. 482 if (SrcVT == MVT::i1) { 483 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 484 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 485 if (!InputReg) 486 return false; 487 } 488 // If the result is i1, truncate to the target's type for i1 first. 489 if (DstVT == MVT::i1) 490 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 491 492 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 493 DstVT.getSimpleVT(), 494 Opcode, 495 InputReg); 496 if (!ResultReg) 497 return false; 498 499 UpdateValueMap(I, ResultReg); 500 return true; 501} 502 503bool FastISel::SelectBitCast(User *I) { 504 // If the bitcast doesn't change the type, just use the operand value. 505 if (I->getType() == I->getOperand(0)->getType()) { 506 unsigned Reg = getRegForValue(I->getOperand(0)); 507 if (Reg == 0) 508 return false; 509 UpdateValueMap(I, Reg); 510 return true; 511 } 512 513 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 514 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 515 EVT DstVT = TLI.getValueType(I->getType()); 516 517 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 518 DstVT == MVT::Other || !DstVT.isSimple() || 519 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 520 // Unhandled type. Halt "fast" selection and bail. 521 return false; 522 523 unsigned Op0 = getRegForValue(I->getOperand(0)); 524 if (Op0 == 0) 525 // Unhandled operand. Halt "fast" selection and bail. 526 return false; 527 528 // First, try to perform the bitcast by inserting a reg-reg copy. 529 unsigned ResultReg = 0; 530 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 531 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 532 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 533 ResultReg = createResultReg(DstClass); 534 535 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 536 Op0, DstClass, SrcClass); 537 if (!InsertedCopy) 538 ResultReg = 0; 539 } 540 541 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 542 if (!ResultReg) 543 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 544 ISD::BIT_CONVERT, Op0); 545 546 if (!ResultReg) 547 return false; 548 549 UpdateValueMap(I, ResultReg); 550 return true; 551} 552 553bool 554FastISel::SelectInstruction(Instruction *I) { 555 // First, try doing target-independent selection. 556 if (SelectOperator(I, I->getOpcode())) 557 return true; 558 559 // Next, try calling the target to attempt to handle the instruction. 560 if (TargetSelectInstruction(I)) 561 return true; 562 563 return false; 564} 565 566/// FastEmitBranch - Emit an unconditional branch to the given block, 567/// unless it is the immediate (fall-through) successor, and update 568/// the CFG. 569void 570FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 571 if (MBB->isLayoutSuccessor(MSucc)) { 572 // The unconditional fall-through case, which needs no instructions. 573 } else { 574 // The unconditional branch case. 575 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 576 } 577 MBB->addSuccessor(MSucc); 578} 579 580/// SelectFNeg - Emit an FNeg operation. 581/// 582bool 583FastISel::SelectFNeg(User *I) { 584 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 585 if (OpReg == 0) return false; 586 587 // If the target has ISD::FNEG, use it. 588 EVT VT = TLI.getValueType(I->getType()); 589 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 590 ISD::FNEG, OpReg); 591 if (ResultReg != 0) { 592 UpdateValueMap(I, ResultReg); 593 return true; 594 } 595 596 // Bitcast the value to integer, twiddle the sign bit with xor, 597 // and then bitcast it back to floating-point. 598 if (VT.getSizeInBits() > 64) return false; 599 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 600 if (!TLI.isTypeLegal(IntVT)) 601 return false; 602 603 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 604 ISD::BIT_CONVERT, OpReg); 605 if (IntReg == 0) 606 return false; 607 608 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, 609 UINT64_C(1) << (VT.getSizeInBits()-1), 610 IntVT.getSimpleVT()); 611 if (IntResultReg == 0) 612 return false; 613 614 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 615 ISD::BIT_CONVERT, IntResultReg); 616 if (ResultReg == 0) 617 return false; 618 619 UpdateValueMap(I, ResultReg); 620 return true; 621} 622 623bool 624FastISel::SelectOperator(User *I, unsigned Opcode) { 625 switch (Opcode) { 626 case Instruction::Add: 627 return SelectBinaryOp(I, ISD::ADD); 628 case Instruction::FAdd: 629 return SelectBinaryOp(I, ISD::FADD); 630 case Instruction::Sub: 631 return SelectBinaryOp(I, ISD::SUB); 632 case Instruction::FSub: 633 // FNeg is currently represented in LLVM IR as a special case of FSub. 634 if (BinaryOperator::isFNeg(I)) 635 return SelectFNeg(I); 636 return SelectBinaryOp(I, ISD::FSUB); 637 case Instruction::Mul: 638 return SelectBinaryOp(I, ISD::MUL); 639 case Instruction::FMul: 640 return SelectBinaryOp(I, ISD::FMUL); 641 case Instruction::SDiv: 642 return SelectBinaryOp(I, ISD::SDIV); 643 case Instruction::UDiv: 644 return SelectBinaryOp(I, ISD::UDIV); 645 case Instruction::FDiv: 646 return SelectBinaryOp(I, ISD::FDIV); 647 case Instruction::SRem: 648 return SelectBinaryOp(I, ISD::SREM); 649 case Instruction::URem: 650 return SelectBinaryOp(I, ISD::UREM); 651 case Instruction::FRem: 652 return SelectBinaryOp(I, ISD::FREM); 653 case Instruction::Shl: 654 return SelectBinaryOp(I, ISD::SHL); 655 case Instruction::LShr: 656 return SelectBinaryOp(I, ISD::SRL); 657 case Instruction::AShr: 658 return SelectBinaryOp(I, ISD::SRA); 659 case Instruction::And: 660 return SelectBinaryOp(I, ISD::AND); 661 case Instruction::Or: 662 return SelectBinaryOp(I, ISD::OR); 663 case Instruction::Xor: 664 return SelectBinaryOp(I, ISD::XOR); 665 666 case Instruction::GetElementPtr: 667 return SelectGetElementPtr(I); 668 669 case Instruction::Br: { 670 BranchInst *BI = cast<BranchInst>(I); 671 672 if (BI->isUnconditional()) { 673 BasicBlock *LLVMSucc = BI->getSuccessor(0); 674 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 675 FastEmitBranch(MSucc); 676 return true; 677 } 678 679 // Conditional branches are not handed yet. 680 // Halt "fast" selection and bail. 681 return false; 682 } 683 684 case Instruction::Unreachable: 685 // Nothing to emit. 686 return true; 687 688 case Instruction::PHI: 689 // PHI nodes are already emitted. 690 return true; 691 692 case Instruction::Alloca: 693 // FunctionLowering has the static-sized case covered. 694 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 695 return true; 696 697 // Dynamic-sized alloca is not handled yet. 698 return false; 699 700 case Instruction::Call: 701 return SelectCall(I); 702 703 case Instruction::BitCast: 704 return SelectBitCast(I); 705 706 case Instruction::FPToSI: 707 return SelectCast(I, ISD::FP_TO_SINT); 708 case Instruction::ZExt: 709 return SelectCast(I, ISD::ZERO_EXTEND); 710 case Instruction::SExt: 711 return SelectCast(I, ISD::SIGN_EXTEND); 712 case Instruction::Trunc: 713 return SelectCast(I, ISD::TRUNCATE); 714 case Instruction::SIToFP: 715 return SelectCast(I, ISD::SINT_TO_FP); 716 717 case Instruction::IntToPtr: // Deliberate fall-through. 718 case Instruction::PtrToInt: { 719 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 720 EVT DstVT = TLI.getValueType(I->getType()); 721 if (DstVT.bitsGT(SrcVT)) 722 return SelectCast(I, ISD::ZERO_EXTEND); 723 if (DstVT.bitsLT(SrcVT)) 724 return SelectCast(I, ISD::TRUNCATE); 725 unsigned Reg = getRegForValue(I->getOperand(0)); 726 if (Reg == 0) return false; 727 UpdateValueMap(I, Reg); 728 return true; 729 } 730 731 default: 732 // Unhandled instruction. Halt "fast" selection and bail. 733 return false; 734 } 735} 736 737FastISel::FastISel(MachineFunction &mf, 738 DenseMap<const Value *, unsigned> &vm, 739 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 740 DenseMap<const AllocaInst *, int> &am 741#ifndef NDEBUG 742 , SmallSet<Instruction*, 8> &cil 743#endif 744 ) 745 : MBB(0), 746 ValueMap(vm), 747 MBBMap(bm), 748 StaticAllocaMap(am), 749#ifndef NDEBUG 750 CatchInfoLost(cil), 751#endif 752 MF(mf), 753 MRI(MF.getRegInfo()), 754 MFI(*MF.getFrameInfo()), 755 MCP(*MF.getConstantPool()), 756 TM(MF.getTarget()), 757 TD(*TM.getTargetData()), 758 TII(*TM.getInstrInfo()), 759 TLI(*TM.getTargetLowering()) { 760} 761 762FastISel::~FastISel() {} 763 764unsigned FastISel::FastEmit_(MVT, MVT, 765 unsigned) { 766 return 0; 767} 768 769unsigned FastISel::FastEmit_r(MVT, MVT, 770 unsigned, unsigned /*Op0*/) { 771 return 0; 772} 773 774unsigned FastISel::FastEmit_rr(MVT, MVT, 775 unsigned, unsigned /*Op0*/, 776 unsigned /*Op0*/) { 777 return 0; 778} 779 780unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 781 return 0; 782} 783 784unsigned FastISel::FastEmit_f(MVT, MVT, 785 unsigned, ConstantFP * /*FPImm*/) { 786 return 0; 787} 788 789unsigned FastISel::FastEmit_ri(MVT, MVT, 790 unsigned, unsigned /*Op0*/, 791 uint64_t /*Imm*/) { 792 return 0; 793} 794 795unsigned FastISel::FastEmit_rf(MVT, MVT, 796 unsigned, unsigned /*Op0*/, 797 ConstantFP * /*FPImm*/) { 798 return 0; 799} 800 801unsigned FastISel::FastEmit_rri(MVT, MVT, 802 unsigned, 803 unsigned /*Op0*/, unsigned /*Op1*/, 804 uint64_t /*Imm*/) { 805 return 0; 806} 807 808/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 809/// to emit an instruction with an immediate operand using FastEmit_ri. 810/// If that fails, it materializes the immediate into a register and try 811/// FastEmit_rr instead. 812unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 813 unsigned Op0, uint64_t Imm, 814 MVT ImmType) { 815 // First check if immediate type is legal. If not, we can't use the ri form. 816 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 817 if (ResultReg != 0) 818 return ResultReg; 819 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 820 if (MaterialReg == 0) 821 return 0; 822 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 823} 824 825/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 826/// to emit an instruction with a floating-point immediate operand using 827/// FastEmit_rf. If that fails, it materializes the immediate into a register 828/// and try FastEmit_rr instead. 829unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 830 unsigned Op0, ConstantFP *FPImm, 831 MVT ImmType) { 832 // First check if immediate type is legal. If not, we can't use the rf form. 833 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 834 if (ResultReg != 0) 835 return ResultReg; 836 837 // Materialize the constant in a register. 838 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 839 if (MaterialReg == 0) { 840 // If the target doesn't have a way to directly enter a floating-point 841 // value into a register, use an alternate approach. 842 // TODO: The current approach only supports floating-point constants 843 // that can be constructed by conversion from integer values. This should 844 // be replaced by code that creates a load from a constant-pool entry, 845 // which will require some target-specific work. 846 const APFloat &Flt = FPImm->getValueAPF(); 847 EVT IntVT = TLI.getPointerTy(); 848 849 uint64_t x[2]; 850 uint32_t IntBitWidth = IntVT.getSizeInBits(); 851 bool isExact; 852 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 853 APFloat::rmTowardZero, &isExact); 854 if (!isExact) 855 return 0; 856 APInt IntVal(IntBitWidth, 2, x); 857 858 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 859 ISD::Constant, IntVal.getZExtValue()); 860 if (IntegerReg == 0) 861 return 0; 862 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 863 ISD::SINT_TO_FP, IntegerReg); 864 if (MaterialReg == 0) 865 return 0; 866 } 867 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 868} 869 870unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 871 return MRI.createVirtualRegister(RC); 872} 873 874unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 875 const TargetRegisterClass* RC) { 876 unsigned ResultReg = createResultReg(RC); 877 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 878 879 BuildMI(MBB, DL, II, ResultReg); 880 return ResultReg; 881} 882 883unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 884 const TargetRegisterClass *RC, 885 unsigned Op0) { 886 unsigned ResultReg = createResultReg(RC); 887 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 888 889 if (II.getNumDefs() >= 1) 890 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 891 else { 892 BuildMI(MBB, DL, II).addReg(Op0); 893 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 894 II.ImplicitDefs[0], RC, RC); 895 if (!InsertedCopy) 896 ResultReg = 0; 897 } 898 899 return ResultReg; 900} 901 902unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 903 const TargetRegisterClass *RC, 904 unsigned Op0, unsigned Op1) { 905 unsigned ResultReg = createResultReg(RC); 906 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 907 908 if (II.getNumDefs() >= 1) 909 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 910 else { 911 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 912 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 913 II.ImplicitDefs[0], RC, RC); 914 if (!InsertedCopy) 915 ResultReg = 0; 916 } 917 return ResultReg; 918} 919 920unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 921 const TargetRegisterClass *RC, 922 unsigned Op0, uint64_t Imm) { 923 unsigned ResultReg = createResultReg(RC); 924 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 925 926 if (II.getNumDefs() >= 1) 927 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 928 else { 929 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 930 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 931 II.ImplicitDefs[0], RC, RC); 932 if (!InsertedCopy) 933 ResultReg = 0; 934 } 935 return ResultReg; 936} 937 938unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 939 const TargetRegisterClass *RC, 940 unsigned Op0, ConstantFP *FPImm) { 941 unsigned ResultReg = createResultReg(RC); 942 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 943 944 if (II.getNumDefs() >= 1) 945 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 946 else { 947 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 948 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 949 II.ImplicitDefs[0], RC, RC); 950 if (!InsertedCopy) 951 ResultReg = 0; 952 } 953 return ResultReg; 954} 955 956unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 957 const TargetRegisterClass *RC, 958 unsigned Op0, unsigned Op1, uint64_t Imm) { 959 unsigned ResultReg = createResultReg(RC); 960 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 961 962 if (II.getNumDefs() >= 1) 963 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 964 else { 965 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 966 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 967 II.ImplicitDefs[0], RC, RC); 968 if (!InsertedCopy) 969 ResultReg = 0; 970 } 971 return ResultReg; 972} 973 974unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 975 const TargetRegisterClass *RC, 976 uint64_t Imm) { 977 unsigned ResultReg = createResultReg(RC); 978 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 979 980 if (II.getNumDefs() >= 1) 981 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 982 else { 983 BuildMI(MBB, DL, II).addImm(Imm); 984 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 985 II.ImplicitDefs[0], RC, RC); 986 if (!InsertedCopy) 987 ResultReg = 0; 988 } 989 return ResultReg; 990} 991 992unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 993 unsigned Op0, uint32_t Idx) { 994 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 995 996 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 997 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG); 998 999 if (II.getNumDefs() >= 1) 1000 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 1001 else { 1002 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 1003 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1004 II.ImplicitDefs[0], RC, RC); 1005 if (!InsertedCopy) 1006 ResultReg = 0; 1007 } 1008 return ResultReg; 1009} 1010 1011/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1012/// with all but the least significant bit set to zero. 1013unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) { 1014 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1015} 1016