FastISel.cpp revision 44d23825d61d530b8d562329ec8fc2d4f843bb8d
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#define DEBUG_TYPE "isel" 43#include "llvm/Function.h" 44#include "llvm/GlobalVariable.h" 45#include "llvm/Instructions.h" 46#include "llvm/IntrinsicInst.h" 47#include "llvm/Operator.h" 48#include "llvm/CodeGen/Analysis.h" 49#include "llvm/CodeGen/FastISel.h" 50#include "llvm/CodeGen/FunctionLoweringInfo.h" 51#include "llvm/CodeGen/MachineInstrBuilder.h" 52#include "llvm/CodeGen/MachineModuleInfo.h" 53#include "llvm/CodeGen/MachineRegisterInfo.h" 54#include "llvm/Analysis/DebugInfo.h" 55#include "llvm/Analysis/Loads.h" 56#include "llvm/Target/TargetData.h" 57#include "llvm/Target/TargetInstrInfo.h" 58#include "llvm/Target/TargetLowering.h" 59#include "llvm/Target/TargetMachine.h" 60#include "llvm/Support/ErrorHandling.h" 61#include "llvm/Support/Debug.h" 62#include "llvm/ADT/Statistic.h" 63using namespace llvm; 64 65STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by " 66 "target-independent selector"); 67STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by " 68 "target-specific selector"); 69STATISTIC(NumFastIselDead, "Number of dead insts removed on failure"); 70 71/// startNewBlock - Set the current block to which generated machine 72/// instructions will be appended, and clear the local CSE map. 73/// 74void FastISel::startNewBlock() { 75 LocalValueMap.clear(); 76 77 EmitStartPt = 0; 78 79 // Advance the emit start point past any EH_LABEL instructions. 80 MachineBasicBlock::iterator 81 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end(); 82 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { 83 EmitStartPt = I; 84 ++I; 85 } 86 LastLocalValue = EmitStartPt; 87} 88 89void FastISel::flushLocalValueMap() { 90 LocalValueMap.clear(); 91 LastLocalValue = EmitStartPt; 92 recomputeInsertPt(); 93} 94 95bool FastISel::hasTrivialKill(const Value *V) const { 96 // Don't consider constants or arguments to have trivial kills. 97 const Instruction *I = dyn_cast<Instruction>(V); 98 if (!I) 99 return false; 100 101 // No-op casts are trivially coalesced by fast-isel. 102 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 103 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 104 !hasTrivialKill(Cast->getOperand(0))) 105 return false; 106 107 // GEPs with all zero indices are trivially coalesced by fast-isel. 108 if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I)) 109 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0))) 110 return false; 111 112 // Only instructions with a single use in the same basic block are considered 113 // to have trivial kills. 114 return I->hasOneUse() && 115 !(I->getOpcode() == Instruction::BitCast || 116 I->getOpcode() == Instruction::PtrToInt || 117 I->getOpcode() == Instruction::IntToPtr) && 118 cast<Instruction>(*I->use_begin())->getParent() == I->getParent(); 119} 120 121unsigned FastISel::getRegForValue(const Value *V) { 122 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 123 // Don't handle non-simple values in FastISel. 124 if (!RealVT.isSimple()) 125 return 0; 126 127 // Ignore illegal types. We must do this before looking up the value 128 // in ValueMap because Arguments are given virtual registers regardless 129 // of whether FastISel can handle them. 130 MVT VT = RealVT.getSimpleVT(); 131 if (!TLI.isTypeLegal(VT)) { 132 // Handle integer promotions, though, because they're common and easy. 133 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 134 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 135 else 136 return 0; 137 } 138 139 // Look up the value to see if we already have a register for it. We 140 // cache values defined by Instructions across blocks, and other values 141 // only locally. This is because Instructions already have the SSA 142 // def-dominates-use requirement enforced. 143 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 144 if (I != FuncInfo.ValueMap.end()) 145 return I->second; 146 147 unsigned Reg = LocalValueMap[V]; 148 if (Reg != 0) 149 return Reg; 150 151 // In bottom-up mode, just create the virtual register which will be used 152 // to hold the value. It will be materialized later. 153 if (isa<Instruction>(V) && 154 (!isa<AllocaInst>(V) || 155 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) 156 return FuncInfo.InitializeRegForValue(V); 157 158 SavePoint SaveInsertPt = enterLocalValueArea(); 159 160 // Materialize the value in a register. Emit any instructions in the 161 // local value area. 162 Reg = materializeRegForValue(V, VT); 163 164 leaveLocalValueArea(SaveInsertPt); 165 166 return Reg; 167} 168 169/// materializeRegForValue - Helper for getRegForValue. This function is 170/// called when the value isn't already available in a register and must 171/// be materialized with new instructions. 172unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 173 unsigned Reg = 0; 174 175 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 176 if (CI->getValue().getActiveBits() <= 64) 177 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 178 } else if (isa<AllocaInst>(V)) { 179 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 180 } else if (isa<ConstantPointerNull>(V)) { 181 // Translate this as an integer zero so that it can be 182 // local-CSE'd with actual integer zeros. 183 Reg = 184 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 185 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 186 if (CF->isNullValue()) { 187 Reg = TargetMaterializeFloatZero(CF); 188 } else { 189 // Try to emit the constant directly. 190 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 191 } 192 193 if (!Reg) { 194 // Try to emit the constant by using an integer constant with a cast. 195 const APFloat &Flt = CF->getValueAPF(); 196 EVT IntVT = TLI.getPointerTy(); 197 198 uint64_t x[2]; 199 uint32_t IntBitWidth = IntVT.getSizeInBits(); 200 bool isExact; 201 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 202 APFloat::rmTowardZero, &isExact); 203 if (isExact) { 204 APInt IntVal(IntBitWidth, x); 205 206 unsigned IntegerReg = 207 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 208 if (IntegerReg != 0) 209 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 210 IntegerReg, /*Kill=*/false); 211 } 212 } 213 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 214 if (!SelectOperator(Op, Op->getOpcode())) 215 if (!isa<Instruction>(Op) || 216 !TargetSelectInstruction(cast<Instruction>(Op))) 217 return 0; 218 Reg = lookUpRegForValue(Op); 219 } else if (isa<UndefValue>(V)) { 220 Reg = createResultReg(TLI.getRegClassFor(VT)); 221 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 222 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 223 } 224 225 // If target-independent code couldn't handle the value, give target-specific 226 // code a try. 227 if (!Reg && isa<Constant>(V)) 228 Reg = TargetMaterializeConstant(cast<Constant>(V)); 229 230 // Don't cache constant materializations in the general ValueMap. 231 // To do so would require tracking what uses they dominate. 232 if (Reg != 0) { 233 LocalValueMap[V] = Reg; 234 LastLocalValue = MRI.getVRegDef(Reg); 235 } 236 return Reg; 237} 238 239unsigned FastISel::lookUpRegForValue(const Value *V) { 240 // Look up the value to see if we already have a register for it. We 241 // cache values defined by Instructions across blocks, and other values 242 // only locally. This is because Instructions already have the SSA 243 // def-dominates-use requirement enforced. 244 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 245 if (I != FuncInfo.ValueMap.end()) 246 return I->second; 247 return LocalValueMap[V]; 248} 249 250/// UpdateValueMap - Update the value map to include the new mapping for this 251/// instruction, or insert an extra copy to get the result in a previous 252/// determined register. 253/// NOTE: This is only necessary because we might select a block that uses 254/// a value before we select the block that defines the value. It might be 255/// possible to fix this by selecting blocks in reverse postorder. 256void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { 257 if (!isa<Instruction>(I)) { 258 LocalValueMap[I] = Reg; 259 return; 260 } 261 262 unsigned &AssignedReg = FuncInfo.ValueMap[I]; 263 if (AssignedReg == 0) 264 // Use the new register. 265 AssignedReg = Reg; 266 else if (Reg != AssignedReg) { 267 // Arrange for uses of AssignedReg to be replaced by uses of Reg. 268 for (unsigned i = 0; i < NumRegs; i++) 269 FuncInfo.RegFixups[AssignedReg+i] = Reg+i; 270 271 AssignedReg = Reg; 272 } 273} 274 275std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 276 unsigned IdxN = getRegForValue(Idx); 277 if (IdxN == 0) 278 // Unhandled operand. Halt "fast" selection and bail. 279 return std::pair<unsigned, bool>(0, false); 280 281 bool IdxNIsKill = hasTrivialKill(Idx); 282 283 // If the index is smaller or larger than intptr_t, truncate or extend it. 284 MVT PtrVT = TLI.getPointerTy(); 285 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 286 if (IdxVT.bitsLT(PtrVT)) { 287 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 288 IdxN, IdxNIsKill); 289 IdxNIsKill = true; 290 } 291 else if (IdxVT.bitsGT(PtrVT)) { 292 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 293 IdxN, IdxNIsKill); 294 IdxNIsKill = true; 295 } 296 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 297} 298 299void FastISel::recomputeInsertPt() { 300 if (getLastLocalValue()) { 301 FuncInfo.InsertPt = getLastLocalValue(); 302 FuncInfo.MBB = FuncInfo.InsertPt->getParent(); 303 ++FuncInfo.InsertPt; 304 } else 305 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI(); 306 307 // Now skip past any EH_LABELs, which must remain at the beginning. 308 while (FuncInfo.InsertPt != FuncInfo.MBB->end() && 309 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 310 ++FuncInfo.InsertPt; 311} 312 313void FastISel::removeDeadCode(MachineBasicBlock::iterator I, 314 MachineBasicBlock::iterator E) { 315 assert (I && E && std::distance(I, E) > 0 && "Invalid iterator!"); 316 while (I != E) { 317 MachineInstr *Dead = &*I; 318 ++I; 319 Dead->eraseFromParent(); 320 ++NumFastIselDead; 321 } 322 recomputeInsertPt(); 323} 324 325FastISel::SavePoint FastISel::enterLocalValueArea() { 326 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; 327 DebugLoc OldDL = DL; 328 recomputeInsertPt(); 329 DL = DebugLoc(); 330 SavePoint SP = { OldInsertPt, OldDL }; 331 return SP; 332} 333 334void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { 335 if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) 336 LastLocalValue = llvm::prior(FuncInfo.InsertPt); 337 338 // Restore the previous insert position. 339 FuncInfo.InsertPt = OldInsertPt.InsertPt; 340 DL = OldInsertPt.DL; 341} 342 343/// SelectBinaryOp - Select and emit code for a binary operator instruction, 344/// which has an opcode which directly corresponds to the given ISD opcode. 345/// 346bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 347 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 348 if (VT == MVT::Other || !VT.isSimple()) 349 // Unhandled type. Halt "fast" selection and bail. 350 return false; 351 352 // We only handle legal types. For example, on x86-32 the instruction 353 // selector contains all of the 64-bit instructions from x86-64, 354 // under the assumption that i64 won't be used if the target doesn't 355 // support it. 356 if (!TLI.isTypeLegal(VT)) { 357 // MVT::i1 is special. Allow AND, OR, or XOR because they 358 // don't require additional zeroing, which makes them easy. 359 if (VT == MVT::i1 && 360 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 361 ISDOpcode == ISD::XOR)) 362 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 363 else 364 return false; 365 } 366 367 // Check if the first operand is a constant, and handle it as "ri". At -O0, 368 // we don't have anything that canonicalizes operand order. 369 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0))) 370 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) { 371 unsigned Op1 = getRegForValue(I->getOperand(1)); 372 if (Op1 == 0) return false; 373 374 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 375 376 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, 377 Op1IsKill, CI->getZExtValue(), 378 VT.getSimpleVT()); 379 if (ResultReg == 0) return false; 380 381 // We successfully emitted code for the given LLVM Instruction. 382 UpdateValueMap(I, ResultReg); 383 return true; 384 } 385 386 387 unsigned Op0 = getRegForValue(I->getOperand(0)); 388 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail. 389 return false; 390 391 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 392 393 // Check if the second operand is a constant and handle it appropriately. 394 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 395 uint64_t Imm = CI->getZExtValue(); 396 397 // Transform "sdiv exact X, 8" -> "sra X, 3". 398 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && 399 cast<BinaryOperator>(I)->isExact() && 400 isPowerOf2_64(Imm)) { 401 Imm = Log2_64(Imm); 402 ISDOpcode = ISD::SRA; 403 } 404 405 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 406 Op0IsKill, Imm, VT.getSimpleVT()); 407 if (ResultReg == 0) return false; 408 409 // We successfully emitted code for the given LLVM Instruction. 410 UpdateValueMap(I, ResultReg); 411 return true; 412 } 413 414 // Check if the second operand is a constant float. 415 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 416 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 417 ISDOpcode, Op0, Op0IsKill, CF); 418 if (ResultReg != 0) { 419 // We successfully emitted code for the given LLVM Instruction. 420 UpdateValueMap(I, ResultReg); 421 return true; 422 } 423 } 424 425 unsigned Op1 = getRegForValue(I->getOperand(1)); 426 if (Op1 == 0) 427 // Unhandled operand. Halt "fast" selection and bail. 428 return false; 429 430 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 431 432 // Now we have both operands in registers. Emit the instruction. 433 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 434 ISDOpcode, 435 Op0, Op0IsKill, 436 Op1, Op1IsKill); 437 if (ResultReg == 0) 438 // Target-specific code wasn't able to find a machine opcode for 439 // the given ISD opcode and type. Halt "fast" selection and bail. 440 return false; 441 442 // We successfully emitted code for the given LLVM Instruction. 443 UpdateValueMap(I, ResultReg); 444 return true; 445} 446 447bool FastISel::SelectGetElementPtr(const User *I) { 448 unsigned N = getRegForValue(I->getOperand(0)); 449 if (N == 0) 450 // Unhandled operand. Halt "fast" selection and bail. 451 return false; 452 453 bool NIsKill = hasTrivialKill(I->getOperand(0)); 454 455 // Keep a running tab of the total offset to coalesce multiple N = N + Offset 456 // into a single N = N + TotalOffset. 457 uint64_t TotalOffs = 0; 458 // FIXME: What's a good SWAG number for MaxOffs? 459 uint64_t MaxOffs = 2048; 460 Type *Ty = I->getOperand(0)->getType(); 461 MVT VT = TLI.getPointerTy(); 462 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 463 E = I->op_end(); OI != E; ++OI) { 464 const Value *Idx = *OI; 465 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 466 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 467 if (Field) { 468 // N = N + Offset 469 TotalOffs += TD.getStructLayout(StTy)->getElementOffset(Field); 470 if (TotalOffs >= MaxOffs) { 471 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 472 if (N == 0) 473 // Unhandled operand. Halt "fast" selection and bail. 474 return false; 475 NIsKill = true; 476 TotalOffs = 0; 477 } 478 } 479 Ty = StTy->getElementType(Field); 480 } else { 481 Ty = cast<SequentialType>(Ty)->getElementType(); 482 483 // If this is a constant subscript, handle it quickly. 484 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 485 if (CI->isZero()) continue; 486 // N = N + Offset 487 TotalOffs += 488 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 489 if (TotalOffs >= MaxOffs) { 490 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 491 if (N == 0) 492 // Unhandled operand. Halt "fast" selection and bail. 493 return false; 494 NIsKill = true; 495 TotalOffs = 0; 496 } 497 continue; 498 } 499 if (TotalOffs) { 500 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 501 if (N == 0) 502 // Unhandled operand. Halt "fast" selection and bail. 503 return false; 504 NIsKill = true; 505 TotalOffs = 0; 506 } 507 508 // N = N + Idx * ElementSize; 509 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 510 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 511 unsigned IdxN = Pair.first; 512 bool IdxNIsKill = Pair.second; 513 if (IdxN == 0) 514 // Unhandled operand. Halt "fast" selection and bail. 515 return false; 516 517 if (ElementSize != 1) { 518 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 519 if (IdxN == 0) 520 // Unhandled operand. Halt "fast" selection and bail. 521 return false; 522 IdxNIsKill = true; 523 } 524 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 525 if (N == 0) 526 // Unhandled operand. Halt "fast" selection and bail. 527 return false; 528 } 529 } 530 if (TotalOffs) { 531 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT); 532 if (N == 0) 533 // Unhandled operand. Halt "fast" selection and bail. 534 return false; 535 } 536 537 // We successfully emitted code for the given LLVM Instruction. 538 UpdateValueMap(I, N); 539 return true; 540} 541 542bool FastISel::SelectCall(const User *I) { 543 const CallInst *Call = cast<CallInst>(I); 544 545 // Handle simple inline asms. 546 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) { 547 // Don't attempt to handle constraints. 548 if (!IA->getConstraintString().empty()) 549 return false; 550 551 unsigned ExtraInfo = 0; 552 if (IA->hasSideEffects()) 553 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 554 if (IA->isAlignStack()) 555 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 556 557 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 558 TII.get(TargetOpcode::INLINEASM)) 559 .addExternalSymbol(IA->getAsmString().c_str()) 560 .addImm(ExtraInfo); 561 return true; 562 } 563 564 const Function *F = Call->getCalledFunction(); 565 if (!F) return false; 566 567 // Handle selected intrinsic function calls. 568 switch (F->getIntrinsicID()) { 569 default: break; 570 // At -O0 we don't care about the lifetime intrinsics. 571 case Intrinsic::lifetime_start: 572 case Intrinsic::lifetime_end: 573 return true; 574 case Intrinsic::dbg_declare: { 575 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call); 576 if (!DIVariable(DI->getVariable()).Verify() || 577 !FuncInfo.MF->getMMI().hasDebugInfo()) 578 return true; 579 580 const Value *Address = DI->getAddress(); 581 if (!Address || isa<UndefValue>(Address) || isa<AllocaInst>(Address)) 582 return true; 583 584 unsigned Reg = 0; 585 unsigned Offset = 0; 586 if (const Argument *Arg = dyn_cast<Argument>(Address)) { 587 // Some arguments' frame index is recorded during argument lowering. 588 Offset = FuncInfo.getArgumentFrameIndex(Arg); 589 if (Offset) 590 Reg = TRI.getFrameRegister(*FuncInfo.MF); 591 } 592 if (!Reg) 593 Reg = getRegForValue(Address); 594 595 if (Reg) 596 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 597 TII.get(TargetOpcode::DBG_VALUE)) 598 .addReg(Reg, RegState::Debug).addImm(Offset) 599 .addMetadata(DI->getVariable()); 600 return true; 601 } 602 case Intrinsic::dbg_value: { 603 // This form of DBG_VALUE is target-independent. 604 const DbgValueInst *DI = cast<DbgValueInst>(Call); 605 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 606 const Value *V = DI->getValue(); 607 if (!V) { 608 // Currently the optimizer can produce this; insert an undef to 609 // help debugging. Probably the optimizer should not do this. 610 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 611 .addReg(0U).addImm(DI->getOffset()) 612 .addMetadata(DI->getVariable()); 613 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 614 if (CI->getBitWidth() > 64) 615 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 616 .addCImm(CI).addImm(DI->getOffset()) 617 .addMetadata(DI->getVariable()); 618 else 619 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 620 .addImm(CI->getZExtValue()).addImm(DI->getOffset()) 621 .addMetadata(DI->getVariable()); 622 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 624 .addFPImm(CF).addImm(DI->getOffset()) 625 .addMetadata(DI->getVariable()); 626 } else if (unsigned Reg = lookUpRegForValue(V)) { 627 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 628 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 629 .addMetadata(DI->getVariable()); 630 } else { 631 // We can't yet handle anything else here because it would require 632 // generating code, thus altering codegen because of debug info. 633 DEBUG(dbgs() << "Dropping debug info for " << DI); 634 } 635 return true; 636 } 637 case Intrinsic::objectsize: { 638 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1)); 639 unsigned long long Res = CI->isZero() ? -1ULL : 0; 640 Constant *ResCI = ConstantInt::get(Call->getType(), Res); 641 unsigned ResultReg = getRegForValue(ResCI); 642 if (ResultReg == 0) 643 return false; 644 UpdateValueMap(Call, ResultReg); 645 return true; 646 } 647 } 648 649 // Usually, it does not make sense to initialize a value, 650 // make an unrelated function call and use the value, because 651 // it tends to be spilled on the stack. So, we move the pointer 652 // to the last local value to the beginning of the block, so that 653 // all the values which have already been materialized, 654 // appear after the call. It also makes sense to skip intrinsics 655 // since they tend to be inlined. 656 if (!isa<IntrinsicInst>(F)) 657 flushLocalValueMap(); 658 659 // An arbitrary call. Bail. 660 return false; 661} 662 663bool FastISel::SelectCast(const User *I, unsigned Opcode) { 664 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 665 EVT DstVT = TLI.getValueType(I->getType()); 666 667 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 668 DstVT == MVT::Other || !DstVT.isSimple()) 669 // Unhandled type. Halt "fast" selection and bail. 670 return false; 671 672 // Check if the destination type is legal. 673 if (!TLI.isTypeLegal(DstVT)) 674 return false; 675 676 // Check if the source operand is legal. 677 if (!TLI.isTypeLegal(SrcVT)) 678 return false; 679 680 unsigned InputReg = getRegForValue(I->getOperand(0)); 681 if (!InputReg) 682 // Unhandled operand. Halt "fast" selection and bail. 683 return false; 684 685 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 686 687 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 688 DstVT.getSimpleVT(), 689 Opcode, 690 InputReg, InputRegIsKill); 691 if (!ResultReg) 692 return false; 693 694 UpdateValueMap(I, ResultReg); 695 return true; 696} 697 698bool FastISel::SelectBitCast(const User *I) { 699 // If the bitcast doesn't change the type, just use the operand value. 700 if (I->getType() == I->getOperand(0)->getType()) { 701 unsigned Reg = getRegForValue(I->getOperand(0)); 702 if (Reg == 0) 703 return false; 704 UpdateValueMap(I, Reg); 705 return true; 706 } 707 708 // Bitcasts of other values become reg-reg copies or BITCAST operators. 709 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 710 EVT DstVT = TLI.getValueType(I->getType()); 711 712 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 713 DstVT == MVT::Other || !DstVT.isSimple() || 714 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 715 // Unhandled type. Halt "fast" selection and bail. 716 return false; 717 718 unsigned Op0 = getRegForValue(I->getOperand(0)); 719 if (Op0 == 0) 720 // Unhandled operand. Halt "fast" selection and bail. 721 return false; 722 723 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 724 725 // First, try to perform the bitcast by inserting a reg-reg copy. 726 unsigned ResultReg = 0; 727 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 728 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 729 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 730 // Don't attempt a cross-class copy. It will likely fail. 731 if (SrcClass == DstClass) { 732 ResultReg = createResultReg(DstClass); 733 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 734 ResultReg).addReg(Op0); 735 } 736 } 737 738 // If the reg-reg copy failed, select a BITCAST opcode. 739 if (!ResultReg) 740 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 741 ISD::BITCAST, Op0, Op0IsKill); 742 743 if (!ResultReg) 744 return false; 745 746 UpdateValueMap(I, ResultReg); 747 return true; 748} 749 750bool 751FastISel::SelectInstruction(const Instruction *I) { 752 // Just before the terminator instruction, insert instructions to 753 // feed PHI nodes in successor blocks. 754 if (isa<TerminatorInst>(I)) 755 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 756 return false; 757 758 DL = I->getDebugLoc(); 759 760 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt; 761 762 // First, try doing target-independent selection. 763 if (SelectOperator(I, I->getOpcode())) { 764 ++NumFastIselSuccessIndependent; 765 DL = DebugLoc(); 766 return true; 767 } 768 // Remove dead code. However, ignore call instructions since we've flushed 769 // the local value map and recomputed the insert point. 770 if (!isa<CallInst>(I)) { 771 recomputeInsertPt(); 772 if (SavedInsertPt != FuncInfo.InsertPt) 773 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt); 774 } 775 776 // Next, try calling the target to attempt to handle the instruction. 777 SavedInsertPt = FuncInfo.InsertPt; 778 if (TargetSelectInstruction(I)) { 779 ++NumFastIselSuccessTarget; 780 DL = DebugLoc(); 781 return true; 782 } 783 // Check for dead code and remove as necessary. 784 recomputeInsertPt(); 785 if (SavedInsertPt != FuncInfo.InsertPt) 786 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt); 787 788 DL = DebugLoc(); 789 return false; 790} 791 792/// FastEmitBranch - Emit an unconditional branch to the given block, 793/// unless it is the immediate (fall-through) successor, and update 794/// the CFG. 795void 796FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 797 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) { 798 // The unconditional fall-through case, which needs no instructions. 799 } else { 800 // The unconditional branch case. 801 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 802 SmallVector<MachineOperand, 0>(), DL); 803 } 804 FuncInfo.MBB->addSuccessor(MSucc); 805} 806 807/// SelectFNeg - Emit an FNeg operation. 808/// 809bool 810FastISel::SelectFNeg(const User *I) { 811 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 812 if (OpReg == 0) return false; 813 814 bool OpRegIsKill = hasTrivialKill(I); 815 816 // If the target has ISD::FNEG, use it. 817 EVT VT = TLI.getValueType(I->getType()); 818 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 819 ISD::FNEG, OpReg, OpRegIsKill); 820 if (ResultReg != 0) { 821 UpdateValueMap(I, ResultReg); 822 return true; 823 } 824 825 // Bitcast the value to integer, twiddle the sign bit with xor, 826 // and then bitcast it back to floating-point. 827 if (VT.getSizeInBits() > 64) return false; 828 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 829 if (!TLI.isTypeLegal(IntVT)) 830 return false; 831 832 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 833 ISD::BITCAST, OpReg, OpRegIsKill); 834 if (IntReg == 0) 835 return false; 836 837 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 838 IntReg, /*Kill=*/true, 839 UINT64_C(1) << (VT.getSizeInBits()-1), 840 IntVT.getSimpleVT()); 841 if (IntResultReg == 0) 842 return false; 843 844 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 845 ISD::BITCAST, IntResultReg, /*Kill=*/true); 846 if (ResultReg == 0) 847 return false; 848 849 UpdateValueMap(I, ResultReg); 850 return true; 851} 852 853bool 854FastISel::SelectExtractValue(const User *U) { 855 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U); 856 if (!EVI) 857 return false; 858 859 // Make sure we only try to handle extracts with a legal result. But also 860 // allow i1 because it's easy. 861 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true); 862 if (!RealVT.isSimple()) 863 return false; 864 MVT VT = RealVT.getSimpleVT(); 865 if (!TLI.isTypeLegal(VT) && VT != MVT::i1) 866 return false; 867 868 const Value *Op0 = EVI->getOperand(0); 869 Type *AggTy = Op0->getType(); 870 871 // Get the base result register. 872 unsigned ResultReg; 873 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0); 874 if (I != FuncInfo.ValueMap.end()) 875 ResultReg = I->second; 876 else if (isa<Instruction>(Op0)) 877 ResultReg = FuncInfo.InitializeRegForValue(Op0); 878 else 879 return false; // fast-isel can't handle aggregate constants at the moment 880 881 // Get the actual result register, which is an offset from the base register. 882 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices()); 883 884 SmallVector<EVT, 4> AggValueVTs; 885 ComputeValueVTs(TLI, AggTy, AggValueVTs); 886 887 for (unsigned i = 0; i < VTIndex; i++) 888 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]); 889 890 UpdateValueMap(EVI, ResultReg); 891 return true; 892} 893 894bool 895FastISel::SelectOperator(const User *I, unsigned Opcode) { 896 switch (Opcode) { 897 case Instruction::Add: 898 return SelectBinaryOp(I, ISD::ADD); 899 case Instruction::FAdd: 900 return SelectBinaryOp(I, ISD::FADD); 901 case Instruction::Sub: 902 return SelectBinaryOp(I, ISD::SUB); 903 case Instruction::FSub: 904 // FNeg is currently represented in LLVM IR as a special case of FSub. 905 if (BinaryOperator::isFNeg(I)) 906 return SelectFNeg(I); 907 return SelectBinaryOp(I, ISD::FSUB); 908 case Instruction::Mul: 909 return SelectBinaryOp(I, ISD::MUL); 910 case Instruction::FMul: 911 return SelectBinaryOp(I, ISD::FMUL); 912 case Instruction::SDiv: 913 return SelectBinaryOp(I, ISD::SDIV); 914 case Instruction::UDiv: 915 return SelectBinaryOp(I, ISD::UDIV); 916 case Instruction::FDiv: 917 return SelectBinaryOp(I, ISD::FDIV); 918 case Instruction::SRem: 919 return SelectBinaryOp(I, ISD::SREM); 920 case Instruction::URem: 921 return SelectBinaryOp(I, ISD::UREM); 922 case Instruction::FRem: 923 return SelectBinaryOp(I, ISD::FREM); 924 case Instruction::Shl: 925 return SelectBinaryOp(I, ISD::SHL); 926 case Instruction::LShr: 927 return SelectBinaryOp(I, ISD::SRL); 928 case Instruction::AShr: 929 return SelectBinaryOp(I, ISD::SRA); 930 case Instruction::And: 931 return SelectBinaryOp(I, ISD::AND); 932 case Instruction::Or: 933 return SelectBinaryOp(I, ISD::OR); 934 case Instruction::Xor: 935 return SelectBinaryOp(I, ISD::XOR); 936 937 case Instruction::GetElementPtr: 938 return SelectGetElementPtr(I); 939 940 case Instruction::Br: { 941 const BranchInst *BI = cast<BranchInst>(I); 942 943 if (BI->isUnconditional()) { 944 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 945 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc]; 946 FastEmitBranch(MSucc, BI->getDebugLoc()); 947 return true; 948 } 949 950 // Conditional branches are not handed yet. 951 // Halt "fast" selection and bail. 952 return false; 953 } 954 955 case Instruction::Unreachable: 956 // Nothing to emit. 957 return true; 958 959 case Instruction::Alloca: 960 // FunctionLowering has the static-sized case covered. 961 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I))) 962 return true; 963 964 // Dynamic-sized alloca is not handled yet. 965 return false; 966 967 case Instruction::Call: 968 return SelectCall(I); 969 970 case Instruction::BitCast: 971 return SelectBitCast(I); 972 973 case Instruction::FPToSI: 974 return SelectCast(I, ISD::FP_TO_SINT); 975 case Instruction::ZExt: 976 return SelectCast(I, ISD::ZERO_EXTEND); 977 case Instruction::SExt: 978 return SelectCast(I, ISD::SIGN_EXTEND); 979 case Instruction::Trunc: 980 return SelectCast(I, ISD::TRUNCATE); 981 case Instruction::SIToFP: 982 return SelectCast(I, ISD::SINT_TO_FP); 983 984 case Instruction::IntToPtr: // Deliberate fall-through. 985 case Instruction::PtrToInt: { 986 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 987 EVT DstVT = TLI.getValueType(I->getType()); 988 if (DstVT.bitsGT(SrcVT)) 989 return SelectCast(I, ISD::ZERO_EXTEND); 990 if (DstVT.bitsLT(SrcVT)) 991 return SelectCast(I, ISD::TRUNCATE); 992 unsigned Reg = getRegForValue(I->getOperand(0)); 993 if (Reg == 0) return false; 994 UpdateValueMap(I, Reg); 995 return true; 996 } 997 998 case Instruction::ExtractValue: 999 return SelectExtractValue(I); 1000 1001 case Instruction::PHI: 1002 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 1003 1004 default: 1005 // Unhandled instruction. Halt "fast" selection and bail. 1006 return false; 1007 } 1008} 1009 1010FastISel::FastISel(FunctionLoweringInfo &funcInfo) 1011 : FuncInfo(funcInfo), 1012 MRI(FuncInfo.MF->getRegInfo()), 1013 MFI(*FuncInfo.MF->getFrameInfo()), 1014 MCP(*FuncInfo.MF->getConstantPool()), 1015 TM(FuncInfo.MF->getTarget()), 1016 TD(*TM.getTargetData()), 1017 TII(*TM.getInstrInfo()), 1018 TLI(*TM.getTargetLowering()), 1019 TRI(*TM.getRegisterInfo()) { 1020} 1021 1022FastISel::~FastISel() {} 1023 1024unsigned FastISel::FastEmit_(MVT, MVT, 1025 unsigned) { 1026 return 0; 1027} 1028 1029unsigned FastISel::FastEmit_r(MVT, MVT, 1030 unsigned, 1031 unsigned /*Op0*/, bool /*Op0IsKill*/) { 1032 return 0; 1033} 1034 1035unsigned FastISel::FastEmit_rr(MVT, MVT, 1036 unsigned, 1037 unsigned /*Op0*/, bool /*Op0IsKill*/, 1038 unsigned /*Op1*/, bool /*Op1IsKill*/) { 1039 return 0; 1040} 1041 1042unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 1043 return 0; 1044} 1045 1046unsigned FastISel::FastEmit_f(MVT, MVT, 1047 unsigned, const ConstantFP * /*FPImm*/) { 1048 return 0; 1049} 1050 1051unsigned FastISel::FastEmit_ri(MVT, MVT, 1052 unsigned, 1053 unsigned /*Op0*/, bool /*Op0IsKill*/, 1054 uint64_t /*Imm*/) { 1055 return 0; 1056} 1057 1058unsigned FastISel::FastEmit_rf(MVT, MVT, 1059 unsigned, 1060 unsigned /*Op0*/, bool /*Op0IsKill*/, 1061 const ConstantFP * /*FPImm*/) { 1062 return 0; 1063} 1064 1065unsigned FastISel::FastEmit_rri(MVT, MVT, 1066 unsigned, 1067 unsigned /*Op0*/, bool /*Op0IsKill*/, 1068 unsigned /*Op1*/, bool /*Op1IsKill*/, 1069 uint64_t /*Imm*/) { 1070 return 0; 1071} 1072 1073/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 1074/// to emit an instruction with an immediate operand using FastEmit_ri. 1075/// If that fails, it materializes the immediate into a register and try 1076/// FastEmit_rr instead. 1077unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 1078 unsigned Op0, bool Op0IsKill, 1079 uint64_t Imm, MVT ImmType) { 1080 // If this is a multiply by a power of two, emit this as a shift left. 1081 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) { 1082 Opcode = ISD::SHL; 1083 Imm = Log2_64(Imm); 1084 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { 1085 // div x, 8 -> srl x, 3 1086 Opcode = ISD::SRL; 1087 Imm = Log2_64(Imm); 1088 } 1089 1090 // Horrible hack (to be removed), check to make sure shift amounts are 1091 // in-range. 1092 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && 1093 Imm >= VT.getSizeInBits()) 1094 return 0; 1095 1096 // First check if immediate type is legal. If not, we can't use the ri form. 1097 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 1098 if (ResultReg != 0) 1099 return ResultReg; 1100 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 1101 if (MaterialReg == 0) { 1102 // This is a bit ugly/slow, but failing here means falling out of 1103 // fast-isel, which would be very slow. 1104 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(), 1105 VT.getSizeInBits()); 1106 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm)); 1107 } 1108 return FastEmit_rr(VT, VT, Opcode, 1109 Op0, Op0IsKill, 1110 MaterialReg, /*Kill=*/true); 1111} 1112 1113unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 1114 return MRI.createVirtualRegister(RC); 1115} 1116 1117unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 1118 const TargetRegisterClass* RC) { 1119 unsigned ResultReg = createResultReg(RC); 1120 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1121 1122 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); 1123 return ResultReg; 1124} 1125 1126unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 1127 const TargetRegisterClass *RC, 1128 unsigned Op0, bool Op0IsKill) { 1129 unsigned ResultReg = createResultReg(RC); 1130 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1131 1132 if (II.getNumDefs() >= 1) 1133 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1134 .addReg(Op0, Op0IsKill * RegState::Kill); 1135 else { 1136 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1137 .addReg(Op0, Op0IsKill * RegState::Kill); 1138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1139 ResultReg).addReg(II.ImplicitDefs[0]); 1140 } 1141 1142 return ResultReg; 1143} 1144 1145unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1146 const TargetRegisterClass *RC, 1147 unsigned Op0, bool Op0IsKill, 1148 unsigned Op1, bool Op1IsKill) { 1149 unsigned ResultReg = createResultReg(RC); 1150 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1151 1152 if (II.getNumDefs() >= 1) 1153 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1154 .addReg(Op0, Op0IsKill * RegState::Kill) 1155 .addReg(Op1, Op1IsKill * RegState::Kill); 1156 else { 1157 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1158 .addReg(Op0, Op0IsKill * RegState::Kill) 1159 .addReg(Op1, Op1IsKill * RegState::Kill); 1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1161 ResultReg).addReg(II.ImplicitDefs[0]); 1162 } 1163 return ResultReg; 1164} 1165 1166unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, 1167 const TargetRegisterClass *RC, 1168 unsigned Op0, bool Op0IsKill, 1169 unsigned Op1, bool Op1IsKill, 1170 unsigned Op2, bool Op2IsKill) { 1171 unsigned ResultReg = createResultReg(RC); 1172 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1173 1174 if (II.getNumDefs() >= 1) 1175 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1176 .addReg(Op0, Op0IsKill * RegState::Kill) 1177 .addReg(Op1, Op1IsKill * RegState::Kill) 1178 .addReg(Op2, Op2IsKill * RegState::Kill); 1179 else { 1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1181 .addReg(Op0, Op0IsKill * RegState::Kill) 1182 .addReg(Op1, Op1IsKill * RegState::Kill) 1183 .addReg(Op2, Op2IsKill * RegState::Kill); 1184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1185 ResultReg).addReg(II.ImplicitDefs[0]); 1186 } 1187 return ResultReg; 1188} 1189 1190unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1191 const TargetRegisterClass *RC, 1192 unsigned Op0, bool Op0IsKill, 1193 uint64_t Imm) { 1194 unsigned ResultReg = createResultReg(RC); 1195 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1196 1197 if (II.getNumDefs() >= 1) 1198 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1199 .addReg(Op0, Op0IsKill * RegState::Kill) 1200 .addImm(Imm); 1201 else { 1202 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1203 .addReg(Op0, Op0IsKill * RegState::Kill) 1204 .addImm(Imm); 1205 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1206 ResultReg).addReg(II.ImplicitDefs[0]); 1207 } 1208 return ResultReg; 1209} 1210 1211unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode, 1212 const TargetRegisterClass *RC, 1213 unsigned Op0, bool Op0IsKill, 1214 uint64_t Imm1, uint64_t Imm2) { 1215 unsigned ResultReg = createResultReg(RC); 1216 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1217 1218 if (II.getNumDefs() >= 1) 1219 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1220 .addReg(Op0, Op0IsKill * RegState::Kill) 1221 .addImm(Imm1) 1222 .addImm(Imm2); 1223 else { 1224 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1225 .addReg(Op0, Op0IsKill * RegState::Kill) 1226 .addImm(Imm1) 1227 .addImm(Imm2); 1228 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1229 ResultReg).addReg(II.ImplicitDefs[0]); 1230 } 1231 return ResultReg; 1232} 1233 1234unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1235 const TargetRegisterClass *RC, 1236 unsigned Op0, bool Op0IsKill, 1237 const ConstantFP *FPImm) { 1238 unsigned ResultReg = createResultReg(RC); 1239 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1240 1241 if (II.getNumDefs() >= 1) 1242 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1243 .addReg(Op0, Op0IsKill * RegState::Kill) 1244 .addFPImm(FPImm); 1245 else { 1246 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1247 .addReg(Op0, Op0IsKill * RegState::Kill) 1248 .addFPImm(FPImm); 1249 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1250 ResultReg).addReg(II.ImplicitDefs[0]); 1251 } 1252 return ResultReg; 1253} 1254 1255unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1256 const TargetRegisterClass *RC, 1257 unsigned Op0, bool Op0IsKill, 1258 unsigned Op1, bool Op1IsKill, 1259 uint64_t Imm) { 1260 unsigned ResultReg = createResultReg(RC); 1261 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1262 1263 if (II.getNumDefs() >= 1) 1264 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1265 .addReg(Op0, Op0IsKill * RegState::Kill) 1266 .addReg(Op1, Op1IsKill * RegState::Kill) 1267 .addImm(Imm); 1268 else { 1269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1270 .addReg(Op0, Op0IsKill * RegState::Kill) 1271 .addReg(Op1, Op1IsKill * RegState::Kill) 1272 .addImm(Imm); 1273 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1274 ResultReg).addReg(II.ImplicitDefs[0]); 1275 } 1276 return ResultReg; 1277} 1278 1279unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1280 const TargetRegisterClass *RC, 1281 uint64_t Imm) { 1282 unsigned ResultReg = createResultReg(RC); 1283 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1284 1285 if (II.getNumDefs() >= 1) 1286 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); 1287 else { 1288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm); 1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1290 ResultReg).addReg(II.ImplicitDefs[0]); 1291 } 1292 return ResultReg; 1293} 1294 1295unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode, 1296 const TargetRegisterClass *RC, 1297 uint64_t Imm1, uint64_t Imm2) { 1298 unsigned ResultReg = createResultReg(RC); 1299 const MCInstrDesc &II = TII.get(MachineInstOpcode); 1300 1301 if (II.getNumDefs() >= 1) 1302 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1303 .addImm(Imm1).addImm(Imm2); 1304 else { 1305 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2); 1306 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1307 ResultReg).addReg(II.ImplicitDefs[0]); 1308 } 1309 return ResultReg; 1310} 1311 1312unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1313 unsigned Op0, bool Op0IsKill, 1314 uint32_t Idx) { 1315 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1316 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 1317 "Cannot yet extract from physregs"); 1318 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 1319 DL, TII.get(TargetOpcode::COPY), ResultReg) 1320 .addReg(Op0, getKillRegState(Op0IsKill), Idx); 1321 return ResultReg; 1322} 1323 1324/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1325/// with all but the least significant bit set to zero. 1326unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1327 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1328} 1329 1330/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1331/// Emit code to ensure constants are copied into registers when needed. 1332/// Remember the virtual registers that need to be added to the Machine PHI 1333/// nodes as input. We cannot just directly add them, because expansion 1334/// might result in multiple MBB's for one BB. As such, the start of the 1335/// BB might correspond to a different MBB than the end. 1336bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1337 const TerminatorInst *TI = LLVMBB->getTerminator(); 1338 1339 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1340 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); 1341 1342 // Check successor nodes' PHI nodes that expect a constant to be available 1343 // from this block. 1344 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1345 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1346 if (!isa<PHINode>(SuccBB->begin())) continue; 1347 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 1348 1349 // If this terminator has multiple identical successors (common for 1350 // switches), only handle each succ once. 1351 if (!SuccsHandled.insert(SuccMBB)) continue; 1352 1353 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1354 1355 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1356 // nodes and Machine PHI nodes, but the incoming operands have not been 1357 // emitted yet. 1358 for (BasicBlock::const_iterator I = SuccBB->begin(); 1359 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1360 1361 // Ignore dead phi's. 1362 if (PN->use_empty()) continue; 1363 1364 // Only handle legal types. Two interesting things to note here. First, 1365 // by bailing out early, we may leave behind some dead instructions, 1366 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1367 // own moves. Second, this check is necessary because FastISel doesn't 1368 // use CreateRegs to create registers, so it always creates 1369 // exactly one register for each non-void instruction. 1370 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1371 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1372 // Handle integer promotions, though, because they're common and easy. 1373 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 1374 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1375 else { 1376 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1377 return false; 1378 } 1379 } 1380 1381 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1382 1383 // Set the DebugLoc for the copy. Prefer the location of the operand 1384 // if there is one; use the location of the PHI otherwise. 1385 DL = PN->getDebugLoc(); 1386 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1387 DL = Inst->getDebugLoc(); 1388 1389 unsigned Reg = getRegForValue(PHIOp); 1390 if (Reg == 0) { 1391 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1392 return false; 1393 } 1394 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1395 DL = DebugLoc(); 1396 } 1397 } 1398 1399 return true; 1400} 1401