FastISel.cpp revision 483f0db2d164142681731eb5dff96442af72c255 
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Instructions.h"
15#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetLowering.h"
21#include "llvm/Target/TargetMachine.h"
22using namespace llvm;
23
24unsigned FastISel::getRegForValue(Value *V) {
25  // Look up the value to see if we already have a register for it. We
26  // cache values defined by Instructions across blocks, and other values
27  // only locally. This is because Instructions already have the SSA
28  // def-dominatess-use requirement enforced.
29  if (ValueMap.count(V))
30    return ValueMap[V];
31  unsigned Reg = LocalValueMap[V];
32  if (Reg != 0)
33    return Reg;
34
35  MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
36  if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
37    if (CI->getValue().getActiveBits() > 64)
38      return TargetMaterializeConstant(CI,
39                                       MBB->getParent()->getConstantPool());
40    // Don't cache constant materializations.  To do so would require
41    // tracking what uses they dominate.
42    Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
43  } else if (isa<GlobalValue>(V)) {
44    return TargetMaterializeConstant(dyn_cast<Constant>(V),
45                                     MBB->getParent()->getConstantPool());
46  } else if (isa<ConstantPointerNull>(V)) {
47    Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
48  } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
49    Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
50
51    if (!Reg) {
52      const APFloat &Flt = CF->getValueAPF();
53      MVT IntVT = TLI.getPointerTy();
54
55      uint64_t x[2];
56      uint32_t IntBitWidth = IntVT.getSizeInBits();
57      if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
58                               APFloat::rmTowardZero) != APFloat::opOK)
59        return TargetMaterializeConstant(CF,
60                                         MBB->getParent()->getConstantPool());
61      APInt IntVal(IntBitWidth, 2, x);
62
63      unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
64                                       ISD::Constant, IntVal.getZExtValue());
65      if (IntegerReg == 0)
66        return TargetMaterializeConstant(CF,
67                                         MBB->getParent()->getConstantPool());
68      Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
69      if (Reg == 0)
70        return TargetMaterializeConstant(CF,
71                                         MBB->getParent()->getConstantPool());;
72    }
73  } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
74    if (!SelectOperator(CE, CE->getOpcode())) return 0;
75    Reg = LocalValueMap[CE];
76  } else if (isa<UndefValue>(V)) {
77    Reg = createResultReg(TLI.getRegClassFor(VT));
78    BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
79  } else {
80    return 0;
81  }
82
83  if (!Reg && isa<Constant>(V))
84    return TargetMaterializeConstant(cast<Constant>(V),
85                                     MBB->getParent()->getConstantPool());
86
87  LocalValueMap[V] = Reg;
88  return Reg;
89}
90
91unsigned FastISel::lookUpRegForValue(Value *V) {
92  // Look up the value to see if we already have a register for it. We
93  // cache values defined by Instructions across blocks, and other values
94  // only locally. This is because Instructions already have the SSA
95  // def-dominatess-use requirement enforced.
96  if (ValueMap.count(V))
97    return ValueMap[V];
98  return LocalValueMap[V];
99}
100
101/// UpdateValueMap - Update the value map to include the new mapping for this
102/// instruction, or insert an extra copy to get the result in a previous
103/// determined register.
104/// NOTE: This is only necessary because we might select a block that uses
105/// a value before we select the block that defines the value.  It might be
106/// possible to fix this by selecting blocks in reverse postorder.
107void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
108  if (!isa<Instruction>(I)) {
109    LocalValueMap[I] = Reg;
110    return;
111  }
112  if (!ValueMap.count(I))
113    ValueMap[I] = Reg;
114  else
115    TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
116                     Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
117}
118
119/// SelectBinaryOp - Select and emit code for a binary operator instruction,
120/// which has an opcode which directly corresponds to the given ISD opcode.
121///
122bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
123  MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
124  if (VT == MVT::Other || !VT.isSimple())
125    // Unhandled type. Halt "fast" selection and bail.
126    return false;
127
128  // We only handle legal types. For example, on x86-32 the instruction
129  // selector contains all of the 64-bit instructions from x86-64,
130  // under the assumption that i64 won't be used if the target doesn't
131  // support it.
132  if (!TLI.isTypeLegal(VT)) {
133    // MVT::i1 is special. Allow AND and OR (but not XOR) because they
134    // don't require additional zeroing, which makes them easy.
135    if (VT == MVT::i1 &&
136        (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR))
137      VT = TLI.getTypeToTransformTo(VT);
138    else
139      return false;
140  }
141
142  unsigned Op0 = getRegForValue(I->getOperand(0));
143  if (Op0 == 0)
144    // Unhandled operand. Halt "fast" selection and bail.
145    return false;
146
147  // Check if the second operand is a constant and handle it appropriately.
148  if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
149    unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
150                                     ISDOpcode, Op0, CI->getZExtValue());
151    if (ResultReg != 0) {
152      // We successfully emitted code for the given LLVM Instruction.
153      UpdateValueMap(I, ResultReg);
154      return true;
155    }
156  }
157
158  // Check if the second operand is a constant float.
159  if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
160    unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
161                                     ISDOpcode, Op0, CF);
162    if (ResultReg != 0) {
163      // We successfully emitted code for the given LLVM Instruction.
164      UpdateValueMap(I, ResultReg);
165      return true;
166    }
167  }
168
169  unsigned Op1 = getRegForValue(I->getOperand(1));
170  if (Op1 == 0)
171    // Unhandled operand. Halt "fast" selection and bail.
172    return false;
173
174  // Now we have both operands in registers. Emit the instruction.
175  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
176                                   ISDOpcode, Op0, Op1);
177  if (ResultReg == 0)
178    // Target-specific code wasn't able to find a machine opcode for
179    // the given ISD opcode and type. Halt "fast" selection and bail.
180    return false;
181
182  // We successfully emitted code for the given LLVM Instruction.
183  UpdateValueMap(I, ResultReg);
184  return true;
185}
186
187bool FastISel::SelectGetElementPtr(User *I) {
188  unsigned N = getRegForValue(I->getOperand(0));
189  if (N == 0)
190    // Unhandled operand. Halt "fast" selection and bail.
191    return false;
192
193  const Type *Ty = I->getOperand(0)->getType();
194  MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
195  for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
196       OI != E; ++OI) {
197    Value *Idx = *OI;
198    if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
199      unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
200      if (Field) {
201        // N = N + Offset
202        uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
203        // FIXME: This can be optimized by combining the add with a
204        // subsequent one.
205        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
206        if (N == 0)
207          // Unhandled operand. Halt "fast" selection and bail.
208          return false;
209      }
210      Ty = StTy->getElementType(Field);
211    } else {
212      Ty = cast<SequentialType>(Ty)->getElementType();
213
214      // If this is a constant subscript, handle it quickly.
215      if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
216        if (CI->getZExtValue() == 0) continue;
217        uint64_t Offs =
218          TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
219        N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
220        if (N == 0)
221          // Unhandled operand. Halt "fast" selection and bail.
222          return false;
223        continue;
224      }
225
226      // N = N + Idx * ElementSize;
227      uint64_t ElementSize = TD.getABITypeSize(Ty);
228      unsigned IdxN = getRegForValue(Idx);
229      if (IdxN == 0)
230        // Unhandled operand. Halt "fast" selection and bail.
231        return false;
232
233      // If the index is smaller or larger than intptr_t, truncate or extend
234      // it.
235      MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
236      if (IdxVT.bitsLT(VT))
237        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
238      else if (IdxVT.bitsGT(VT))
239        IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
240      if (IdxN == 0)
241        // Unhandled operand. Halt "fast" selection and bail.
242        return false;
243
244      if (ElementSize != 1) {
245        IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
246        if (IdxN == 0)
247          // Unhandled operand. Halt "fast" selection and bail.
248          return false;
249      }
250      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
251      if (N == 0)
252        // Unhandled operand. Halt "fast" selection and bail.
253        return false;
254    }
255  }
256
257  // We successfully emitted code for the given LLVM Instruction.
258  UpdateValueMap(I, N);
259  return true;
260}
261
262bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
263  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
264  MVT DstVT = TLI.getValueType(I->getType());
265
266  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
267      DstVT == MVT::Other || !DstVT.isSimple() ||
268      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
269    // Unhandled type. Halt "fast" selection and bail.
270    return false;
271
272  unsigned InputReg = getRegForValue(I->getOperand(0));
273  if (!InputReg)
274    // Unhandled operand.  Halt "fast" selection and bail.
275    return false;
276
277  unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
278                                  DstVT.getSimpleVT(),
279                                  Opcode,
280                                  InputReg);
281  if (!ResultReg)
282    return false;
283
284  UpdateValueMap(I, ResultReg);
285  return true;
286}
287
288bool FastISel::SelectBitCast(User *I) {
289  // If the bitcast doesn't change the type, just use the operand value.
290  if (I->getType() == I->getOperand(0)->getType()) {
291    unsigned Reg = getRegForValue(I->getOperand(0));
292    if (Reg == 0)
293      return false;
294    UpdateValueMap(I, Reg);
295    return true;
296  }
297
298  // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
299  MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
300  MVT DstVT = TLI.getValueType(I->getType());
301
302  if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
303      DstVT == MVT::Other || !DstVT.isSimple() ||
304      !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
305    // Unhandled type. Halt "fast" selection and bail.
306    return false;
307
308  unsigned Op0 = getRegForValue(I->getOperand(0));
309  if (Op0 == 0)
310    // Unhandled operand. Halt "fast" selection and bail.
311    return false;
312
313  // First, try to perform the bitcast by inserting a reg-reg copy.
314  unsigned ResultReg = 0;
315  if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
316    TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
317    TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
318    ResultReg = createResultReg(DstClass);
319
320    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
321                                         Op0, DstClass, SrcClass);
322    if (!InsertedCopy)
323      ResultReg = 0;
324  }
325
326  // If the reg-reg copy failed, select a BIT_CONVERT opcode.
327  if (!ResultReg)
328    ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
329                           ISD::BIT_CONVERT, Op0);
330
331  if (!ResultReg)
332    return false;
333
334  UpdateValueMap(I, ResultReg);
335  return true;
336}
337
338bool
339FastISel::SelectInstruction(Instruction *I) {
340  return SelectOperator(I, I->getOpcode());
341}
342
343bool
344FastISel::SelectOperator(User *I, unsigned Opcode) {
345  switch (Opcode) {
346  case Instruction::Add: {
347    ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
348    return SelectBinaryOp(I, Opc);
349  }
350  case Instruction::Sub: {
351    ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
352    return SelectBinaryOp(I, Opc);
353  }
354  case Instruction::Mul: {
355    ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
356    return SelectBinaryOp(I, Opc);
357  }
358  case Instruction::SDiv:
359    return SelectBinaryOp(I, ISD::SDIV);
360  case Instruction::UDiv:
361    return SelectBinaryOp(I, ISD::UDIV);
362  case Instruction::FDiv:
363    return SelectBinaryOp(I, ISD::FDIV);
364  case Instruction::SRem:
365    return SelectBinaryOp(I, ISD::SREM);
366  case Instruction::URem:
367    return SelectBinaryOp(I, ISD::UREM);
368  case Instruction::FRem:
369    return SelectBinaryOp(I, ISD::FREM);
370  case Instruction::Shl:
371    return SelectBinaryOp(I, ISD::SHL);
372  case Instruction::LShr:
373    return SelectBinaryOp(I, ISD::SRL);
374  case Instruction::AShr:
375    return SelectBinaryOp(I, ISD::SRA);
376  case Instruction::And:
377    return SelectBinaryOp(I, ISD::AND);
378  case Instruction::Or:
379    return SelectBinaryOp(I, ISD::OR);
380  case Instruction::Xor:
381    return SelectBinaryOp(I, ISD::XOR);
382
383  case Instruction::GetElementPtr:
384    return SelectGetElementPtr(I);
385
386  case Instruction::Br: {
387    BranchInst *BI = cast<BranchInst>(I);
388
389    if (BI->isUnconditional()) {
390      MachineFunction::iterator NextMBB =
391         next(MachineFunction::iterator(MBB));
392      BasicBlock *LLVMSucc = BI->getSuccessor(0);
393      MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
394
395      if (NextMBB != MF.end() && MSucc == NextMBB) {
396        // The unconditional fall-through case, which needs no instructions.
397      } else {
398        // The unconditional branch case.
399        TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
400      }
401      MBB->addSuccessor(MSucc);
402      return true;
403    }
404
405    // Conditional branches are not handed yet.
406    // Halt "fast" selection and bail.
407    return false;
408  }
409
410  case Instruction::Unreachable:
411    // Nothing to emit.
412    return true;
413
414  case Instruction::PHI:
415    // PHI nodes are already emitted.
416    return true;
417
418  case Instruction::BitCast:
419    return SelectBitCast(I);
420
421  case Instruction::FPToSI:
422    return SelectCast(I, ISD::FP_TO_SINT);
423  case Instruction::ZExt:
424    return SelectCast(I, ISD::ZERO_EXTEND);
425  case Instruction::SExt:
426    return SelectCast(I, ISD::SIGN_EXTEND);
427  case Instruction::Trunc:
428    return SelectCast(I, ISD::TRUNCATE);
429  case Instruction::SIToFP:
430    return SelectCast(I, ISD::SINT_TO_FP);
431
432  case Instruction::IntToPtr: // Deliberate fall-through.
433  case Instruction::PtrToInt: {
434    MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
435    MVT DstVT = TLI.getValueType(I->getType());
436    if (DstVT.bitsGT(SrcVT))
437      return SelectCast(I, ISD::ZERO_EXTEND);
438    if (DstVT.bitsLT(SrcVT))
439      return SelectCast(I, ISD::TRUNCATE);
440    unsigned Reg = getRegForValue(I->getOperand(0));
441    if (Reg == 0) return false;
442    UpdateValueMap(I, Reg);
443    return true;
444  }
445
446  default:
447    // Unhandled instruction. Halt "fast" selection and bail.
448    return false;
449  }
450}
451
452FastISel::FastISel(MachineFunction &mf,
453                   DenseMap<const Value *, unsigned> &vm,
454                   DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
455  : MBB(0),
456    ValueMap(vm),
457    MBBMap(bm),
458    MF(mf),
459    MRI(MF.getRegInfo()),
460    TM(MF.getTarget()),
461    TD(*TM.getTargetData()),
462    TII(*TM.getInstrInfo()),
463    TLI(*TM.getTargetLowering()) {
464}
465
466FastISel::~FastISel() {}
467
468unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
469                             ISD::NodeType) {
470  return 0;
471}
472
473unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
474                              ISD::NodeType, unsigned /*Op0*/) {
475  return 0;
476}
477
478unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
479                               ISD::NodeType, unsigned /*Op0*/,
480                               unsigned /*Op0*/) {
481  return 0;
482}
483
484unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
485                              ISD::NodeType, uint64_t /*Imm*/) {
486  return 0;
487}
488
489unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
490                              ISD::NodeType, ConstantFP * /*FPImm*/) {
491  return 0;
492}
493
494unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
495                               ISD::NodeType, unsigned /*Op0*/,
496                               uint64_t /*Imm*/) {
497  return 0;
498}
499
500unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
501                               ISD::NodeType, unsigned /*Op0*/,
502                               ConstantFP * /*FPImm*/) {
503  return 0;
504}
505
506unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
507                                ISD::NodeType,
508                                unsigned /*Op0*/, unsigned /*Op1*/,
509                                uint64_t /*Imm*/) {
510  return 0;
511}
512
513/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
514/// to emit an instruction with an immediate operand using FastEmit_ri.
515/// If that fails, it materializes the immediate into a register and try
516/// FastEmit_rr instead.
517unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
518                                unsigned Op0, uint64_t Imm,
519                                MVT::SimpleValueType ImmType) {
520  // First check if immediate type is legal. If not, we can't use the ri form.
521  unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
522  if (ResultReg != 0)
523    return ResultReg;
524  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
525  if (MaterialReg == 0)
526    return 0;
527  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
528}
529
530/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
531/// to emit an instruction with a floating-point immediate operand using
532/// FastEmit_rf. If that fails, it materializes the immediate into a register
533/// and try FastEmit_rr instead.
534unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
535                                unsigned Op0, ConstantFP *FPImm,
536                                MVT::SimpleValueType ImmType) {
537  // First check if immediate type is legal. If not, we can't use the rf form.
538  unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
539  if (ResultReg != 0)
540    return ResultReg;
541
542  // Materialize the constant in a register.
543  unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
544  if (MaterialReg == 0) {
545    // If the target doesn't have a way to directly enter a floating-point
546    // value into a register, use an alternate approach.
547    // TODO: The current approach only supports floating-point constants
548    // that can be constructed by conversion from integer values. This should
549    // be replaced by code that creates a load from a constant-pool entry,
550    // which will require some target-specific work.
551    const APFloat &Flt = FPImm->getValueAPF();
552    MVT IntVT = TLI.getPointerTy();
553
554    uint64_t x[2];
555    uint32_t IntBitWidth = IntVT.getSizeInBits();
556    if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
557                             APFloat::rmTowardZero) != APFloat::opOK)
558      return 0;
559    APInt IntVal(IntBitWidth, 2, x);
560
561    unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
562                                     ISD::Constant, IntVal.getZExtValue());
563    if (IntegerReg == 0)
564      return 0;
565    MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
566                             ISD::SINT_TO_FP, IntegerReg);
567    if (MaterialReg == 0)
568      return 0;
569  }
570  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
571}
572
573unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
574  return MRI.createVirtualRegister(RC);
575}
576
577unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
578                                 const TargetRegisterClass* RC) {
579  unsigned ResultReg = createResultReg(RC);
580  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
581
582  BuildMI(MBB, II, ResultReg);
583  return ResultReg;
584}
585
586unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
587                                  const TargetRegisterClass *RC,
588                                  unsigned Op0) {
589  unsigned ResultReg = createResultReg(RC);
590  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
591
592  if (II.getNumDefs() >= 1)
593    BuildMI(MBB, II, ResultReg).addReg(Op0);
594  else {
595    BuildMI(MBB, II).addReg(Op0);
596    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
597                                         II.ImplicitDefs[0], RC, RC);
598    if (!InsertedCopy)
599      ResultReg = 0;
600  }
601
602  return ResultReg;
603}
604
605unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
606                                   const TargetRegisterClass *RC,
607                                   unsigned Op0, unsigned Op1) {
608  unsigned ResultReg = createResultReg(RC);
609  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
610
611  if (II.getNumDefs() >= 1)
612    BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
613  else {
614    BuildMI(MBB, II).addReg(Op0).addReg(Op1);
615    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
616                                         II.ImplicitDefs[0], RC, RC);
617    if (!InsertedCopy)
618      ResultReg = 0;
619  }
620  return ResultReg;
621}
622
623unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
624                                   const TargetRegisterClass *RC,
625                                   unsigned Op0, uint64_t Imm) {
626  unsigned ResultReg = createResultReg(RC);
627  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
628
629  if (II.getNumDefs() >= 1)
630    BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
631  else {
632    BuildMI(MBB, II).addReg(Op0).addImm(Imm);
633    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
634                                         II.ImplicitDefs[0], RC, RC);
635    if (!InsertedCopy)
636      ResultReg = 0;
637  }
638  return ResultReg;
639}
640
641unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
642                                   const TargetRegisterClass *RC,
643                                   unsigned Op0, ConstantFP *FPImm) {
644  unsigned ResultReg = createResultReg(RC);
645  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
646
647  if (II.getNumDefs() >= 1)
648    BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
649  else {
650    BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
651    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
652                                         II.ImplicitDefs[0], RC, RC);
653    if (!InsertedCopy)
654      ResultReg = 0;
655  }
656  return ResultReg;
657}
658
659unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
660                                    const TargetRegisterClass *RC,
661                                    unsigned Op0, unsigned Op1, uint64_t Imm) {
662  unsigned ResultReg = createResultReg(RC);
663  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
664
665  if (II.getNumDefs() >= 1)
666    BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
667  else {
668    BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
669    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
670                                         II.ImplicitDefs[0], RC, RC);
671    if (!InsertedCopy)
672      ResultReg = 0;
673  }
674  return ResultReg;
675}
676
677unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
678                                  const TargetRegisterClass *RC,
679                                  uint64_t Imm) {
680  unsigned ResultReg = createResultReg(RC);
681  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
682
683  if (II.getNumDefs() >= 1)
684    BuildMI(MBB, II, ResultReg).addImm(Imm);
685  else {
686    BuildMI(MBB, II).addImm(Imm);
687    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
688                                         II.ImplicitDefs[0], RC, RC);
689    if (!InsertedCopy)
690      ResultReg = 0;
691  }
692  return ResultReg;
693}
694
695unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
696  const TargetRegisterClass* RC = MRI.getRegClass(Op0);
697  const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
698
699  unsigned ResultReg = createResultReg(SRC);
700  const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
701
702  if (II.getNumDefs() >= 1)
703    BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
704  else {
705    BuildMI(MBB, II).addReg(Op0).addImm(Idx);
706    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
707                                         II.ImplicitDefs[0], RC, RC);
708    if (!InsertedCopy)
709      ResultReg = 0;
710  }
711  return ResultReg;
712}
713