FastISel.cpp revision 4bafda9618f9dfa9edc8da08bb3001ef2d1a9b68
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/FunctionLoweringInfo.h" 48#include "llvm/CodeGen/MachineInstrBuilder.h" 49#include "llvm/CodeGen/MachineModuleInfo.h" 50#include "llvm/CodeGen/MachineRegisterInfo.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Analysis/Loads.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "llvm/Support/ErrorHandling.h" 58using namespace llvm; 59 60/// startNewBlock - Set the current block to which generated machine 61/// instructions will be appended, and clear the local CSE map. 62/// 63void FastISel::startNewBlock() { 64 LocalValueMap.clear(); 65 66 // Start out as null, meaining no local-value instructions have 67 // been emitted. 68 LastLocalValue = 0; 69 70 // Advance the last local value past any EH_LABEL instructions. 71 MachineBasicBlock::iterator 72 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end(); 73 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { 74 LastLocalValue = I; 75 ++I; 76 } 77} 78 79bool FastISel::hasTrivialKill(const Value *V) const { 80 // Don't consider constants or arguments to have trivial kills. 81 const Instruction *I = dyn_cast<Instruction>(V); 82 if (!I) 83 return false; 84 85 // No-op casts are trivially coalesced by fast-isel. 86 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 87 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 88 !hasTrivialKill(Cast->getOperand(0))) 89 return false; 90 91 // Only instructions with a single use in the same basic block are considered 92 // to have trivial kills. 93 return I->hasOneUse() && 94 !(I->getOpcode() == Instruction::BitCast || 95 I->getOpcode() == Instruction::PtrToInt || 96 I->getOpcode() == Instruction::IntToPtr) && 97 cast<Instruction>(*I->use_begin())->getParent() == I->getParent(); 98} 99 100unsigned FastISel::getRegForValue(const Value *V) { 101 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 102 // Don't handle non-simple values in FastISel. 103 if (!RealVT.isSimple()) 104 return 0; 105 106 // Ignore illegal types. We must do this before looking up the value 107 // in ValueMap because Arguments are given virtual registers regardless 108 // of whether FastISel can handle them. 109 MVT VT = RealVT.getSimpleVT(); 110 if (!TLI.isTypeLegal(VT)) { 111 // Promote MVT::i1 to a legal type though, because it's common and easy. 112 if (VT == MVT::i1) 113 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 114 else 115 return 0; 116 } 117 118 // Look up the value to see if we already have a register for it. We 119 // cache values defined by Instructions across blocks, and other values 120 // only locally. This is because Instructions already have the SSA 121 // def-dominates-use requirement enforced. 122 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 123 if (I != FuncInfo.ValueMap.end()) { 124 unsigned Reg = I->second; 125 return Reg; 126 } 127 unsigned Reg = LocalValueMap[V]; 128 if (Reg != 0) 129 return Reg; 130 131 // In bottom-up mode, just create the virtual register which will be used 132 // to hold the value. It will be materialized later. 133 if (isa<Instruction>(V) && 134 (!isa<AllocaInst>(V) || 135 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) 136 return FuncInfo.InitializeRegForValue(V); 137 138 SavePoint SaveInsertPt = enterLocalValueArea(); 139 140 // Materialize the value in a register. Emit any instructions in the 141 // local value area. 142 Reg = materializeRegForValue(V, VT); 143 144 leaveLocalValueArea(SaveInsertPt); 145 146 return Reg; 147} 148 149/// materializeRegForValue - Helper for getRegForValue. This function is 150/// called when the value isn't already available in a register and must 151/// be materialized with new instructions. 152unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 153 unsigned Reg = 0; 154 155 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 156 if (CI->getValue().getActiveBits() <= 64) 157 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 158 } else if (isa<AllocaInst>(V)) { 159 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 160 } else if (isa<ConstantPointerNull>(V)) { 161 // Translate this as an integer zero so that it can be 162 // local-CSE'd with actual integer zeros. 163 Reg = 164 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 165 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 166 // Try to emit the constant directly. 167 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 168 169 if (!Reg) { 170 // Try to emit the constant by using an integer constant with a cast. 171 const APFloat &Flt = CF->getValueAPF(); 172 EVT IntVT = TLI.getPointerTy(); 173 174 uint64_t x[2]; 175 uint32_t IntBitWidth = IntVT.getSizeInBits(); 176 bool isExact; 177 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 178 APFloat::rmTowardZero, &isExact); 179 if (isExact) { 180 APInt IntVal(IntBitWidth, 2, x); 181 182 unsigned IntegerReg = 183 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 184 if (IntegerReg != 0) 185 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 186 IntegerReg, /*Kill=*/false); 187 } 188 } 189 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 190 if (!SelectOperator(Op, Op->getOpcode())) 191 if (!isa<Instruction>(Op) || 192 !TargetSelectInstruction(cast<Instruction>(Op))) 193 return 0; 194 Reg = lookUpRegForValue(Op); 195 } else if (isa<UndefValue>(V)) { 196 Reg = createResultReg(TLI.getRegClassFor(VT)); 197 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 198 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 199 } 200 201 // If target-independent code couldn't handle the value, give target-specific 202 // code a try. 203 if (!Reg && isa<Constant>(V)) 204 Reg = TargetMaterializeConstant(cast<Constant>(V)); 205 206 // Don't cache constant materializations in the general ValueMap. 207 // To do so would require tracking what uses they dominate. 208 if (Reg != 0) { 209 LocalValueMap[V] = Reg; 210 LastLocalValue = MRI.getVRegDef(Reg); 211 } 212 return Reg; 213} 214 215unsigned FastISel::lookUpRegForValue(const Value *V) { 216 // Look up the value to see if we already have a register for it. We 217 // cache values defined by Instructions across blocks, and other values 218 // only locally. This is because Instructions already have the SSA 219 // def-dominates-use requirement enforced. 220 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 221 if (I != FuncInfo.ValueMap.end()) 222 return I->second; 223 return LocalValueMap[V]; 224} 225 226/// UpdateValueMap - Update the value map to include the new mapping for this 227/// instruction, or insert an extra copy to get the result in a previous 228/// determined register. 229/// NOTE: This is only necessary because we might select a block that uses 230/// a value before we select the block that defines the value. It might be 231/// possible to fix this by selecting blocks in reverse postorder. 232unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) { 233 if (!isa<Instruction>(I)) { 234 LocalValueMap[I] = Reg; 235 return Reg; 236 } 237 238 unsigned &AssignedReg = FuncInfo.ValueMap[I]; 239 if (AssignedReg == 0) 240 // Use the new register. 241 AssignedReg = Reg; 242 else if (Reg != AssignedReg) { 243 // Arrange for uses of AssignedReg to be replaced by uses of Reg. 244 FuncInfo.RegFixups[AssignedReg] = Reg; 245 246 AssignedReg = Reg; 247 } 248 249 return AssignedReg; 250} 251 252std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 253 unsigned IdxN = getRegForValue(Idx); 254 if (IdxN == 0) 255 // Unhandled operand. Halt "fast" selection and bail. 256 return std::pair<unsigned, bool>(0, false); 257 258 bool IdxNIsKill = hasTrivialKill(Idx); 259 260 // If the index is smaller or larger than intptr_t, truncate or extend it. 261 MVT PtrVT = TLI.getPointerTy(); 262 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 263 if (IdxVT.bitsLT(PtrVT)) { 264 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 265 IdxN, IdxNIsKill); 266 IdxNIsKill = true; 267 } 268 else if (IdxVT.bitsGT(PtrVT)) { 269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 270 IdxN, IdxNIsKill); 271 IdxNIsKill = true; 272 } 273 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 274} 275 276void FastISel::recomputeInsertPt() { 277 if (getLastLocalValue()) { 278 FuncInfo.InsertPt = getLastLocalValue(); 279 FuncInfo.MBB = FuncInfo.InsertPt->getParent(); 280 ++FuncInfo.InsertPt; 281 } else 282 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI(); 283 284 // Now skip past any EH_LABELs, which must remain at the beginning. 285 while (FuncInfo.InsertPt != FuncInfo.MBB->end() && 286 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 287 ++FuncInfo.InsertPt; 288} 289 290FastISel::SavePoint FastISel::enterLocalValueArea() { 291 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; 292 DebugLoc OldDL = DL; 293 recomputeInsertPt(); 294 DL = DebugLoc(); 295 SavePoint SP = { OldInsertPt, OldDL }; 296 return SP; 297} 298 299void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { 300 if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) 301 LastLocalValue = llvm::prior(FuncInfo.InsertPt); 302 303 // Restore the previous insert position. 304 FuncInfo.InsertPt = OldInsertPt.InsertPt; 305 DL = OldInsertPt.DL; 306} 307 308/// SelectBinaryOp - Select and emit code for a binary operator instruction, 309/// which has an opcode which directly corresponds to the given ISD opcode. 310/// 311bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 312 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 313 if (VT == MVT::Other || !VT.isSimple()) 314 // Unhandled type. Halt "fast" selection and bail. 315 return false; 316 317 // We only handle legal types. For example, on x86-32 the instruction 318 // selector contains all of the 64-bit instructions from x86-64, 319 // under the assumption that i64 won't be used if the target doesn't 320 // support it. 321 if (!TLI.isTypeLegal(VT)) { 322 // MVT::i1 is special. Allow AND, OR, or XOR because they 323 // don't require additional zeroing, which makes them easy. 324 if (VT == MVT::i1 && 325 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 326 ISDOpcode == ISD::XOR)) 327 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 328 else 329 return false; 330 } 331 332 unsigned Op0 = getRegForValue(I->getOperand(0)); 333 if (Op0 == 0) 334 // Unhandled operand. Halt "fast" selection and bail. 335 return false; 336 337 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 338 339 // Check if the second operand is a constant and handle it appropriately. 340 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 341 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 342 ISDOpcode, Op0, Op0IsKill, 343 CI->getZExtValue()); 344 if (ResultReg != 0) { 345 // We successfully emitted code for the given LLVM Instruction. 346 UpdateValueMap(I, ResultReg); 347 return true; 348 } 349 } 350 351 // Check if the second operand is a constant float. 352 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 353 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 354 ISDOpcode, Op0, Op0IsKill, CF); 355 if (ResultReg != 0) { 356 // We successfully emitted code for the given LLVM Instruction. 357 UpdateValueMap(I, ResultReg); 358 return true; 359 } 360 } 361 362 unsigned Op1 = getRegForValue(I->getOperand(1)); 363 if (Op1 == 0) 364 // Unhandled operand. Halt "fast" selection and bail. 365 return false; 366 367 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 368 369 // Now we have both operands in registers. Emit the instruction. 370 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 371 ISDOpcode, 372 Op0, Op0IsKill, 373 Op1, Op1IsKill); 374 if (ResultReg == 0) 375 // Target-specific code wasn't able to find a machine opcode for 376 // the given ISD opcode and type. Halt "fast" selection and bail. 377 return false; 378 379 // We successfully emitted code for the given LLVM Instruction. 380 UpdateValueMap(I, ResultReg); 381 return true; 382} 383 384bool FastISel::SelectGetElementPtr(const User *I) { 385 unsigned N = getRegForValue(I->getOperand(0)); 386 if (N == 0) 387 // Unhandled operand. Halt "fast" selection and bail. 388 return false; 389 390 bool NIsKill = hasTrivialKill(I->getOperand(0)); 391 392 const Type *Ty = I->getOperand(0)->getType(); 393 MVT VT = TLI.getPointerTy(); 394 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 395 E = I->op_end(); OI != E; ++OI) { 396 const Value *Idx = *OI; 397 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 398 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 399 if (Field) { 400 // N = N + Offset 401 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 402 // FIXME: This can be optimized by combining the add with a 403 // subsequent one. 404 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 405 if (N == 0) 406 // Unhandled operand. Halt "fast" selection and bail. 407 return false; 408 NIsKill = true; 409 } 410 Ty = StTy->getElementType(Field); 411 } else { 412 Ty = cast<SequentialType>(Ty)->getElementType(); 413 414 // If this is a constant subscript, handle it quickly. 415 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 416 if (CI->isZero()) continue; 417 uint64_t Offs = 418 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 419 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 420 if (N == 0) 421 // Unhandled operand. Halt "fast" selection and bail. 422 return false; 423 NIsKill = true; 424 continue; 425 } 426 427 // N = N + Idx * ElementSize; 428 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 429 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 430 unsigned IdxN = Pair.first; 431 bool IdxNIsKill = Pair.second; 432 if (IdxN == 0) 433 // Unhandled operand. Halt "fast" selection and bail. 434 return false; 435 436 if (ElementSize != 1) { 437 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 438 if (IdxN == 0) 439 // Unhandled operand. Halt "fast" selection and bail. 440 return false; 441 IdxNIsKill = true; 442 } 443 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 444 if (N == 0) 445 // Unhandled operand. Halt "fast" selection and bail. 446 return false; 447 } 448 } 449 450 // We successfully emitted code for the given LLVM Instruction. 451 UpdateValueMap(I, N); 452 return true; 453} 454 455bool FastISel::SelectCall(const User *I) { 456 const Function *F = cast<CallInst>(I)->getCalledFunction(); 457 if (!F) return false; 458 459 // Handle selected intrinsic function calls. 460 unsigned IID = F->getIntrinsicID(); 461 switch (IID) { 462 default: break; 463 case Intrinsic::dbg_declare: { 464 const DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 465 if (!DIVariable(DI->getVariable()).Verify() || 466 !FuncInfo.MF->getMMI().hasDebugInfo()) 467 return true; 468 469 const Value *Address = DI->getAddress(); 470 if (!Address) 471 return true; 472 if (isa<UndefValue>(Address)) 473 return true; 474 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 475 // Don't handle byval struct arguments or VLAs, for example. 476 if (!AI) { 477 // Building the map above is target independent. Generating DBG_VALUE 478 // inline is target dependent; do this now. 479 DenseMap<const Value *, unsigned>::iterator It = 480 FuncInfo.ValueMap.find(Address); 481 if (0 && It != FuncInfo.ValueMap.end()) { 482 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 483 TII.get(TargetOpcode::DBG_VALUE)) 484 .addReg(It->second, RegState::Debug).addImm(0).addMetadata(DI->getVariable()); 485 } else 486 (void)TargetSelectInstruction(cast<Instruction>(I)); 487 } 488 return true; 489 } 490 case Intrinsic::dbg_value: { 491 // This form of DBG_VALUE is target-independent. 492 const DbgValueInst *DI = cast<DbgValueInst>(I); 493 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 494 const Value *V = DI->getValue(); 495 if (!V) { 496 // Currently the optimizer can produce this; insert an undef to 497 // help debugging. Probably the optimizer should not do this. 498 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 499 .addReg(0U).addImm(DI->getOffset()) 500 .addMetadata(DI->getVariable()); 501 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 503 .addImm(CI->getZExtValue()).addImm(DI->getOffset()) 504 .addMetadata(DI->getVariable()); 505 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 507 .addFPImm(CF).addImm(DI->getOffset()) 508 .addMetadata(DI->getVariable()); 509 } else if (unsigned Reg = lookUpRegForValue(V)) { 510 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 511 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 512 .addMetadata(DI->getVariable()); 513 } else { 514 // We can't yet handle anything else here because it would require 515 // generating code, thus altering codegen because of debug info. 516 // Insert an undef so we can see what we dropped. 517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 518 .addReg(0U).addImm(DI->getOffset()) 519 .addMetadata(DI->getVariable()); 520 } 521 return true; 522 } 523 case Intrinsic::eh_exception: { 524 EVT VT = TLI.getValueType(I->getType()); 525 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 526 default: break; 527 case TargetLowering::Expand: { 528 assert(FuncInfo.MBB->isLandingPad() && 529 "Call to eh.exception not in landing pad!"); 530 unsigned Reg = TLI.getExceptionAddressRegister(); 531 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 532 unsigned ResultReg = createResultReg(RC); 533 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 534 ResultReg).addReg(Reg); 535 UpdateValueMap(I, ResultReg); 536 return true; 537 } 538 } 539 break; 540 } 541 case Intrinsic::eh_selector: { 542 EVT VT = TLI.getValueType(I->getType()); 543 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 544 default: break; 545 case TargetLowering::Expand: { 546 if (FuncInfo.MBB->isLandingPad()) 547 AddCatchInfo(*cast<CallInst>(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB); 548 else { 549#ifndef NDEBUG 550 FuncInfo.CatchInfoLost.insert(cast<CallInst>(I)); 551#endif 552 // FIXME: Mark exception selector register as live in. Hack for PR1508. 553 unsigned Reg = TLI.getExceptionSelectorRegister(); 554 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 555 } 556 557 unsigned Reg = TLI.getExceptionSelectorRegister(); 558 EVT SrcVT = TLI.getPointerTy(); 559 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 560 unsigned ResultReg = createResultReg(RC); 561 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 562 ResultReg).addReg(Reg); 563 564 bool ResultRegIsKill = hasTrivialKill(I); 565 566 // Cast the register to the type of the selector. 567 if (SrcVT.bitsGT(MVT::i32)) 568 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 569 ResultReg, ResultRegIsKill); 570 else if (SrcVT.bitsLT(MVT::i32)) 571 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 572 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); 573 if (ResultReg == 0) 574 // Unhandled operand. Halt "fast" selection and bail. 575 return false; 576 577 UpdateValueMap(I, ResultReg); 578 579 return true; 580 } 581 } 582 break; 583 } 584 } 585 586 // An arbitrary call. Bail. 587 return false; 588} 589 590bool FastISel::SelectCast(const User *I, unsigned Opcode) { 591 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 592 EVT DstVT = TLI.getValueType(I->getType()); 593 594 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 595 DstVT == MVT::Other || !DstVT.isSimple()) 596 // Unhandled type. Halt "fast" selection and bail. 597 return false; 598 599 // Check if the destination type is legal. Or as a special case, 600 // it may be i1 if we're doing a truncate because that's 601 // easy and somewhat common. 602 if (!TLI.isTypeLegal(DstVT)) 603 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 604 // Unhandled type. Halt "fast" selection and bail. 605 return false; 606 607 // Check if the source operand is legal. Or as a special case, 608 // it may be i1 if we're doing zero-extension because that's 609 // easy and somewhat common. 610 if (!TLI.isTypeLegal(SrcVT)) 611 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 612 // Unhandled type. Halt "fast" selection and bail. 613 return false; 614 615 unsigned InputReg = getRegForValue(I->getOperand(0)); 616 if (!InputReg) 617 // Unhandled operand. Halt "fast" selection and bail. 618 return false; 619 620 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 621 622 // If the operand is i1, arrange for the high bits in the register to be zero. 623 if (SrcVT == MVT::i1) { 624 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 625 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg, InputRegIsKill); 626 if (!InputReg) 627 return false; 628 InputRegIsKill = true; 629 } 630 // If the result is i1, truncate to the target's type for i1 first. 631 if (DstVT == MVT::i1) 632 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 633 634 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 635 DstVT.getSimpleVT(), 636 Opcode, 637 InputReg, InputRegIsKill); 638 if (!ResultReg) 639 return false; 640 641 UpdateValueMap(I, ResultReg); 642 return true; 643} 644 645bool FastISel::SelectBitCast(const User *I) { 646 // If the bitcast doesn't change the type, just use the operand value. 647 if (I->getType() == I->getOperand(0)->getType()) { 648 unsigned Reg = getRegForValue(I->getOperand(0)); 649 if (Reg == 0) 650 return false; 651 UpdateValueMap(I, Reg); 652 return true; 653 } 654 655 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 656 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 657 EVT DstVT = TLI.getValueType(I->getType()); 658 659 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 660 DstVT == MVT::Other || !DstVT.isSimple() || 661 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 662 // Unhandled type. Halt "fast" selection and bail. 663 return false; 664 665 unsigned Op0 = getRegForValue(I->getOperand(0)); 666 if (Op0 == 0) 667 // Unhandled operand. Halt "fast" selection and bail. 668 return false; 669 670 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 671 672 // First, try to perform the bitcast by inserting a reg-reg copy. 673 unsigned ResultReg = 0; 674 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 675 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 676 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 677 // Don't attempt a cross-class copy. It will likely fail. 678 if (SrcClass == DstClass) { 679 ResultReg = createResultReg(DstClass); 680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 681 ResultReg).addReg(Op0); 682 } 683 } 684 685 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 686 if (!ResultReg) 687 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 688 ISD::BIT_CONVERT, Op0, Op0IsKill); 689 690 if (!ResultReg) 691 return false; 692 693 UpdateValueMap(I, ResultReg); 694 return true; 695} 696 697bool 698FastISel::SelectInstruction(const Instruction *I) { 699 // Just before the terminator instruction, insert instructions to 700 // feed PHI nodes in successor blocks. 701 if (isa<TerminatorInst>(I)) 702 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 703 return false; 704 705 DL = I->getDebugLoc(); 706 707 // First, try doing target-independent selection. 708 if (SelectOperator(I, I->getOpcode())) { 709 DL = DebugLoc(); 710 return true; 711 } 712 713 // Next, try calling the target to attempt to handle the instruction. 714 if (TargetSelectInstruction(I)) { 715 DL = DebugLoc(); 716 return true; 717 } 718 719 DL = DebugLoc(); 720 return false; 721} 722 723/// FastEmitBranch - Emit an unconditional branch to the given block, 724/// unless it is the immediate (fall-through) successor, and update 725/// the CFG. 726void 727FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 728 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) { 729 // The unconditional fall-through case, which needs no instructions. 730 } else { 731 // The unconditional branch case. 732 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 733 SmallVector<MachineOperand, 0>(), DL); 734 } 735 FuncInfo.MBB->addSuccessor(MSucc); 736} 737 738/// SelectFNeg - Emit an FNeg operation. 739/// 740bool 741FastISel::SelectFNeg(const User *I) { 742 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 743 if (OpReg == 0) return false; 744 745 bool OpRegIsKill = hasTrivialKill(I); 746 747 // If the target has ISD::FNEG, use it. 748 EVT VT = TLI.getValueType(I->getType()); 749 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 750 ISD::FNEG, OpReg, OpRegIsKill); 751 if (ResultReg != 0) { 752 UpdateValueMap(I, ResultReg); 753 return true; 754 } 755 756 // Bitcast the value to integer, twiddle the sign bit with xor, 757 // and then bitcast it back to floating-point. 758 if (VT.getSizeInBits() > 64) return false; 759 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 760 if (!TLI.isTypeLegal(IntVT)) 761 return false; 762 763 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 764 ISD::BIT_CONVERT, OpReg, OpRegIsKill); 765 if (IntReg == 0) 766 return false; 767 768 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 769 IntReg, /*Kill=*/true, 770 UINT64_C(1) << (VT.getSizeInBits()-1), 771 IntVT.getSimpleVT()); 772 if (IntResultReg == 0) 773 return false; 774 775 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 776 ISD::BIT_CONVERT, IntResultReg, /*Kill=*/true); 777 if (ResultReg == 0) 778 return false; 779 780 UpdateValueMap(I, ResultReg); 781 return true; 782} 783 784bool 785FastISel::SelectOperator(const User *I, unsigned Opcode) { 786 switch (Opcode) { 787 case Instruction::Add: 788 return SelectBinaryOp(I, ISD::ADD); 789 case Instruction::FAdd: 790 return SelectBinaryOp(I, ISD::FADD); 791 case Instruction::Sub: 792 return SelectBinaryOp(I, ISD::SUB); 793 case Instruction::FSub: 794 // FNeg is currently represented in LLVM IR as a special case of FSub. 795 if (BinaryOperator::isFNeg(I)) 796 return SelectFNeg(I); 797 return SelectBinaryOp(I, ISD::FSUB); 798 case Instruction::Mul: 799 return SelectBinaryOp(I, ISD::MUL); 800 case Instruction::FMul: 801 return SelectBinaryOp(I, ISD::FMUL); 802 case Instruction::SDiv: 803 return SelectBinaryOp(I, ISD::SDIV); 804 case Instruction::UDiv: 805 return SelectBinaryOp(I, ISD::UDIV); 806 case Instruction::FDiv: 807 return SelectBinaryOp(I, ISD::FDIV); 808 case Instruction::SRem: 809 return SelectBinaryOp(I, ISD::SREM); 810 case Instruction::URem: 811 return SelectBinaryOp(I, ISD::UREM); 812 case Instruction::FRem: 813 return SelectBinaryOp(I, ISD::FREM); 814 case Instruction::Shl: 815 return SelectBinaryOp(I, ISD::SHL); 816 case Instruction::LShr: 817 return SelectBinaryOp(I, ISD::SRL); 818 case Instruction::AShr: 819 return SelectBinaryOp(I, ISD::SRA); 820 case Instruction::And: 821 return SelectBinaryOp(I, ISD::AND); 822 case Instruction::Or: 823 return SelectBinaryOp(I, ISD::OR); 824 case Instruction::Xor: 825 return SelectBinaryOp(I, ISD::XOR); 826 827 case Instruction::GetElementPtr: 828 return SelectGetElementPtr(I); 829 830 case Instruction::Br: { 831 const BranchInst *BI = cast<BranchInst>(I); 832 833 if (BI->isUnconditional()) { 834 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 835 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc]; 836 FastEmitBranch(MSucc, BI->getDebugLoc()); 837 return true; 838 } 839 840 // Conditional branches are not handed yet. 841 // Halt "fast" selection and bail. 842 return false; 843 } 844 845 case Instruction::Unreachable: 846 // Nothing to emit. 847 return true; 848 849 case Instruction::Alloca: 850 // FunctionLowering has the static-sized case covered. 851 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I))) 852 return true; 853 854 // Dynamic-sized alloca is not handled yet. 855 return false; 856 857 case Instruction::Call: 858 return SelectCall(I); 859 860 case Instruction::BitCast: 861 return SelectBitCast(I); 862 863 case Instruction::FPToSI: 864 return SelectCast(I, ISD::FP_TO_SINT); 865 case Instruction::ZExt: 866 return SelectCast(I, ISD::ZERO_EXTEND); 867 case Instruction::SExt: 868 return SelectCast(I, ISD::SIGN_EXTEND); 869 case Instruction::Trunc: 870 return SelectCast(I, ISD::TRUNCATE); 871 case Instruction::SIToFP: 872 return SelectCast(I, ISD::SINT_TO_FP); 873 874 case Instruction::IntToPtr: // Deliberate fall-through. 875 case Instruction::PtrToInt: { 876 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 877 EVT DstVT = TLI.getValueType(I->getType()); 878 if (DstVT.bitsGT(SrcVT)) 879 return SelectCast(I, ISD::ZERO_EXTEND); 880 if (DstVT.bitsLT(SrcVT)) 881 return SelectCast(I, ISD::TRUNCATE); 882 unsigned Reg = getRegForValue(I->getOperand(0)); 883 if (Reg == 0) return false; 884 UpdateValueMap(I, Reg); 885 return true; 886 } 887 888 case Instruction::PHI: 889 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 890 891 default: 892 // Unhandled instruction. Halt "fast" selection and bail. 893 return false; 894 } 895} 896 897FastISel::FastISel(FunctionLoweringInfo &funcInfo) 898 : FuncInfo(funcInfo), 899 MRI(FuncInfo.MF->getRegInfo()), 900 MFI(*FuncInfo.MF->getFrameInfo()), 901 MCP(*FuncInfo.MF->getConstantPool()), 902 TM(FuncInfo.MF->getTarget()), 903 TD(*TM.getTargetData()), 904 TII(*TM.getInstrInfo()), 905 TLI(*TM.getTargetLowering()), 906 TRI(*TM.getRegisterInfo()) { 907} 908 909FastISel::~FastISel() {} 910 911unsigned FastISel::FastEmit_(MVT, MVT, 912 unsigned) { 913 return 0; 914} 915 916unsigned FastISel::FastEmit_r(MVT, MVT, 917 unsigned, 918 unsigned /*Op0*/, bool /*Op0IsKill*/) { 919 return 0; 920} 921 922unsigned FastISel::FastEmit_rr(MVT, MVT, 923 unsigned, 924 unsigned /*Op0*/, bool /*Op0IsKill*/, 925 unsigned /*Op1*/, bool /*Op1IsKill*/) { 926 return 0; 927} 928 929unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 930 return 0; 931} 932 933unsigned FastISel::FastEmit_f(MVT, MVT, 934 unsigned, const ConstantFP * /*FPImm*/) { 935 return 0; 936} 937 938unsigned FastISel::FastEmit_ri(MVT, MVT, 939 unsigned, 940 unsigned /*Op0*/, bool /*Op0IsKill*/, 941 uint64_t /*Imm*/) { 942 return 0; 943} 944 945unsigned FastISel::FastEmit_rf(MVT, MVT, 946 unsigned, 947 unsigned /*Op0*/, bool /*Op0IsKill*/, 948 const ConstantFP * /*FPImm*/) { 949 return 0; 950} 951 952unsigned FastISel::FastEmit_rri(MVT, MVT, 953 unsigned, 954 unsigned /*Op0*/, bool /*Op0IsKill*/, 955 unsigned /*Op1*/, bool /*Op1IsKill*/, 956 uint64_t /*Imm*/) { 957 return 0; 958} 959 960/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 961/// to emit an instruction with an immediate operand using FastEmit_ri. 962/// If that fails, it materializes the immediate into a register and try 963/// FastEmit_rr instead. 964unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 965 unsigned Op0, bool Op0IsKill, 966 uint64_t Imm, MVT ImmType) { 967 // First check if immediate type is legal. If not, we can't use the ri form. 968 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 969 if (ResultReg != 0) 970 return ResultReg; 971 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 972 if (MaterialReg == 0) 973 return 0; 974 return FastEmit_rr(VT, VT, Opcode, 975 Op0, Op0IsKill, 976 MaterialReg, /*Kill=*/true); 977} 978 979/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 980/// to emit an instruction with a floating-point immediate operand using 981/// FastEmit_rf. If that fails, it materializes the immediate into a register 982/// and try FastEmit_rr instead. 983unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 984 unsigned Op0, bool Op0IsKill, 985 const ConstantFP *FPImm, MVT ImmType) { 986 // First check if immediate type is legal. If not, we can't use the rf form. 987 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, Op0IsKill, FPImm); 988 if (ResultReg != 0) 989 return ResultReg; 990 991 // Materialize the constant in a register. 992 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 993 if (MaterialReg == 0) { 994 // If the target doesn't have a way to directly enter a floating-point 995 // value into a register, use an alternate approach. 996 // TODO: The current approach only supports floating-point constants 997 // that can be constructed by conversion from integer values. This should 998 // be replaced by code that creates a load from a constant-pool entry, 999 // which will require some target-specific work. 1000 const APFloat &Flt = FPImm->getValueAPF(); 1001 EVT IntVT = TLI.getPointerTy(); 1002 1003 uint64_t x[2]; 1004 uint32_t IntBitWidth = IntVT.getSizeInBits(); 1005 bool isExact; 1006 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 1007 APFloat::rmTowardZero, &isExact); 1008 if (!isExact) 1009 return 0; 1010 APInt IntVal(IntBitWidth, 2, x); 1011 1012 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 1013 ISD::Constant, IntVal.getZExtValue()); 1014 if (IntegerReg == 0) 1015 return 0; 1016 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 1017 ISD::SINT_TO_FP, IntegerReg, /*Kill=*/true); 1018 if (MaterialReg == 0) 1019 return 0; 1020 } 1021 return FastEmit_rr(VT, VT, Opcode, 1022 Op0, Op0IsKill, 1023 MaterialReg, /*Kill=*/true); 1024} 1025 1026unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 1027 return MRI.createVirtualRegister(RC); 1028} 1029 1030unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 1031 const TargetRegisterClass* RC) { 1032 unsigned ResultReg = createResultReg(RC); 1033 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1034 1035 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); 1036 return ResultReg; 1037} 1038 1039unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 1040 const TargetRegisterClass *RC, 1041 unsigned Op0, bool Op0IsKill) { 1042 unsigned ResultReg = createResultReg(RC); 1043 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1044 1045 if (II.getNumDefs() >= 1) 1046 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1047 .addReg(Op0, Op0IsKill * RegState::Kill); 1048 else { 1049 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1050 .addReg(Op0, Op0IsKill * RegState::Kill); 1051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1052 ResultReg).addReg(II.ImplicitDefs[0]); 1053 } 1054 1055 return ResultReg; 1056} 1057 1058unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1059 const TargetRegisterClass *RC, 1060 unsigned Op0, bool Op0IsKill, 1061 unsigned Op1, bool Op1IsKill) { 1062 unsigned ResultReg = createResultReg(RC); 1063 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1064 1065 if (II.getNumDefs() >= 1) 1066 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1067 .addReg(Op0, Op0IsKill * RegState::Kill) 1068 .addReg(Op1, Op1IsKill * RegState::Kill); 1069 else { 1070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1071 .addReg(Op0, Op0IsKill * RegState::Kill) 1072 .addReg(Op1, Op1IsKill * RegState::Kill); 1073 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1074 ResultReg).addReg(II.ImplicitDefs[0]); 1075 } 1076 return ResultReg; 1077} 1078 1079unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1080 const TargetRegisterClass *RC, 1081 unsigned Op0, bool Op0IsKill, 1082 uint64_t Imm) { 1083 unsigned ResultReg = createResultReg(RC); 1084 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1085 1086 if (II.getNumDefs() >= 1) 1087 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1088 .addReg(Op0, Op0IsKill * RegState::Kill) 1089 .addImm(Imm); 1090 else { 1091 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1092 .addReg(Op0, Op0IsKill * RegState::Kill) 1093 .addImm(Imm); 1094 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1095 ResultReg).addReg(II.ImplicitDefs[0]); 1096 } 1097 return ResultReg; 1098} 1099 1100unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1101 const TargetRegisterClass *RC, 1102 unsigned Op0, bool Op0IsKill, 1103 const ConstantFP *FPImm) { 1104 unsigned ResultReg = createResultReg(RC); 1105 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1106 1107 if (II.getNumDefs() >= 1) 1108 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1109 .addReg(Op0, Op0IsKill * RegState::Kill) 1110 .addFPImm(FPImm); 1111 else { 1112 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1113 .addReg(Op0, Op0IsKill * RegState::Kill) 1114 .addFPImm(FPImm); 1115 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1116 ResultReg).addReg(II.ImplicitDefs[0]); 1117 } 1118 return ResultReg; 1119} 1120 1121unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1122 const TargetRegisterClass *RC, 1123 unsigned Op0, bool Op0IsKill, 1124 unsigned Op1, bool Op1IsKill, 1125 uint64_t Imm) { 1126 unsigned ResultReg = createResultReg(RC); 1127 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1128 1129 if (II.getNumDefs() >= 1) 1130 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1131 .addReg(Op0, Op0IsKill * RegState::Kill) 1132 .addReg(Op1, Op1IsKill * RegState::Kill) 1133 .addImm(Imm); 1134 else { 1135 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1136 .addReg(Op0, Op0IsKill * RegState::Kill) 1137 .addReg(Op1, Op1IsKill * RegState::Kill) 1138 .addImm(Imm); 1139 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1140 ResultReg).addReg(II.ImplicitDefs[0]); 1141 } 1142 return ResultReg; 1143} 1144 1145unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1146 const TargetRegisterClass *RC, 1147 uint64_t Imm) { 1148 unsigned ResultReg = createResultReg(RC); 1149 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1150 1151 if (II.getNumDefs() >= 1) 1152 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); 1153 else { 1154 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm); 1155 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1156 ResultReg).addReg(II.ImplicitDefs[0]); 1157 } 1158 return ResultReg; 1159} 1160 1161unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1162 unsigned Op0, bool Op0IsKill, 1163 uint32_t Idx) { 1164 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1165 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 1166 "Cannot yet extract from physregs"); 1167 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 1168 DL, TII.get(TargetOpcode::COPY), ResultReg) 1169 .addReg(Op0, getKillRegState(Op0IsKill), Idx); 1170 return ResultReg; 1171} 1172 1173/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1174/// with all but the least significant bit set to zero. 1175unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1176 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1177} 1178 1179/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1180/// Emit code to ensure constants are copied into registers when needed. 1181/// Remember the virtual registers that need to be added to the Machine PHI 1182/// nodes as input. We cannot just directly add them, because expansion 1183/// might result in multiple MBB's for one BB. As such, the start of the 1184/// BB might correspond to a different MBB than the end. 1185bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1186 const TerminatorInst *TI = LLVMBB->getTerminator(); 1187 1188 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1189 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); 1190 1191 // Check successor nodes' PHI nodes that expect a constant to be available 1192 // from this block. 1193 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1194 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1195 if (!isa<PHINode>(SuccBB->begin())) continue; 1196 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 1197 1198 // If this terminator has multiple identical successors (common for 1199 // switches), only handle each succ once. 1200 if (!SuccsHandled.insert(SuccMBB)) continue; 1201 1202 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1203 1204 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1205 // nodes and Machine PHI nodes, but the incoming operands have not been 1206 // emitted yet. 1207 for (BasicBlock::const_iterator I = SuccBB->begin(); 1208 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1209 1210 // Ignore dead phi's. 1211 if (PN->use_empty()) continue; 1212 1213 // Only handle legal types. Two interesting things to note here. First, 1214 // by bailing out early, we may leave behind some dead instructions, 1215 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1216 // own moves. Second, this check is necessary becuase FastISel doesn't 1217 // use CreateRegs to create registers, so it always creates 1218 // exactly one register for each non-void instruction. 1219 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1220 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1221 // Promote MVT::i1. 1222 if (VT == MVT::i1) 1223 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1224 else { 1225 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1226 return false; 1227 } 1228 } 1229 1230 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1231 1232 // Set the DebugLoc for the copy. Prefer the location of the operand 1233 // if there is one; use the location of the PHI otherwise. 1234 DL = PN->getDebugLoc(); 1235 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1236 DL = Inst->getDebugLoc(); 1237 1238 unsigned Reg = getRegForValue(PHIOp); 1239 if (Reg == 0) { 1240 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1241 return false; 1242 } 1243 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1244 DL = DebugLoc(); 1245 } 1246 } 1247 1248 return true; 1249} 1250