FastISel.cpp revision 518bb53485df640d7b7e3f6b0544099020c42aa7
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuilder.h" 57#include "FunctionLoweringInfo.h" 58using namespace llvm; 59 60unsigned FastISel::getRegForValue(Value *V) { 61 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 62 // Don't handle non-simple values in FastISel. 63 if (!RealVT.isSimple()) 64 return 0; 65 66 // Ignore illegal types. We must do this before looking up the value 67 // in ValueMap because Arguments are given virtual registers regardless 68 // of whether FastISel can handle them. 69 MVT VT = RealVT.getSimpleVT(); 70 if (!TLI.isTypeLegal(VT)) { 71 // Promote MVT::i1 to a legal type though, because it's common and easy. 72 if (VT == MVT::i1) 73 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 74 else 75 return 0; 76 } 77 78 // Look up the value to see if we already have a register for it. We 79 // cache values defined by Instructions across blocks, and other values 80 // only locally. This is because Instructions already have the SSA 81 // def-dominates-use requirement enforced. 82 if (ValueMap.count(V)) 83 return ValueMap[V]; 84 unsigned Reg = LocalValueMap[V]; 85 if (Reg != 0) 86 return Reg; 87 88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 89 if (CI->getValue().getActiveBits() <= 64) 90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 91 } else if (isa<AllocaInst>(V)) { 92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 93 } else if (isa<ConstantPointerNull>(V)) { 94 // Translate this as an integer zero so that it can be 95 // local-CSE'd with actual integer zeros. 96 Reg = 97 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 98 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 99 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 100 101 if (!Reg) { 102 const APFloat &Flt = CF->getValueAPF(); 103 EVT IntVT = TLI.getPointerTy(); 104 105 uint64_t x[2]; 106 uint32_t IntBitWidth = IntVT.getSizeInBits(); 107 bool isExact; 108 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 109 APFloat::rmTowardZero, &isExact); 110 if (isExact) { 111 APInt IntVal(IntBitWidth, 2, x); 112 113 unsigned IntegerReg = 114 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 115 if (IntegerReg != 0) 116 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 117 } 118 } 119 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 120 if (!SelectOperator(CE, CE->getOpcode())) return 0; 121 Reg = LocalValueMap[CE]; 122 } else if (isa<UndefValue>(V)) { 123 Reg = createResultReg(TLI.getRegClassFor(VT)); 124 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 125 } 126 127 // If target-independent code couldn't handle the value, give target-specific 128 // code a try. 129 if (!Reg && isa<Constant>(V)) 130 Reg = TargetMaterializeConstant(cast<Constant>(V)); 131 132 // Don't cache constant materializations in the general ValueMap. 133 // To do so would require tracking what uses they dominate. 134 if (Reg != 0) 135 LocalValueMap[V] = Reg; 136 return Reg; 137} 138 139unsigned FastISel::lookUpRegForValue(Value *V) { 140 // Look up the value to see if we already have a register for it. We 141 // cache values defined by Instructions across blocks, and other values 142 // only locally. This is because Instructions already have the SSA 143 // def-dominatess-use requirement enforced. 144 if (ValueMap.count(V)) 145 return ValueMap[V]; 146 return LocalValueMap[V]; 147} 148 149/// UpdateValueMap - Update the value map to include the new mapping for this 150/// instruction, or insert an extra copy to get the result in a previous 151/// determined register. 152/// NOTE: This is only necessary because we might select a block that uses 153/// a value before we select the block that defines the value. It might be 154/// possible to fix this by selecting blocks in reverse postorder. 155unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 156 if (!isa<Instruction>(I)) { 157 LocalValueMap[I] = Reg; 158 return Reg; 159 } 160 161 unsigned &AssignedReg = ValueMap[I]; 162 if (AssignedReg == 0) 163 AssignedReg = Reg; 164 else if (Reg != AssignedReg) { 165 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 166 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 167 Reg, RegClass, RegClass); 168 } 169 return AssignedReg; 170} 171 172unsigned FastISel::getRegForGEPIndex(Value *Idx) { 173 unsigned IdxN = getRegForValue(Idx); 174 if (IdxN == 0) 175 // Unhandled operand. Halt "fast" selection and bail. 176 return 0; 177 178 // If the index is smaller or larger than intptr_t, truncate or extend it. 179 MVT PtrVT = TLI.getPointerTy(); 180 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 181 if (IdxVT.bitsLT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); 183 else if (IdxVT.bitsGT(PtrVT)) 184 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) { 192 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT VT = TLI.getPointerTy(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 unsigned IID = F->getIntrinsicID(); 326 switch (IID) { 327 default: break; 328 case Intrinsic::dbg_declare: { 329 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 330 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW 331 || !DW->ShouldEmitDwarfDebug()) 332 return true; 333 334 Value *Address = DI->getAddress(); 335 if (!Address) 336 return true; 337 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 338 // Don't handle byval struct arguments or VLAs, for example. 339 if (!AI) break; 340 DenseMap<const AllocaInst*, int>::iterator SI = 341 StaticAllocaMap.find(AI); 342 if (SI == StaticAllocaMap.end()) break; // VLAs. 343 int FI = SI->second; 344 if (MMI) { 345 if (MDNode *Dbg = DI->getMetadata("dbg")) 346 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg); 347 } 348 // Building the map above is target independent. Generating DEBUG_VALUE 349 // inline is target dependent; do this now. 350 (void)TargetSelectInstruction(cast<Instruction>(I)); 351 return true; 352 } 353 case Intrinsic::eh_exception: { 354 EVT VT = TLI.getValueType(I->getType()); 355 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 356 default: break; 357 case TargetLowering::Expand: { 358 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 359 unsigned Reg = TLI.getExceptionAddressRegister(); 360 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 361 unsigned ResultReg = createResultReg(RC); 362 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 363 Reg, RC, RC); 364 assert(InsertedCopy && "Can't copy address registers!"); 365 InsertedCopy = InsertedCopy; 366 UpdateValueMap(I, ResultReg); 367 return true; 368 } 369 } 370 break; 371 } 372 case Intrinsic::eh_selector: { 373 EVT VT = TLI.getValueType(I->getType()); 374 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 375 default: break; 376 case TargetLowering::Expand: { 377 if (MMI) { 378 if (MBB->isLandingPad()) 379 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 380 else { 381#ifndef NDEBUG 382 CatchInfoLost.insert(cast<CallInst>(I)); 383#endif 384 // FIXME: Mark exception selector register as live in. Hack for PR1508. 385 unsigned Reg = TLI.getExceptionSelectorRegister(); 386 if (Reg) MBB->addLiveIn(Reg); 387 } 388 389 unsigned Reg = TLI.getExceptionSelectorRegister(); 390 EVT SrcVT = TLI.getPointerTy(); 391 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 392 unsigned ResultReg = createResultReg(RC); 393 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 394 RC, RC); 395 assert(InsertedCopy && "Can't copy address registers!"); 396 InsertedCopy = InsertedCopy; 397 398 // Cast the register to the type of the selector. 399 if (SrcVT.bitsGT(MVT::i32)) 400 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 401 ResultReg); 402 else if (SrcVT.bitsLT(MVT::i32)) 403 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 404 ISD::SIGN_EXTEND, ResultReg); 405 if (ResultReg == 0) 406 // Unhandled operand. Halt "fast" selection and bail. 407 return false; 408 409 UpdateValueMap(I, ResultReg); 410 } else { 411 unsigned ResultReg = 412 getRegForValue(Constant::getNullValue(I->getType())); 413 UpdateValueMap(I, ResultReg); 414 } 415 return true; 416 } 417 } 418 break; 419 } 420 } 421 return false; 422} 423 424bool FastISel::SelectCast(User *I, unsigned Opcode) { 425 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 426 EVT DstVT = TLI.getValueType(I->getType()); 427 428 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 429 DstVT == MVT::Other || !DstVT.isSimple()) 430 // Unhandled type. Halt "fast" selection and bail. 431 return false; 432 433 // Check if the destination type is legal. Or as a special case, 434 // it may be i1 if we're doing a truncate because that's 435 // easy and somewhat common. 436 if (!TLI.isTypeLegal(DstVT)) 437 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 438 // Unhandled type. Halt "fast" selection and bail. 439 return false; 440 441 // Check if the source operand is legal. Or as a special case, 442 // it may be i1 if we're doing zero-extension because that's 443 // easy and somewhat common. 444 if (!TLI.isTypeLegal(SrcVT)) 445 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 446 // Unhandled type. Halt "fast" selection and bail. 447 return false; 448 449 unsigned InputReg = getRegForValue(I->getOperand(0)); 450 if (!InputReg) 451 // Unhandled operand. Halt "fast" selection and bail. 452 return false; 453 454 // If the operand is i1, arrange for the high bits in the register to be zero. 455 if (SrcVT == MVT::i1) { 456 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 457 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 458 if (!InputReg) 459 return false; 460 } 461 // If the result is i1, truncate to the target's type for i1 first. 462 if (DstVT == MVT::i1) 463 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 464 465 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 466 DstVT.getSimpleVT(), 467 Opcode, 468 InputReg); 469 if (!ResultReg) 470 return false; 471 472 UpdateValueMap(I, ResultReg); 473 return true; 474} 475 476bool FastISel::SelectBitCast(User *I) { 477 // If the bitcast doesn't change the type, just use the operand value. 478 if (I->getType() == I->getOperand(0)->getType()) { 479 unsigned Reg = getRegForValue(I->getOperand(0)); 480 if (Reg == 0) 481 return false; 482 UpdateValueMap(I, Reg); 483 return true; 484 } 485 486 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 487 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 488 EVT DstVT = TLI.getValueType(I->getType()); 489 490 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 491 DstVT == MVT::Other || !DstVT.isSimple() || 492 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 493 // Unhandled type. Halt "fast" selection and bail. 494 return false; 495 496 unsigned Op0 = getRegForValue(I->getOperand(0)); 497 if (Op0 == 0) 498 // Unhandled operand. Halt "fast" selection and bail. 499 return false; 500 501 // First, try to perform the bitcast by inserting a reg-reg copy. 502 unsigned ResultReg = 0; 503 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 504 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 505 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 506 ResultReg = createResultReg(DstClass); 507 508 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 509 Op0, DstClass, SrcClass); 510 if (!InsertedCopy) 511 ResultReg = 0; 512 } 513 514 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 515 if (!ResultReg) 516 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 517 ISD::BIT_CONVERT, Op0); 518 519 if (!ResultReg) 520 return false; 521 522 UpdateValueMap(I, ResultReg); 523 return true; 524} 525 526bool 527FastISel::SelectInstruction(Instruction *I) { 528 // First, try doing target-independent selection. 529 if (SelectOperator(I, I->getOpcode())) 530 return true; 531 532 // Next, try calling the target to attempt to handle the instruction. 533 if (TargetSelectInstruction(I)) 534 return true; 535 536 return false; 537} 538 539/// FastEmitBranch - Emit an unconditional branch to the given block, 540/// unless it is the immediate (fall-through) successor, and update 541/// the CFG. 542void 543FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 544 if (MBB->isLayoutSuccessor(MSucc)) { 545 // The unconditional fall-through case, which needs no instructions. 546 } else { 547 // The unconditional branch case. 548 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 549 } 550 MBB->addSuccessor(MSucc); 551} 552 553/// SelectFNeg - Emit an FNeg operation. 554/// 555bool 556FastISel::SelectFNeg(User *I) { 557 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 558 if (OpReg == 0) return false; 559 560 // If the target has ISD::FNEG, use it. 561 EVT VT = TLI.getValueType(I->getType()); 562 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 563 ISD::FNEG, OpReg); 564 if (ResultReg != 0) { 565 UpdateValueMap(I, ResultReg); 566 return true; 567 } 568 569 // Bitcast the value to integer, twiddle the sign bit with xor, 570 // and then bitcast it back to floating-point. 571 if (VT.getSizeInBits() > 64) return false; 572 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 573 if (!TLI.isTypeLegal(IntVT)) 574 return false; 575 576 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 577 ISD::BIT_CONVERT, OpReg); 578 if (IntReg == 0) 579 return false; 580 581 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, 582 UINT64_C(1) << (VT.getSizeInBits()-1), 583 IntVT.getSimpleVT()); 584 if (IntResultReg == 0) 585 return false; 586 587 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 588 ISD::BIT_CONVERT, IntResultReg); 589 if (ResultReg == 0) 590 return false; 591 592 UpdateValueMap(I, ResultReg); 593 return true; 594} 595 596bool 597FastISel::SelectOperator(User *I, unsigned Opcode) { 598 switch (Opcode) { 599 case Instruction::Add: 600 return SelectBinaryOp(I, ISD::ADD); 601 case Instruction::FAdd: 602 return SelectBinaryOp(I, ISD::FADD); 603 case Instruction::Sub: 604 return SelectBinaryOp(I, ISD::SUB); 605 case Instruction::FSub: 606 // FNeg is currently represented in LLVM IR as a special case of FSub. 607 if (BinaryOperator::isFNeg(I)) 608 return SelectFNeg(I); 609 return SelectBinaryOp(I, ISD::FSUB); 610 case Instruction::Mul: 611 return SelectBinaryOp(I, ISD::MUL); 612 case Instruction::FMul: 613 return SelectBinaryOp(I, ISD::FMUL); 614 case Instruction::SDiv: 615 return SelectBinaryOp(I, ISD::SDIV); 616 case Instruction::UDiv: 617 return SelectBinaryOp(I, ISD::UDIV); 618 case Instruction::FDiv: 619 return SelectBinaryOp(I, ISD::FDIV); 620 case Instruction::SRem: 621 return SelectBinaryOp(I, ISD::SREM); 622 case Instruction::URem: 623 return SelectBinaryOp(I, ISD::UREM); 624 case Instruction::FRem: 625 return SelectBinaryOp(I, ISD::FREM); 626 case Instruction::Shl: 627 return SelectBinaryOp(I, ISD::SHL); 628 case Instruction::LShr: 629 return SelectBinaryOp(I, ISD::SRL); 630 case Instruction::AShr: 631 return SelectBinaryOp(I, ISD::SRA); 632 case Instruction::And: 633 return SelectBinaryOp(I, ISD::AND); 634 case Instruction::Or: 635 return SelectBinaryOp(I, ISD::OR); 636 case Instruction::Xor: 637 return SelectBinaryOp(I, ISD::XOR); 638 639 case Instruction::GetElementPtr: 640 return SelectGetElementPtr(I); 641 642 case Instruction::Br: { 643 BranchInst *BI = cast<BranchInst>(I); 644 645 if (BI->isUnconditional()) { 646 BasicBlock *LLVMSucc = BI->getSuccessor(0); 647 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 648 FastEmitBranch(MSucc); 649 return true; 650 } 651 652 // Conditional branches are not handed yet. 653 // Halt "fast" selection and bail. 654 return false; 655 } 656 657 case Instruction::Unreachable: 658 // Nothing to emit. 659 return true; 660 661 case Instruction::PHI: 662 // PHI nodes are already emitted. 663 return true; 664 665 case Instruction::Alloca: 666 // FunctionLowering has the static-sized case covered. 667 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 668 return true; 669 670 // Dynamic-sized alloca is not handled yet. 671 return false; 672 673 case Instruction::Call: 674 return SelectCall(I); 675 676 case Instruction::BitCast: 677 return SelectBitCast(I); 678 679 case Instruction::FPToSI: 680 return SelectCast(I, ISD::FP_TO_SINT); 681 case Instruction::ZExt: 682 return SelectCast(I, ISD::ZERO_EXTEND); 683 case Instruction::SExt: 684 return SelectCast(I, ISD::SIGN_EXTEND); 685 case Instruction::Trunc: 686 return SelectCast(I, ISD::TRUNCATE); 687 case Instruction::SIToFP: 688 return SelectCast(I, ISD::SINT_TO_FP); 689 690 case Instruction::IntToPtr: // Deliberate fall-through. 691 case Instruction::PtrToInt: { 692 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 693 EVT DstVT = TLI.getValueType(I->getType()); 694 if (DstVT.bitsGT(SrcVT)) 695 return SelectCast(I, ISD::ZERO_EXTEND); 696 if (DstVT.bitsLT(SrcVT)) 697 return SelectCast(I, ISD::TRUNCATE); 698 unsigned Reg = getRegForValue(I->getOperand(0)); 699 if (Reg == 0) return false; 700 UpdateValueMap(I, Reg); 701 return true; 702 } 703 704 default: 705 // Unhandled instruction. Halt "fast" selection and bail. 706 return false; 707 } 708} 709 710FastISel::FastISel(MachineFunction &mf, 711 MachineModuleInfo *mmi, 712 DwarfWriter *dw, 713 DenseMap<const Value *, unsigned> &vm, 714 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 715 DenseMap<const AllocaInst *, int> &am 716#ifndef NDEBUG 717 , SmallSet<Instruction*, 8> &cil 718#endif 719 ) 720 : MBB(0), 721 ValueMap(vm), 722 MBBMap(bm), 723 StaticAllocaMap(am), 724#ifndef NDEBUG 725 CatchInfoLost(cil), 726#endif 727 MF(mf), 728 MMI(mmi), 729 DW(dw), 730 MRI(MF.getRegInfo()), 731 MFI(*MF.getFrameInfo()), 732 MCP(*MF.getConstantPool()), 733 TM(MF.getTarget()), 734 TD(*TM.getTargetData()), 735 TII(*TM.getInstrInfo()), 736 TLI(*TM.getTargetLowering()) { 737} 738 739FastISel::~FastISel() {} 740 741unsigned FastISel::FastEmit_(MVT, MVT, 742 unsigned) { 743 return 0; 744} 745 746unsigned FastISel::FastEmit_r(MVT, MVT, 747 unsigned, unsigned /*Op0*/) { 748 return 0; 749} 750 751unsigned FastISel::FastEmit_rr(MVT, MVT, 752 unsigned, unsigned /*Op0*/, 753 unsigned /*Op0*/) { 754 return 0; 755} 756 757unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 758 return 0; 759} 760 761unsigned FastISel::FastEmit_f(MVT, MVT, 762 unsigned, ConstantFP * /*FPImm*/) { 763 return 0; 764} 765 766unsigned FastISel::FastEmit_ri(MVT, MVT, 767 unsigned, unsigned /*Op0*/, 768 uint64_t /*Imm*/) { 769 return 0; 770} 771 772unsigned FastISel::FastEmit_rf(MVT, MVT, 773 unsigned, unsigned /*Op0*/, 774 ConstantFP * /*FPImm*/) { 775 return 0; 776} 777 778unsigned FastISel::FastEmit_rri(MVT, MVT, 779 unsigned, 780 unsigned /*Op0*/, unsigned /*Op1*/, 781 uint64_t /*Imm*/) { 782 return 0; 783} 784 785/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 786/// to emit an instruction with an immediate operand using FastEmit_ri. 787/// If that fails, it materializes the immediate into a register and try 788/// FastEmit_rr instead. 789unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 790 unsigned Op0, uint64_t Imm, 791 MVT ImmType) { 792 // First check if immediate type is legal. If not, we can't use the ri form. 793 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 794 if (ResultReg != 0) 795 return ResultReg; 796 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 797 if (MaterialReg == 0) 798 return 0; 799 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 800} 801 802/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 803/// to emit an instruction with a floating-point immediate operand using 804/// FastEmit_rf. If that fails, it materializes the immediate into a register 805/// and try FastEmit_rr instead. 806unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 807 unsigned Op0, ConstantFP *FPImm, 808 MVT ImmType) { 809 // First check if immediate type is legal. If not, we can't use the rf form. 810 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 811 if (ResultReg != 0) 812 return ResultReg; 813 814 // Materialize the constant in a register. 815 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 816 if (MaterialReg == 0) { 817 // If the target doesn't have a way to directly enter a floating-point 818 // value into a register, use an alternate approach. 819 // TODO: The current approach only supports floating-point constants 820 // that can be constructed by conversion from integer values. This should 821 // be replaced by code that creates a load from a constant-pool entry, 822 // which will require some target-specific work. 823 const APFloat &Flt = FPImm->getValueAPF(); 824 EVT IntVT = TLI.getPointerTy(); 825 826 uint64_t x[2]; 827 uint32_t IntBitWidth = IntVT.getSizeInBits(); 828 bool isExact; 829 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 830 APFloat::rmTowardZero, &isExact); 831 if (!isExact) 832 return 0; 833 APInt IntVal(IntBitWidth, 2, x); 834 835 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 836 ISD::Constant, IntVal.getZExtValue()); 837 if (IntegerReg == 0) 838 return 0; 839 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 840 ISD::SINT_TO_FP, IntegerReg); 841 if (MaterialReg == 0) 842 return 0; 843 } 844 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 845} 846 847unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 848 return MRI.createVirtualRegister(RC); 849} 850 851unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 852 const TargetRegisterClass* RC) { 853 unsigned ResultReg = createResultReg(RC); 854 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 855 856 BuildMI(MBB, DL, II, ResultReg); 857 return ResultReg; 858} 859 860unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 861 const TargetRegisterClass *RC, 862 unsigned Op0) { 863 unsigned ResultReg = createResultReg(RC); 864 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 865 866 if (II.getNumDefs() >= 1) 867 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 868 else { 869 BuildMI(MBB, DL, II).addReg(Op0); 870 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 871 II.ImplicitDefs[0], RC, RC); 872 if (!InsertedCopy) 873 ResultReg = 0; 874 } 875 876 return ResultReg; 877} 878 879unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 880 const TargetRegisterClass *RC, 881 unsigned Op0, unsigned Op1) { 882 unsigned ResultReg = createResultReg(RC); 883 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 884 885 if (II.getNumDefs() >= 1) 886 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 887 else { 888 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 889 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 890 II.ImplicitDefs[0], RC, RC); 891 if (!InsertedCopy) 892 ResultReg = 0; 893 } 894 return ResultReg; 895} 896 897unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 898 const TargetRegisterClass *RC, 899 unsigned Op0, uint64_t Imm) { 900 unsigned ResultReg = createResultReg(RC); 901 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 902 903 if (II.getNumDefs() >= 1) 904 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 905 else { 906 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 907 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 908 II.ImplicitDefs[0], RC, RC); 909 if (!InsertedCopy) 910 ResultReg = 0; 911 } 912 return ResultReg; 913} 914 915unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 916 const TargetRegisterClass *RC, 917 unsigned Op0, ConstantFP *FPImm) { 918 unsigned ResultReg = createResultReg(RC); 919 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 920 921 if (II.getNumDefs() >= 1) 922 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 923 else { 924 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 925 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 926 II.ImplicitDefs[0], RC, RC); 927 if (!InsertedCopy) 928 ResultReg = 0; 929 } 930 return ResultReg; 931} 932 933unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 934 const TargetRegisterClass *RC, 935 unsigned Op0, unsigned Op1, uint64_t Imm) { 936 unsigned ResultReg = createResultReg(RC); 937 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 938 939 if (II.getNumDefs() >= 1) 940 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 941 else { 942 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 943 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 944 II.ImplicitDefs[0], RC, RC); 945 if (!InsertedCopy) 946 ResultReg = 0; 947 } 948 return ResultReg; 949} 950 951unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 952 const TargetRegisterClass *RC, 953 uint64_t Imm) { 954 unsigned ResultReg = createResultReg(RC); 955 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 956 957 if (II.getNumDefs() >= 1) 958 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 959 else { 960 BuildMI(MBB, DL, II).addImm(Imm); 961 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 962 II.ImplicitDefs[0], RC, RC); 963 if (!InsertedCopy) 964 ResultReg = 0; 965 } 966 return ResultReg; 967} 968 969unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 970 unsigned Op0, uint32_t Idx) { 971 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 972 973 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 974 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG); 975 976 if (II.getNumDefs() >= 1) 977 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 978 else { 979 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 980 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 981 II.ImplicitDefs[0], RC, RC); 982 if (!InsertedCopy) 983 ResultReg = 0; 984 } 985 return ResultReg; 986} 987 988/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 989/// with all but the least significant bit set to zero. 990unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) { 991 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 992} 993