FastISel.cpp revision 581cdf90ade3d318dedde0c645d478ffede09e0d
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/LLVMContext.h" 47#include "llvm/CodeGen/FastISel.h" 48#include "llvm/CodeGen/MachineInstrBuilder.h" 49#include "llvm/CodeGen/MachineModuleInfo.h" 50#include "llvm/CodeGen/MachineRegisterInfo.h" 51#include "llvm/CodeGen/DwarfWriter.h" 52#include "llvm/Analysis/DebugInfo.h" 53#include "llvm/Target/TargetData.h" 54#include "llvm/Target/TargetInstrInfo.h" 55#include "llvm/Target/TargetLowering.h" 56#include "llvm/Target/TargetMachine.h" 57#include "SelectionDAGBuilder.h" 58#include "FunctionLoweringInfo.h" 59using namespace llvm; 60 61unsigned FastISel::getRegForValue(Value *V) { 62 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 63 // Don't handle non-simple values in FastISel. 64 if (!RealVT.isSimple()) 65 return 0; 66 67 // Ignore illegal types. We must do this before looking up the value 68 // in ValueMap because Arguments are given virtual registers regardless 69 // of whether FastISel can handle them. 70 MVT VT = RealVT.getSimpleVT(); 71 if (!TLI.isTypeLegal(VT)) { 72 // Promote MVT::i1 to a legal type though, because it's common and easy. 73 if (VT == MVT::i1) 74 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 75 else 76 return 0; 77 } 78 79 // Look up the value to see if we already have a register for it. We 80 // cache values defined by Instructions across blocks, and other values 81 // only locally. This is because Instructions already have the SSA 82 // def-dominatess-use requirement enforced. 83 if (ValueMap.count(V)) 84 return ValueMap[V]; 85 unsigned Reg = LocalValueMap[V]; 86 if (Reg != 0) 87 return Reg; 88 89 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 90 if (CI->getValue().getActiveBits() <= 64) 91 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 92 } else if (isa<AllocaInst>(V)) { 93 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 94 } else if (isa<ConstantPointerNull>(V)) { 95 // Translate this as an integer zero so that it can be 96 // local-CSE'd with actual integer zeros. 97 Reg = 98 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 99 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 100 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 101 102 if (!Reg) { 103 const APFloat &Flt = CF->getValueAPF(); 104 EVT IntVT = TLI.getPointerTy(); 105 106 uint64_t x[2]; 107 uint32_t IntBitWidth = IntVT.getSizeInBits(); 108 bool isExact; 109 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 110 APFloat::rmTowardZero, &isExact); 111 if (isExact) { 112 APInt IntVal(IntBitWidth, 2, x); 113 114 unsigned IntegerReg = 115 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 116 if (IntegerReg != 0) 117 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 118 } 119 } 120 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 121 if (!SelectOperator(CE, CE->getOpcode())) return 0; 122 Reg = LocalValueMap[CE]; 123 } else if (isa<UndefValue>(V)) { 124 Reg = createResultReg(TLI.getRegClassFor(VT)); 125 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 126 } 127 128 // If target-independent code couldn't handle the value, give target-specific 129 // code a try. 130 if (!Reg && isa<Constant>(V)) 131 Reg = TargetMaterializeConstant(cast<Constant>(V)); 132 133 // Don't cache constant materializations in the general ValueMap. 134 // To do so would require tracking what uses they dominate. 135 if (Reg != 0) 136 LocalValueMap[V] = Reg; 137 return Reg; 138} 139 140unsigned FastISel::lookUpRegForValue(Value *V) { 141 // Look up the value to see if we already have a register for it. We 142 // cache values defined by Instructions across blocks, and other values 143 // only locally. This is because Instructions already have the SSA 144 // def-dominatess-use requirement enforced. 145 if (ValueMap.count(V)) 146 return ValueMap[V]; 147 return LocalValueMap[V]; 148} 149 150/// UpdateValueMap - Update the value map to include the new mapping for this 151/// instruction, or insert an extra copy to get the result in a previous 152/// determined register. 153/// NOTE: This is only necessary because we might select a block that uses 154/// a value before we select the block that defines the value. It might be 155/// possible to fix this by selecting blocks in reverse postorder. 156unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 157 if (!isa<Instruction>(I)) { 158 LocalValueMap[I] = Reg; 159 return Reg; 160 } 161 162 unsigned &AssignedReg = ValueMap[I]; 163 if (AssignedReg == 0) 164 AssignedReg = Reg; 165 else if (Reg != AssignedReg) { 166 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 167 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 168 Reg, RegClass, RegClass); 169 } 170 return AssignedReg; 171} 172 173unsigned FastISel::getRegForGEPIndex(Value *Idx) { 174 unsigned IdxN = getRegForValue(Idx); 175 if (IdxN == 0) 176 // Unhandled operand. Halt "fast" selection and bail. 177 return 0; 178 179 // If the index is smaller or larger than intptr_t, truncate or extend it. 180 MVT PtrVT = TLI.getPointerTy(); 181 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 182 if (IdxVT.bitsLT(PtrVT)) 183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); 184 else if (IdxVT.bitsGT(PtrVT)) 185 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); 186 return IdxN; 187} 188 189/// SelectBinaryOp - Select and emit code for a binary operator instruction, 190/// which has an opcode which directly corresponds to the given ISD opcode. 191/// 192bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 193 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 194 if (VT == MVT::Other || !VT.isSimple()) 195 // Unhandled type. Halt "fast" selection and bail. 196 return false; 197 198 // We only handle legal types. For example, on x86-32 the instruction 199 // selector contains all of the 64-bit instructions from x86-64, 200 // under the assumption that i64 won't be used if the target doesn't 201 // support it. 202 if (!TLI.isTypeLegal(VT)) { 203 // MVT::i1 is special. Allow AND, OR, or XOR because they 204 // don't require additional zeroing, which makes them easy. 205 if (VT == MVT::i1 && 206 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 207 ISDOpcode == ISD::XOR)) 208 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 209 else 210 return false; 211 } 212 213 unsigned Op0 = getRegForValue(I->getOperand(0)); 214 if (Op0 == 0) 215 // Unhandled operand. Halt "fast" selection and bail. 216 return false; 217 218 // Check if the second operand is a constant and handle it appropriately. 219 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 220 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 221 ISDOpcode, Op0, CI->getZExtValue()); 222 if (ResultReg != 0) { 223 // We successfully emitted code for the given LLVM Instruction. 224 UpdateValueMap(I, ResultReg); 225 return true; 226 } 227 } 228 229 // Check if the second operand is a constant float. 230 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 231 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 232 ISDOpcode, Op0, CF); 233 if (ResultReg != 0) { 234 // We successfully emitted code for the given LLVM Instruction. 235 UpdateValueMap(I, ResultReg); 236 return true; 237 } 238 } 239 240 unsigned Op1 = getRegForValue(I->getOperand(1)); 241 if (Op1 == 0) 242 // Unhandled operand. Halt "fast" selection and bail. 243 return false; 244 245 // Now we have both operands in registers. Emit the instruction. 246 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 247 ISDOpcode, Op0, Op1); 248 if (ResultReg == 0) 249 // Target-specific code wasn't able to find a machine opcode for 250 // the given ISD opcode and type. Halt "fast" selection and bail. 251 return false; 252 253 // We successfully emitted code for the given LLVM Instruction. 254 UpdateValueMap(I, ResultReg); 255 return true; 256} 257 258bool FastISel::SelectGetElementPtr(User *I) { 259 unsigned N = getRegForValue(I->getOperand(0)); 260 if (N == 0) 261 // Unhandled operand. Halt "fast" selection and bail. 262 return false; 263 264 const Type *Ty = I->getOperand(0)->getType(); 265 MVT VT = TLI.getPointerTy(); 266 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 267 OI != E; ++OI) { 268 Value *Idx = *OI; 269 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 270 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 271 if (Field) { 272 // N = N + Offset 273 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 274 // FIXME: This can be optimized by combining the add with a 275 // subsequent one. 276 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 277 if (N == 0) 278 // Unhandled operand. Halt "fast" selection and bail. 279 return false; 280 } 281 Ty = StTy->getElementType(Field); 282 } else { 283 Ty = cast<SequentialType>(Ty)->getElementType(); 284 285 // If this is a constant subscript, handle it quickly. 286 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 287 if (CI->getZExtValue() == 0) continue; 288 uint64_t Offs = 289 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 290 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 291 if (N == 0) 292 // Unhandled operand. Halt "fast" selection and bail. 293 return false; 294 continue; 295 } 296 297 // N = N + Idx * ElementSize; 298 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 299 unsigned IdxN = getRegForGEPIndex(Idx); 300 if (IdxN == 0) 301 // Unhandled operand. Halt "fast" selection and bail. 302 return false; 303 304 if (ElementSize != 1) { 305 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 306 if (IdxN == 0) 307 // Unhandled operand. Halt "fast" selection and bail. 308 return false; 309 } 310 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 311 if (N == 0) 312 // Unhandled operand. Halt "fast" selection and bail. 313 return false; 314 } 315 } 316 317 // We successfully emitted code for the given LLVM Instruction. 318 UpdateValueMap(I, N); 319 return true; 320} 321 322bool FastISel::SelectCall(User *I) { 323 Function *F = cast<CallInst>(I)->getCalledFunction(); 324 if (!F) return false; 325 326 unsigned IID = F->getIntrinsicID(); 327 switch (IID) { 328 default: break; 329 case Intrinsic::dbg_stoppoint: 330 case Intrinsic::dbg_region_start: 331 case Intrinsic::dbg_region_end: 332 case Intrinsic::dbg_func_start: 333 // FIXME - Remove this instructions once the dust settles. 334 return true; 335 case Intrinsic::dbg_declare: { 336 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 337 if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW 338 || !DW->ShouldEmitDwarfDebug()) 339 return true; 340 341 Value *Address = DI->getAddress(); 342 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 343 Address = BCI->getOperand(0); 344 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 345 // Don't handle byval struct arguments or VLAs, for example. 346 if (!AI) break; 347 DenseMap<const AllocaInst*, int>::iterator SI = 348 StaticAllocaMap.find(AI); 349 if (SI == StaticAllocaMap.end()) break; // VLAs. 350 int FI = SI->second; 351 if (MMI) { 352 MetadataContext &TheMetadata = 353 DI->getParent()->getContext().getMetadata(); 354 unsigned MDDbgKind = TheMetadata.getMDKind("dbg"); 355 MDNode *Dbg = TheMetadata.getMD(MDDbgKind, DI); 356 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg); 357 } 358 return true; 359 } 360 case Intrinsic::eh_exception: { 361 EVT VT = TLI.getValueType(I->getType()); 362 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 363 default: break; 364 case TargetLowering::Expand: { 365 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 366 unsigned Reg = TLI.getExceptionAddressRegister(); 367 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 368 unsigned ResultReg = createResultReg(RC); 369 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 370 Reg, RC, RC); 371 assert(InsertedCopy && "Can't copy address registers!"); 372 InsertedCopy = InsertedCopy; 373 UpdateValueMap(I, ResultReg); 374 return true; 375 } 376 } 377 break; 378 } 379 case Intrinsic::eh_selector: { 380 EVT VT = TLI.getValueType(I->getType()); 381 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 382 default: break; 383 case TargetLowering::Expand: { 384 if (MMI) { 385 if (MBB->isLandingPad()) 386 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 387 else { 388#ifndef NDEBUG 389 CatchInfoLost.insert(cast<CallInst>(I)); 390#endif 391 // FIXME: Mark exception selector register as live in. Hack for PR1508. 392 unsigned Reg = TLI.getExceptionSelectorRegister(); 393 if (Reg) MBB->addLiveIn(Reg); 394 } 395 396 unsigned Reg = TLI.getExceptionSelectorRegister(); 397 EVT SrcVT = TLI.getPointerTy(); 398 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 399 unsigned ResultReg = createResultReg(RC); 400 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 401 RC, RC); 402 assert(InsertedCopy && "Can't copy address registers!"); 403 InsertedCopy = InsertedCopy; 404 405 // Cast the register to the type of the selector. 406 if (SrcVT.bitsGT(MVT::i32)) 407 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 408 ResultReg); 409 else if (SrcVT.bitsLT(MVT::i32)) 410 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 411 ISD::SIGN_EXTEND, ResultReg); 412 if (ResultReg == 0) 413 // Unhandled operand. Halt "fast" selection and bail. 414 return false; 415 416 UpdateValueMap(I, ResultReg); 417 } else { 418 unsigned ResultReg = 419 getRegForValue(Constant::getNullValue(I->getType())); 420 UpdateValueMap(I, ResultReg); 421 } 422 return true; 423 } 424 } 425 break; 426 } 427 } 428 return false; 429} 430 431bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 432 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 433 EVT DstVT = TLI.getValueType(I->getType()); 434 435 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 436 DstVT == MVT::Other || !DstVT.isSimple()) 437 // Unhandled type. Halt "fast" selection and bail. 438 return false; 439 440 // Check if the destination type is legal. Or as a special case, 441 // it may be i1 if we're doing a truncate because that's 442 // easy and somewhat common. 443 if (!TLI.isTypeLegal(DstVT)) 444 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 445 // Unhandled type. Halt "fast" selection and bail. 446 return false; 447 448 // Check if the source operand is legal. Or as a special case, 449 // it may be i1 if we're doing zero-extension because that's 450 // easy and somewhat common. 451 if (!TLI.isTypeLegal(SrcVT)) 452 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 453 // Unhandled type. Halt "fast" selection and bail. 454 return false; 455 456 unsigned InputReg = getRegForValue(I->getOperand(0)); 457 if (!InputReg) 458 // Unhandled operand. Halt "fast" selection and bail. 459 return false; 460 461 // If the operand is i1, arrange for the high bits in the register to be zero. 462 if (SrcVT == MVT::i1) { 463 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 464 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 465 if (!InputReg) 466 return false; 467 } 468 // If the result is i1, truncate to the target's type for i1 first. 469 if (DstVT == MVT::i1) 470 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 471 472 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 473 DstVT.getSimpleVT(), 474 Opcode, 475 InputReg); 476 if (!ResultReg) 477 return false; 478 479 UpdateValueMap(I, ResultReg); 480 return true; 481} 482 483bool FastISel::SelectBitCast(User *I) { 484 // If the bitcast doesn't change the type, just use the operand value. 485 if (I->getType() == I->getOperand(0)->getType()) { 486 unsigned Reg = getRegForValue(I->getOperand(0)); 487 if (Reg == 0) 488 return false; 489 UpdateValueMap(I, Reg); 490 return true; 491 } 492 493 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 494 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 495 EVT DstVT = TLI.getValueType(I->getType()); 496 497 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 498 DstVT == MVT::Other || !DstVT.isSimple() || 499 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 500 // Unhandled type. Halt "fast" selection and bail. 501 return false; 502 503 unsigned Op0 = getRegForValue(I->getOperand(0)); 504 if (Op0 == 0) 505 // Unhandled operand. Halt "fast" selection and bail. 506 return false; 507 508 // First, try to perform the bitcast by inserting a reg-reg copy. 509 unsigned ResultReg = 0; 510 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 511 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 512 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 513 ResultReg = createResultReg(DstClass); 514 515 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 516 Op0, DstClass, SrcClass); 517 if (!InsertedCopy) 518 ResultReg = 0; 519 } 520 521 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 522 if (!ResultReg) 523 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 524 ISD::BIT_CONVERT, Op0); 525 526 if (!ResultReg) 527 return false; 528 529 UpdateValueMap(I, ResultReg); 530 return true; 531} 532 533bool 534FastISel::SelectInstruction(Instruction *I) { 535 // First, try doing target-independent selection. 536 if (SelectOperator(I, I->getOpcode())) 537 return true; 538 539 // Next, try calling the target to attempt to handle the instruction. 540 if (TargetSelectInstruction(I)) 541 return true; 542 543 return false; 544} 545 546/// FastEmitBranch - Emit an unconditional branch to the given block, 547/// unless it is the immediate (fall-through) successor, and update 548/// the CFG. 549void 550FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 551 MachineFunction::iterator NextMBB = 552 llvm::next(MachineFunction::iterator(MBB)); 553 554 if (MBB->isLayoutSuccessor(MSucc)) { 555 // The unconditional fall-through case, which needs no instructions. 556 } else { 557 // The unconditional branch case. 558 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 559 } 560 MBB->addSuccessor(MSucc); 561} 562 563/// SelectFNeg - Emit an FNeg operation. 564/// 565bool 566FastISel::SelectFNeg(User *I) { 567 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 568 if (OpReg == 0) return false; 569 570 // If the target has ISD::FNEG, use it. 571 EVT VT = TLI.getValueType(I->getType()); 572 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 573 ISD::FNEG, OpReg); 574 if (ResultReg != 0) { 575 UpdateValueMap(I, ResultReg); 576 return true; 577 } 578 579 // Bitcast the value to integer, twiddle the sign bit with xor, 580 // and then bitcast it back to floating-point. 581 if (VT.getSizeInBits() > 64) return false; 582 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 583 if (!TLI.isTypeLegal(IntVT)) 584 return false; 585 586 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 587 ISD::BIT_CONVERT, OpReg); 588 if (IntReg == 0) 589 return false; 590 591 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, 592 UINT64_C(1) << (VT.getSizeInBits()-1), 593 IntVT.getSimpleVT()); 594 if (IntResultReg == 0) 595 return false; 596 597 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 598 ISD::BIT_CONVERT, IntResultReg); 599 if (ResultReg == 0) 600 return false; 601 602 UpdateValueMap(I, ResultReg); 603 return true; 604} 605 606bool 607FastISel::SelectOperator(User *I, unsigned Opcode) { 608 switch (Opcode) { 609 case Instruction::Add: 610 return SelectBinaryOp(I, ISD::ADD); 611 case Instruction::FAdd: 612 return SelectBinaryOp(I, ISD::FADD); 613 case Instruction::Sub: 614 return SelectBinaryOp(I, ISD::SUB); 615 case Instruction::FSub: 616 // FNeg is currently represented in LLVM IR as a special case of FSub. 617 if (BinaryOperator::isFNeg(I)) 618 return SelectFNeg(I); 619 return SelectBinaryOp(I, ISD::FSUB); 620 case Instruction::Mul: 621 return SelectBinaryOp(I, ISD::MUL); 622 case Instruction::FMul: 623 return SelectBinaryOp(I, ISD::FMUL); 624 case Instruction::SDiv: 625 return SelectBinaryOp(I, ISD::SDIV); 626 case Instruction::UDiv: 627 return SelectBinaryOp(I, ISD::UDIV); 628 case Instruction::FDiv: 629 return SelectBinaryOp(I, ISD::FDIV); 630 case Instruction::SRem: 631 return SelectBinaryOp(I, ISD::SREM); 632 case Instruction::URem: 633 return SelectBinaryOp(I, ISD::UREM); 634 case Instruction::FRem: 635 return SelectBinaryOp(I, ISD::FREM); 636 case Instruction::Shl: 637 return SelectBinaryOp(I, ISD::SHL); 638 case Instruction::LShr: 639 return SelectBinaryOp(I, ISD::SRL); 640 case Instruction::AShr: 641 return SelectBinaryOp(I, ISD::SRA); 642 case Instruction::And: 643 return SelectBinaryOp(I, ISD::AND); 644 case Instruction::Or: 645 return SelectBinaryOp(I, ISD::OR); 646 case Instruction::Xor: 647 return SelectBinaryOp(I, ISD::XOR); 648 649 case Instruction::GetElementPtr: 650 return SelectGetElementPtr(I); 651 652 case Instruction::Br: { 653 BranchInst *BI = cast<BranchInst>(I); 654 655 if (BI->isUnconditional()) { 656 BasicBlock *LLVMSucc = BI->getSuccessor(0); 657 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 658 FastEmitBranch(MSucc); 659 return true; 660 } 661 662 // Conditional branches are not handed yet. 663 // Halt "fast" selection and bail. 664 return false; 665 } 666 667 case Instruction::Unreachable: 668 // Nothing to emit. 669 return true; 670 671 case Instruction::PHI: 672 // PHI nodes are already emitted. 673 return true; 674 675 case Instruction::Alloca: 676 // FunctionLowering has the static-sized case covered. 677 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 678 return true; 679 680 // Dynamic-sized alloca is not handled yet. 681 return false; 682 683 case Instruction::Call: 684 return SelectCall(I); 685 686 case Instruction::BitCast: 687 return SelectBitCast(I); 688 689 case Instruction::FPToSI: 690 return SelectCast(I, ISD::FP_TO_SINT); 691 case Instruction::ZExt: 692 return SelectCast(I, ISD::ZERO_EXTEND); 693 case Instruction::SExt: 694 return SelectCast(I, ISD::SIGN_EXTEND); 695 case Instruction::Trunc: 696 return SelectCast(I, ISD::TRUNCATE); 697 case Instruction::SIToFP: 698 return SelectCast(I, ISD::SINT_TO_FP); 699 700 case Instruction::IntToPtr: // Deliberate fall-through. 701 case Instruction::PtrToInt: { 702 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 703 EVT DstVT = TLI.getValueType(I->getType()); 704 if (DstVT.bitsGT(SrcVT)) 705 return SelectCast(I, ISD::ZERO_EXTEND); 706 if (DstVT.bitsLT(SrcVT)) 707 return SelectCast(I, ISD::TRUNCATE); 708 unsigned Reg = getRegForValue(I->getOperand(0)); 709 if (Reg == 0) return false; 710 UpdateValueMap(I, Reg); 711 return true; 712 } 713 714 default: 715 // Unhandled instruction. Halt "fast" selection and bail. 716 return false; 717 } 718} 719 720FastISel::FastISel(MachineFunction &mf, 721 MachineModuleInfo *mmi, 722 DwarfWriter *dw, 723 DenseMap<const Value *, unsigned> &vm, 724 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 725 DenseMap<const AllocaInst *, int> &am 726#ifndef NDEBUG 727 , SmallSet<Instruction*, 8> &cil 728#endif 729 ) 730 : MBB(0), 731 ValueMap(vm), 732 MBBMap(bm), 733 StaticAllocaMap(am), 734#ifndef NDEBUG 735 CatchInfoLost(cil), 736#endif 737 MF(mf), 738 MMI(mmi), 739 DW(dw), 740 MRI(MF.getRegInfo()), 741 MFI(*MF.getFrameInfo()), 742 MCP(*MF.getConstantPool()), 743 TM(MF.getTarget()), 744 TD(*TM.getTargetData()), 745 TII(*TM.getInstrInfo()), 746 TLI(*TM.getTargetLowering()) { 747} 748 749FastISel::~FastISel() {} 750 751unsigned FastISel::FastEmit_(MVT, MVT, 752 ISD::NodeType) { 753 return 0; 754} 755 756unsigned FastISel::FastEmit_r(MVT, MVT, 757 ISD::NodeType, unsigned /*Op0*/) { 758 return 0; 759} 760 761unsigned FastISel::FastEmit_rr(MVT, MVT, 762 ISD::NodeType, unsigned /*Op0*/, 763 unsigned /*Op0*/) { 764 return 0; 765} 766 767unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) { 768 return 0; 769} 770 771unsigned FastISel::FastEmit_f(MVT, MVT, 772 ISD::NodeType, ConstantFP * /*FPImm*/) { 773 return 0; 774} 775 776unsigned FastISel::FastEmit_ri(MVT, MVT, 777 ISD::NodeType, unsigned /*Op0*/, 778 uint64_t /*Imm*/) { 779 return 0; 780} 781 782unsigned FastISel::FastEmit_rf(MVT, MVT, 783 ISD::NodeType, unsigned /*Op0*/, 784 ConstantFP * /*FPImm*/) { 785 return 0; 786} 787 788unsigned FastISel::FastEmit_rri(MVT, MVT, 789 ISD::NodeType, 790 unsigned /*Op0*/, unsigned /*Op1*/, 791 uint64_t /*Imm*/) { 792 return 0; 793} 794 795/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 796/// to emit an instruction with an immediate operand using FastEmit_ri. 797/// If that fails, it materializes the immediate into a register and try 798/// FastEmit_rr instead. 799unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode, 800 unsigned Op0, uint64_t Imm, 801 MVT ImmType) { 802 // First check if immediate type is legal. If not, we can't use the ri form. 803 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 804 if (ResultReg != 0) 805 return ResultReg; 806 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 807 if (MaterialReg == 0) 808 return 0; 809 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 810} 811 812/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 813/// to emit an instruction with a floating-point immediate operand using 814/// FastEmit_rf. If that fails, it materializes the immediate into a register 815/// and try FastEmit_rr instead. 816unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode, 817 unsigned Op0, ConstantFP *FPImm, 818 MVT ImmType) { 819 // First check if immediate type is legal. If not, we can't use the rf form. 820 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 821 if (ResultReg != 0) 822 return ResultReg; 823 824 // Materialize the constant in a register. 825 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 826 if (MaterialReg == 0) { 827 // If the target doesn't have a way to directly enter a floating-point 828 // value into a register, use an alternate approach. 829 // TODO: The current approach only supports floating-point constants 830 // that can be constructed by conversion from integer values. This should 831 // be replaced by code that creates a load from a constant-pool entry, 832 // which will require some target-specific work. 833 const APFloat &Flt = FPImm->getValueAPF(); 834 EVT IntVT = TLI.getPointerTy(); 835 836 uint64_t x[2]; 837 uint32_t IntBitWidth = IntVT.getSizeInBits(); 838 bool isExact; 839 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 840 APFloat::rmTowardZero, &isExact); 841 if (!isExact) 842 return 0; 843 APInt IntVal(IntBitWidth, 2, x); 844 845 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 846 ISD::Constant, IntVal.getZExtValue()); 847 if (IntegerReg == 0) 848 return 0; 849 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 850 ISD::SINT_TO_FP, IntegerReg); 851 if (MaterialReg == 0) 852 return 0; 853 } 854 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 855} 856 857unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 858 return MRI.createVirtualRegister(RC); 859} 860 861unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 862 const TargetRegisterClass* RC) { 863 unsigned ResultReg = createResultReg(RC); 864 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 865 866 BuildMI(MBB, DL, II, ResultReg); 867 return ResultReg; 868} 869 870unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 871 const TargetRegisterClass *RC, 872 unsigned Op0) { 873 unsigned ResultReg = createResultReg(RC); 874 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 875 876 if (II.getNumDefs() >= 1) 877 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 878 else { 879 BuildMI(MBB, DL, II).addReg(Op0); 880 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 881 II.ImplicitDefs[0], RC, RC); 882 if (!InsertedCopy) 883 ResultReg = 0; 884 } 885 886 return ResultReg; 887} 888 889unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 890 const TargetRegisterClass *RC, 891 unsigned Op0, unsigned Op1) { 892 unsigned ResultReg = createResultReg(RC); 893 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 894 895 if (II.getNumDefs() >= 1) 896 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 897 else { 898 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 899 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 900 II.ImplicitDefs[0], RC, RC); 901 if (!InsertedCopy) 902 ResultReg = 0; 903 } 904 return ResultReg; 905} 906 907unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 908 const TargetRegisterClass *RC, 909 unsigned Op0, uint64_t Imm) { 910 unsigned ResultReg = createResultReg(RC); 911 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 912 913 if (II.getNumDefs() >= 1) 914 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 915 else { 916 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 917 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 918 II.ImplicitDefs[0], RC, RC); 919 if (!InsertedCopy) 920 ResultReg = 0; 921 } 922 return ResultReg; 923} 924 925unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 926 const TargetRegisterClass *RC, 927 unsigned Op0, ConstantFP *FPImm) { 928 unsigned ResultReg = createResultReg(RC); 929 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 930 931 if (II.getNumDefs() >= 1) 932 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 933 else { 934 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 935 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 936 II.ImplicitDefs[0], RC, RC); 937 if (!InsertedCopy) 938 ResultReg = 0; 939 } 940 return ResultReg; 941} 942 943unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 944 const TargetRegisterClass *RC, 945 unsigned Op0, unsigned Op1, uint64_t Imm) { 946 unsigned ResultReg = createResultReg(RC); 947 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 948 949 if (II.getNumDefs() >= 1) 950 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 951 else { 952 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 953 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 954 II.ImplicitDefs[0], RC, RC); 955 if (!InsertedCopy) 956 ResultReg = 0; 957 } 958 return ResultReg; 959} 960 961unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 962 const TargetRegisterClass *RC, 963 uint64_t Imm) { 964 unsigned ResultReg = createResultReg(RC); 965 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 966 967 if (II.getNumDefs() >= 1) 968 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 969 else { 970 BuildMI(MBB, DL, II).addImm(Imm); 971 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 972 II.ImplicitDefs[0], RC, RC); 973 if (!InsertedCopy) 974 ResultReg = 0; 975 } 976 return ResultReg; 977} 978 979unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 980 unsigned Op0, uint32_t Idx) { 981 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 982 983 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 984 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 985 986 if (II.getNumDefs() >= 1) 987 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 988 else { 989 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 990 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 991 II.ImplicitDefs[0], RC, RC); 992 if (!InsertedCopy) 993 ResultReg = 0; 994 } 995 return ResultReg; 996} 997 998/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 999/// with all but the least significant bit set to zero. 1000unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) { 1001 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 1002} 1003