FastISel.cpp revision 5aa0ddb0f8b15d4d0f3e6385908593e977360812
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuild.h" 57using namespace llvm; 58 59unsigned FastISel::getRegForValue(Value *V) { 60 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT(); 61 62 // Ignore illegal types. We must do this before looking up the value 63 // in ValueMap because Arguments are given virtual registers regardless 64 // of whether FastISel can handle them. 65 if (!TLI.isTypeLegal(VT)) { 66 // Promote MVT::i1 to a legal type though, because it's common and easy. 67 if (VT == MVT::i1) 68 VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); 69 else 70 return 0; 71 } 72 73 // Look up the value to see if we already have a register for it. We 74 // cache values defined by Instructions across blocks, and other values 75 // only locally. This is because Instructions already have the SSA 76 // def-dominatess-use requirement enforced. 77 if (ValueMap.count(V)) 78 return ValueMap[V]; 79 unsigned Reg = LocalValueMap[V]; 80 if (Reg != 0) 81 return Reg; 82 83 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 84 if (CI->getValue().getActiveBits() <= 64) 85 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 86 } else if (isa<AllocaInst>(V)) { 87 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 88 } else if (isa<ConstantPointerNull>(V)) { 89 // Translate this as an integer zero so that it can be 90 // local-CSE'd with actual integer zeros. 91 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType())); 92 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 93 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 94 95 if (!Reg) { 96 const APFloat &Flt = CF->getValueAPF(); 97 MVT IntVT = TLI.getPointerTy(); 98 99 uint64_t x[2]; 100 uint32_t IntBitWidth = IntVT.getSizeInBits(); 101 bool isExact; 102 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 103 APFloat::rmTowardZero, &isExact); 104 if (isExact) { 105 APInt IntVal(IntBitWidth, 2, x); 106 107 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal)); 108 if (IntegerReg != 0) 109 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 110 } 111 } 112 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 113 if (!SelectOperator(CE, CE->getOpcode())) return 0; 114 Reg = LocalValueMap[CE]; 115 } else if (isa<UndefValue>(V)) { 116 Reg = createResultReg(TLI.getRegClassFor(VT)); 117 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 118 } 119 120 // If target-independent code couldn't handle the value, give target-specific 121 // code a try. 122 if (!Reg && isa<Constant>(V)) 123 Reg = TargetMaterializeConstant(cast<Constant>(V)); 124 125 // Don't cache constant materializations in the general ValueMap. 126 // To do so would require tracking what uses they dominate. 127 if (Reg != 0) 128 LocalValueMap[V] = Reg; 129 return Reg; 130} 131 132unsigned FastISel::lookUpRegForValue(Value *V) { 133 // Look up the value to see if we already have a register for it. We 134 // cache values defined by Instructions across blocks, and other values 135 // only locally. This is because Instructions already have the SSA 136 // def-dominatess-use requirement enforced. 137 if (ValueMap.count(V)) 138 return ValueMap[V]; 139 return LocalValueMap[V]; 140} 141 142/// UpdateValueMap - Update the value map to include the new mapping for this 143/// instruction, or insert an extra copy to get the result in a previous 144/// determined register. 145/// NOTE: This is only necessary because we might select a block that uses 146/// a value before we select the block that defines the value. It might be 147/// possible to fix this by selecting blocks in reverse postorder. 148void FastISel::UpdateValueMap(Value* I, unsigned Reg) { 149 if (!isa<Instruction>(I)) { 150 LocalValueMap[I] = Reg; 151 return; 152 } 153 if (!ValueMap.count(I)) 154 ValueMap[I] = Reg; 155 else 156 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I], 157 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg)); 158} 159 160unsigned FastISel::getRegForGEPIndex(Value *Idx) { 161 unsigned IdxN = getRegForValue(Idx); 162 if (IdxN == 0) 163 // Unhandled operand. Halt "fast" selection and bail. 164 return 0; 165 166 // If the index is smaller or larger than intptr_t, truncate or extend it. 167 MVT PtrVT = TLI.getPointerTy(); 168 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); 169 if (IdxVT.bitsLT(PtrVT)) 170 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 171 ISD::SIGN_EXTEND, IdxN); 172 else if (IdxVT.bitsGT(PtrVT)) 173 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), 174 ISD::TRUNCATE, IdxN); 175 return IdxN; 176} 177 178/// SelectBinaryOp - Select and emit code for a binary operator instruction, 179/// which has an opcode which directly corresponds to the given ISD opcode. 180/// 181bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { 182 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); 183 if (VT == MVT::Other || !VT.isSimple()) 184 // Unhandled type. Halt "fast" selection and bail. 185 return false; 186 187 // We only handle legal types. For example, on x86-32 the instruction 188 // selector contains all of the 64-bit instructions from x86-64, 189 // under the assumption that i64 won't be used if the target doesn't 190 // support it. 191 if (!TLI.isTypeLegal(VT)) { 192 // MVT::i1 is special. Allow AND, OR, or XOR because they 193 // don't require additional zeroing, which makes them easy. 194 if (VT == MVT::i1 && 195 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 196 ISDOpcode == ISD::XOR)) 197 VT = TLI.getTypeToTransformTo(VT); 198 else 199 return false; 200 } 201 202 unsigned Op0 = getRegForValue(I->getOperand(0)); 203 if (Op0 == 0) 204 // Unhandled operand. Halt "fast" selection and bail. 205 return false; 206 207 // Check if the second operand is a constant and handle it appropriately. 208 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 209 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 210 ISDOpcode, Op0, CI->getZExtValue()); 211 if (ResultReg != 0) { 212 // We successfully emitted code for the given LLVM Instruction. 213 UpdateValueMap(I, ResultReg); 214 return true; 215 } 216 } 217 218 // Check if the second operand is a constant float. 219 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 220 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 221 ISDOpcode, Op0, CF); 222 if (ResultReg != 0) { 223 // We successfully emitted code for the given LLVM Instruction. 224 UpdateValueMap(I, ResultReg); 225 return true; 226 } 227 } 228 229 unsigned Op1 = getRegForValue(I->getOperand(1)); 230 if (Op1 == 0) 231 // Unhandled operand. Halt "fast" selection and bail. 232 return false; 233 234 // Now we have both operands in registers. Emit the instruction. 235 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 236 ISDOpcode, Op0, Op1); 237 if (ResultReg == 0) 238 // Target-specific code wasn't able to find a machine opcode for 239 // the given ISD opcode and type. Halt "fast" selection and bail. 240 return false; 241 242 // We successfully emitted code for the given LLVM Instruction. 243 UpdateValueMap(I, ResultReg); 244 return true; 245} 246 247bool FastISel::SelectGetElementPtr(User *I) { 248 unsigned N = getRegForValue(I->getOperand(0)); 249 if (N == 0) 250 // Unhandled operand. Halt "fast" selection and bail. 251 return false; 252 253 const Type *Ty = I->getOperand(0)->getType(); 254 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); 255 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 256 OI != E; ++OI) { 257 Value *Idx = *OI; 258 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 259 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 260 if (Field) { 261 // N = N + Offset 262 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 263 // FIXME: This can be optimized by combining the add with a 264 // subsequent one. 265 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 266 if (N == 0) 267 // Unhandled operand. Halt "fast" selection and bail. 268 return false; 269 } 270 Ty = StTy->getElementType(Field); 271 } else { 272 Ty = cast<SequentialType>(Ty)->getElementType(); 273 274 // If this is a constant subscript, handle it quickly. 275 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 276 if (CI->getZExtValue() == 0) continue; 277 uint64_t Offs = 278 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 279 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 280 if (N == 0) 281 // Unhandled operand. Halt "fast" selection and bail. 282 return false; 283 continue; 284 } 285 286 // N = N + Idx * ElementSize; 287 uint64_t ElementSize = TD.getTypePaddedSize(Ty); 288 unsigned IdxN = getRegForGEPIndex(Idx); 289 if (IdxN == 0) 290 // Unhandled operand. Halt "fast" selection and bail. 291 return false; 292 293 if (ElementSize != 1) { 294 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 295 if (IdxN == 0) 296 // Unhandled operand. Halt "fast" selection and bail. 297 return false; 298 } 299 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 300 if (N == 0) 301 // Unhandled operand. Halt "fast" selection and bail. 302 return false; 303 } 304 } 305 306 // We successfully emitted code for the given LLVM Instruction. 307 UpdateValueMap(I, N); 308 return true; 309} 310 311bool FastISel::SelectCall(User *I) { 312 Function *F = cast<CallInst>(I)->getCalledFunction(); 313 if (!F) return false; 314 315 unsigned IID = F->getIntrinsicID(); 316 switch (IID) { 317 default: break; 318 case Intrinsic::dbg_stoppoint: { 319 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I); 320 if (DW && DW->ValidDebugInfo(SPI->getContext())) { 321 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext())); 322 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), 323 CU.getFilename()); 324 unsigned Line = SPI->getLine(); 325 unsigned Col = SPI->getColumn(); 326 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 327 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col); 328 setCurDebugLoc(DebugLoc::get(Idx)); 329 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 330 BuildMI(MBB, DL, II).addImm(ID); 331 } 332 return true; 333 } 334 case Intrinsic::dbg_region_start: { 335 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I); 336 if (DW && DW->ValidDebugInfo(RSI->getContext())) { 337 unsigned ID = 338 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext())); 339 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 340 BuildMI(MBB, DL, II).addImm(ID); 341 } 342 return true; 343 } 344 case Intrinsic::dbg_region_end: { 345 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I); 346 if (DW && DW->ValidDebugInfo(REI->getContext())) { 347 unsigned ID = 348 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext())); 349 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 350 BuildMI(MBB, DL, II).addImm(ID); 351 } 352 return true; 353 } 354 case Intrinsic::dbg_func_start: { 355 if (!DW) return true; 356 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I); 357 Value *SP = FSI->getSubprogram(); 358 359 if (DW->ValidDebugInfo(SP)) { 360 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what 361 // (most?) gdb expects. 362 DISubprogram Subprogram(cast<GlobalVariable>(SP)); 363 DICompileUnit CompileUnit = Subprogram.getCompileUnit(); 364 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(), 365 CompileUnit.getFilename()); 366 367 // Record the source line but does not create a label for the normal 368 // function start. It will be emitted at asm emission time. However, 369 // create a label if this is a beginning of inlined function. 370 unsigned Line = Subprogram.getLineNumber(); 371 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile); 372 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0))); 373 374 if (DW->getRecordSourceLineCount() != 1) { 375 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL); 376 BuildMI(MBB, DL, II).addImm(LabelID); 377 } 378 } 379 380 return true; 381 } 382 case Intrinsic::dbg_declare: { 383 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 384 Value *Variable = DI->getVariable(); 385 if (DW && DW->ValidDebugInfo(Variable)) { 386 // Determine the address of the declared object. 387 Value *Address = DI->getAddress(); 388 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 389 Address = BCI->getOperand(0); 390 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 391 // Don't handle byval struct arguments, for example. 392 if (!AI) break; 393 DenseMap<const AllocaInst*, int>::iterator SI = 394 StaticAllocaMap.find(AI); 395 assert(SI != StaticAllocaMap.end() && "Invalid dbg.declare!"); 396 int FI = SI->second; 397 398 // Determine the debug globalvariable. 399 GlobalValue *GV = cast<GlobalVariable>(Variable); 400 401 // Build the DECLARE instruction. 402 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE); 403 BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV); 404 } 405 return true; 406 } 407 case Intrinsic::eh_exception: { 408 MVT VT = TLI.getValueType(I->getType()); 409 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 410 default: break; 411 case TargetLowering::Expand: { 412 if (!MBB->isLandingPad()) { 413 // FIXME: Mark exception register as live in. Hack for PR1508. 414 unsigned Reg = TLI.getExceptionAddressRegister(); 415 if (Reg) MBB->addLiveIn(Reg); 416 } 417 unsigned Reg = TLI.getExceptionAddressRegister(); 418 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 419 unsigned ResultReg = createResultReg(RC); 420 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 421 Reg, RC, RC); 422 assert(InsertedCopy && "Can't copy address registers!"); 423 InsertedCopy = InsertedCopy; 424 UpdateValueMap(I, ResultReg); 425 return true; 426 } 427 } 428 break; 429 } 430 case Intrinsic::eh_selector_i32: 431 case Intrinsic::eh_selector_i64: { 432 MVT VT = TLI.getValueType(I->getType()); 433 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 434 default: break; 435 case TargetLowering::Expand: { 436 MVT VT = (IID == Intrinsic::eh_selector_i32 ? 437 MVT::i32 : MVT::i64); 438 439 if (MMI) { 440 if (MBB->isLandingPad()) 441 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 442 else { 443#ifndef NDEBUG 444 CatchInfoLost.insert(cast<CallInst>(I)); 445#endif 446 // FIXME: Mark exception selector register as live in. Hack for PR1508. 447 unsigned Reg = TLI.getExceptionSelectorRegister(); 448 if (Reg) MBB->addLiveIn(Reg); 449 } 450 451 unsigned Reg = TLI.getExceptionSelectorRegister(); 452 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 453 unsigned ResultReg = createResultReg(RC); 454 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 455 Reg, RC, RC); 456 assert(InsertedCopy && "Can't copy address registers!"); 457 InsertedCopy = InsertedCopy; 458 UpdateValueMap(I, ResultReg); 459 } else { 460 unsigned ResultReg = 461 getRegForValue(Constant::getNullValue(I->getType())); 462 UpdateValueMap(I, ResultReg); 463 } 464 return true; 465 } 466 } 467 break; 468 } 469 } 470 return false; 471} 472 473bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { 474 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 475 MVT DstVT = TLI.getValueType(I->getType()); 476 477 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 478 DstVT == MVT::Other || !DstVT.isSimple() || 479 !TLI.isTypeLegal(DstVT)) 480 // Unhandled type. Halt "fast" selection and bail. 481 return false; 482 483 // Check if the source operand is legal. Or as a special case, 484 // it may be i1 if we're doing zero-extension because that's 485 // trivially easy and somewhat common. 486 if (!TLI.isTypeLegal(SrcVT)) { 487 if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND) 488 SrcVT = TLI.getTypeToTransformTo(SrcVT); 489 else 490 // Unhandled type. Halt "fast" selection and bail. 491 return false; 492 } 493 494 unsigned InputReg = getRegForValue(I->getOperand(0)); 495 if (!InputReg) 496 // Unhandled operand. Halt "fast" selection and bail. 497 return false; 498 499 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 500 DstVT.getSimpleVT(), 501 Opcode, 502 InputReg); 503 if (!ResultReg) 504 return false; 505 506 UpdateValueMap(I, ResultReg); 507 return true; 508} 509 510bool FastISel::SelectBitCast(User *I) { 511 // If the bitcast doesn't change the type, just use the operand value. 512 if (I->getType() == I->getOperand(0)->getType()) { 513 unsigned Reg = getRegForValue(I->getOperand(0)); 514 if (Reg == 0) 515 return false; 516 UpdateValueMap(I, Reg); 517 return true; 518 } 519 520 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 521 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 522 MVT DstVT = TLI.getValueType(I->getType()); 523 524 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 525 DstVT == MVT::Other || !DstVT.isSimple() || 526 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 527 // Unhandled type. Halt "fast" selection and bail. 528 return false; 529 530 unsigned Op0 = getRegForValue(I->getOperand(0)); 531 if (Op0 == 0) 532 // Unhandled operand. Halt "fast" selection and bail. 533 return false; 534 535 // First, try to perform the bitcast by inserting a reg-reg copy. 536 unsigned ResultReg = 0; 537 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 538 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 539 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 540 ResultReg = createResultReg(DstClass); 541 542 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 543 Op0, DstClass, SrcClass); 544 if (!InsertedCopy) 545 ResultReg = 0; 546 } 547 548 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 549 if (!ResultReg) 550 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 551 ISD::BIT_CONVERT, Op0); 552 553 if (!ResultReg) 554 return false; 555 556 UpdateValueMap(I, ResultReg); 557 return true; 558} 559 560bool 561FastISel::SelectInstruction(Instruction *I) { 562 return SelectOperator(I, I->getOpcode()); 563} 564 565/// FastEmitBranch - Emit an unconditional branch to the given block, 566/// unless it is the immediate (fall-through) successor, and update 567/// the CFG. 568void 569FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 570 MachineFunction::iterator NextMBB = 571 next(MachineFunction::iterator(MBB)); 572 573 if (MBB->isLayoutSuccessor(MSucc)) { 574 // The unconditional fall-through case, which needs no instructions. 575 } else { 576 // The unconditional branch case. 577 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 578 } 579 MBB->addSuccessor(MSucc); 580} 581 582bool 583FastISel::SelectOperator(User *I, unsigned Opcode) { 584 switch (Opcode) { 585 case Instruction::Add: { 586 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; 587 return SelectBinaryOp(I, Opc); 588 } 589 case Instruction::Sub: { 590 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; 591 return SelectBinaryOp(I, Opc); 592 } 593 case Instruction::Mul: { 594 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; 595 return SelectBinaryOp(I, Opc); 596 } 597 case Instruction::SDiv: 598 return SelectBinaryOp(I, ISD::SDIV); 599 case Instruction::UDiv: 600 return SelectBinaryOp(I, ISD::UDIV); 601 case Instruction::FDiv: 602 return SelectBinaryOp(I, ISD::FDIV); 603 case Instruction::SRem: 604 return SelectBinaryOp(I, ISD::SREM); 605 case Instruction::URem: 606 return SelectBinaryOp(I, ISD::UREM); 607 case Instruction::FRem: 608 return SelectBinaryOp(I, ISD::FREM); 609 case Instruction::Shl: 610 return SelectBinaryOp(I, ISD::SHL); 611 case Instruction::LShr: 612 return SelectBinaryOp(I, ISD::SRL); 613 case Instruction::AShr: 614 return SelectBinaryOp(I, ISD::SRA); 615 case Instruction::And: 616 return SelectBinaryOp(I, ISD::AND); 617 case Instruction::Or: 618 return SelectBinaryOp(I, ISD::OR); 619 case Instruction::Xor: 620 return SelectBinaryOp(I, ISD::XOR); 621 622 case Instruction::GetElementPtr: 623 return SelectGetElementPtr(I); 624 625 case Instruction::Br: { 626 BranchInst *BI = cast<BranchInst>(I); 627 628 if (BI->isUnconditional()) { 629 BasicBlock *LLVMSucc = BI->getSuccessor(0); 630 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 631 FastEmitBranch(MSucc); 632 return true; 633 } 634 635 // Conditional branches are not handed yet. 636 // Halt "fast" selection and bail. 637 return false; 638 } 639 640 case Instruction::Unreachable: 641 // Nothing to emit. 642 return true; 643 644 case Instruction::PHI: 645 // PHI nodes are already emitted. 646 return true; 647 648 case Instruction::Alloca: 649 // FunctionLowering has the static-sized case covered. 650 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 651 return true; 652 653 // Dynamic-sized alloca is not handled yet. 654 return false; 655 656 case Instruction::Call: 657 return SelectCall(I); 658 659 case Instruction::BitCast: 660 return SelectBitCast(I); 661 662 case Instruction::FPToSI: 663 return SelectCast(I, ISD::FP_TO_SINT); 664 case Instruction::ZExt: 665 return SelectCast(I, ISD::ZERO_EXTEND); 666 case Instruction::SExt: 667 return SelectCast(I, ISD::SIGN_EXTEND); 668 case Instruction::Trunc: 669 return SelectCast(I, ISD::TRUNCATE); 670 case Instruction::SIToFP: 671 return SelectCast(I, ISD::SINT_TO_FP); 672 673 case Instruction::IntToPtr: // Deliberate fall-through. 674 case Instruction::PtrToInt: { 675 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 676 MVT DstVT = TLI.getValueType(I->getType()); 677 if (DstVT.bitsGT(SrcVT)) 678 return SelectCast(I, ISD::ZERO_EXTEND); 679 if (DstVT.bitsLT(SrcVT)) 680 return SelectCast(I, ISD::TRUNCATE); 681 unsigned Reg = getRegForValue(I->getOperand(0)); 682 if (Reg == 0) return false; 683 UpdateValueMap(I, Reg); 684 return true; 685 } 686 687 default: 688 // Unhandled instruction. Halt "fast" selection and bail. 689 return false; 690 } 691} 692 693FastISel::FastISel(MachineFunction &mf, 694 MachineModuleInfo *mmi, 695 DwarfWriter *dw, 696 DenseMap<const Value *, unsigned> &vm, 697 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 698 DenseMap<const AllocaInst *, int> &am 699#ifndef NDEBUG 700 , SmallSet<Instruction*, 8> &cil 701#endif 702 ) 703 : MBB(0), 704 ValueMap(vm), 705 MBBMap(bm), 706 StaticAllocaMap(am), 707#ifndef NDEBUG 708 CatchInfoLost(cil), 709#endif 710 MF(mf), 711 MMI(mmi), 712 DW(dw), 713 MRI(MF.getRegInfo()), 714 MFI(*MF.getFrameInfo()), 715 MCP(*MF.getConstantPool()), 716 TM(MF.getTarget()), 717 TD(*TM.getTargetData()), 718 TII(*TM.getInstrInfo()), 719 TLI(*TM.getTargetLowering()) { 720} 721 722FastISel::~FastISel() {} 723 724unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, 725 ISD::NodeType) { 726 return 0; 727} 728 729unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, 730 ISD::NodeType, unsigned /*Op0*/) { 731 return 0; 732} 733 734unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 735 ISD::NodeType, unsigned /*Op0*/, 736 unsigned /*Op0*/) { 737 return 0; 738} 739 740unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, 741 ISD::NodeType, uint64_t /*Imm*/) { 742 return 0; 743} 744 745unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, 746 ISD::NodeType, ConstantFP * /*FPImm*/) { 747 return 0; 748} 749 750unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, 751 ISD::NodeType, unsigned /*Op0*/, 752 uint64_t /*Imm*/) { 753 return 0; 754} 755 756unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, 757 ISD::NodeType, unsigned /*Op0*/, 758 ConstantFP * /*FPImm*/) { 759 return 0; 760} 761 762unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, 763 ISD::NodeType, 764 unsigned /*Op0*/, unsigned /*Op1*/, 765 uint64_t /*Imm*/) { 766 return 0; 767} 768 769/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 770/// to emit an instruction with an immediate operand using FastEmit_ri. 771/// If that fails, it materializes the immediate into a register and try 772/// FastEmit_rr instead. 773unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 774 unsigned Op0, uint64_t Imm, 775 MVT::SimpleValueType ImmType) { 776 // First check if immediate type is legal. If not, we can't use the ri form. 777 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 778 if (ResultReg != 0) 779 return ResultReg; 780 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 781 if (MaterialReg == 0) 782 return 0; 783 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 784} 785 786/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 787/// to emit an instruction with a floating-point immediate operand using 788/// FastEmit_rf. If that fails, it materializes the immediate into a register 789/// and try FastEmit_rr instead. 790unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, 791 unsigned Op0, ConstantFP *FPImm, 792 MVT::SimpleValueType ImmType) { 793 // First check if immediate type is legal. If not, we can't use the rf form. 794 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 795 if (ResultReg != 0) 796 return ResultReg; 797 798 // Materialize the constant in a register. 799 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 800 if (MaterialReg == 0) { 801 // If the target doesn't have a way to directly enter a floating-point 802 // value into a register, use an alternate approach. 803 // TODO: The current approach only supports floating-point constants 804 // that can be constructed by conversion from integer values. This should 805 // be replaced by code that creates a load from a constant-pool entry, 806 // which will require some target-specific work. 807 const APFloat &Flt = FPImm->getValueAPF(); 808 MVT IntVT = TLI.getPointerTy(); 809 810 uint64_t x[2]; 811 uint32_t IntBitWidth = IntVT.getSizeInBits(); 812 bool isExact; 813 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 814 APFloat::rmTowardZero, &isExact); 815 if (!isExact) 816 return 0; 817 APInt IntVal(IntBitWidth, 2, x); 818 819 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 820 ISD::Constant, IntVal.getZExtValue()); 821 if (IntegerReg == 0) 822 return 0; 823 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 824 ISD::SINT_TO_FP, IntegerReg); 825 if (MaterialReg == 0) 826 return 0; 827 } 828 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 829} 830 831unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 832 return MRI.createVirtualRegister(RC); 833} 834 835unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 836 const TargetRegisterClass* RC) { 837 unsigned ResultReg = createResultReg(RC); 838 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 839 840 BuildMI(MBB, DL, II, ResultReg); 841 return ResultReg; 842} 843 844unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 845 const TargetRegisterClass *RC, 846 unsigned Op0) { 847 unsigned ResultReg = createResultReg(RC); 848 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 849 850 if (II.getNumDefs() >= 1) 851 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 852 else { 853 BuildMI(MBB, DL, II).addReg(Op0); 854 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 855 II.ImplicitDefs[0], RC, RC); 856 if (!InsertedCopy) 857 ResultReg = 0; 858 } 859 860 return ResultReg; 861} 862 863unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 864 const TargetRegisterClass *RC, 865 unsigned Op0, unsigned Op1) { 866 unsigned ResultReg = createResultReg(RC); 867 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 868 869 if (II.getNumDefs() >= 1) 870 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 871 else { 872 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 873 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 874 II.ImplicitDefs[0], RC, RC); 875 if (!InsertedCopy) 876 ResultReg = 0; 877 } 878 return ResultReg; 879} 880 881unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 882 const TargetRegisterClass *RC, 883 unsigned Op0, uint64_t Imm) { 884 unsigned ResultReg = createResultReg(RC); 885 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 886 887 if (II.getNumDefs() >= 1) 888 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 889 else { 890 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 891 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 892 II.ImplicitDefs[0], RC, RC); 893 if (!InsertedCopy) 894 ResultReg = 0; 895 } 896 return ResultReg; 897} 898 899unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 900 const TargetRegisterClass *RC, 901 unsigned Op0, ConstantFP *FPImm) { 902 unsigned ResultReg = createResultReg(RC); 903 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 904 905 if (II.getNumDefs() >= 1) 906 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 907 else { 908 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 909 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 910 II.ImplicitDefs[0], RC, RC); 911 if (!InsertedCopy) 912 ResultReg = 0; 913 } 914 return ResultReg; 915} 916 917unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 918 const TargetRegisterClass *RC, 919 unsigned Op0, unsigned Op1, uint64_t Imm) { 920 unsigned ResultReg = createResultReg(RC); 921 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 922 923 if (II.getNumDefs() >= 1) 924 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 925 else { 926 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 927 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 928 II.ImplicitDefs[0], RC, RC); 929 if (!InsertedCopy) 930 ResultReg = 0; 931 } 932 return ResultReg; 933} 934 935unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 936 const TargetRegisterClass *RC, 937 uint64_t Imm) { 938 unsigned ResultReg = createResultReg(RC); 939 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 940 941 if (II.getNumDefs() >= 1) 942 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 943 else { 944 BuildMI(MBB, DL, II).addImm(Imm); 945 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 946 II.ImplicitDefs[0], RC, RC); 947 if (!InsertedCopy) 948 ResultReg = 0; 949 } 950 return ResultReg; 951} 952 953unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, 954 unsigned Op0, uint32_t Idx) { 955 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 956 957 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 958 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 959 960 if (II.getNumDefs() >= 1) 961 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 962 else { 963 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 964 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 965 II.ImplicitDefs[0], RC, RC); 966 if (!InsertedCopy) 967 ResultReg = 0; 968 } 969 return ResultReg; 970} 971