FastISel.cpp revision 5f03238d629c32bb0bab78d112a42293838558e9
1///===-- FastISel.cpp - Implementation of the FastISel class --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/CodeGen/FastISel.h" 47#include "llvm/CodeGen/MachineInstrBuilder.h" 48#include "llvm/CodeGen/MachineModuleInfo.h" 49#include "llvm/CodeGen/MachineRegisterInfo.h" 50#include "llvm/CodeGen/DwarfWriter.h" 51#include "llvm/Analysis/DebugInfo.h" 52#include "llvm/Target/TargetData.h" 53#include "llvm/Target/TargetInstrInfo.h" 54#include "llvm/Target/TargetLowering.h" 55#include "llvm/Target/TargetMachine.h" 56#include "SelectionDAGBuilder.h" 57#include "FunctionLoweringInfo.h" 58using namespace llvm; 59 60unsigned FastISel::getRegForValue(Value *V) { 61 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 62 // Don't handle non-simple values in FastISel. 63 if (!RealVT.isSimple()) 64 return 0; 65 66 // Ignore illegal types. We must do this before looking up the value 67 // in ValueMap because Arguments are given virtual registers regardless 68 // of whether FastISel can handle them. 69 MVT VT = RealVT.getSimpleVT(); 70 if (!TLI.isTypeLegal(VT)) { 71 // Promote MVT::i1 to a legal type though, because it's common and easy. 72 if (VT == MVT::i1) 73 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 74 else 75 return 0; 76 } 77 78 // Look up the value to see if we already have a register for it. We 79 // cache values defined by Instructions across blocks, and other values 80 // only locally. This is because Instructions already have the SSA 81 // def-dominates-use requirement enforced. 82 if (ValueMap.count(V)) 83 return ValueMap[V]; 84 unsigned Reg = LocalValueMap[V]; 85 if (Reg != 0) 86 return Reg; 87 88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 89 if (CI->getValue().getActiveBits() <= 64) 90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 91 } else if (isa<AllocaInst>(V)) { 92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 93 } else if (isa<ConstantPointerNull>(V)) { 94 // Translate this as an integer zero so that it can be 95 // local-CSE'd with actual integer zeros. 96 Reg = 97 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 98 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 99 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 100 101 if (!Reg) { 102 const APFloat &Flt = CF->getValueAPF(); 103 EVT IntVT = TLI.getPointerTy(); 104 105 uint64_t x[2]; 106 uint32_t IntBitWidth = IntVT.getSizeInBits(); 107 bool isExact; 108 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 109 APFloat::rmTowardZero, &isExact); 110 if (isExact) { 111 APInt IntVal(IntBitWidth, 2, x); 112 113 unsigned IntegerReg = 114 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 115 if (IntegerReg != 0) 116 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); 117 } 118 } 119 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) { 120 if (!SelectOperator(CE, CE->getOpcode())) return 0; 121 Reg = LocalValueMap[CE]; 122 } else if (isa<UndefValue>(V)) { 123 Reg = createResultReg(TLI.getRegClassFor(VT)); 124 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); 125 } 126 127 // If target-independent code couldn't handle the value, give target-specific 128 // code a try. 129 if (!Reg && isa<Constant>(V)) 130 Reg = TargetMaterializeConstant(cast<Constant>(V)); 131 132 // Don't cache constant materializations in the general ValueMap. 133 // To do so would require tracking what uses they dominate. 134 if (Reg != 0) 135 LocalValueMap[V] = Reg; 136 return Reg; 137} 138 139unsigned FastISel::lookUpRegForValue(Value *V) { 140 // Look up the value to see if we already have a register for it. We 141 // cache values defined by Instructions across blocks, and other values 142 // only locally. This is because Instructions already have the SSA 143 // def-dominatess-use requirement enforced. 144 if (ValueMap.count(V)) 145 return ValueMap[V]; 146 return LocalValueMap[V]; 147} 148 149/// UpdateValueMap - Update the value map to include the new mapping for this 150/// instruction, or insert an extra copy to get the result in a previous 151/// determined register. 152/// NOTE: This is only necessary because we might select a block that uses 153/// a value before we select the block that defines the value. It might be 154/// possible to fix this by selecting blocks in reverse postorder. 155unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) { 156 if (!isa<Instruction>(I)) { 157 LocalValueMap[I] = Reg; 158 return Reg; 159 } 160 161 unsigned &AssignedReg = ValueMap[I]; 162 if (AssignedReg == 0) 163 AssignedReg = Reg; 164 else if (Reg != AssignedReg) { 165 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); 166 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg, 167 Reg, RegClass, RegClass); 168 } 169 return AssignedReg; 170} 171 172unsigned FastISel::getRegForGEPIndex(Value *Idx) { 173 unsigned IdxN = getRegForValue(Idx); 174 if (IdxN == 0) 175 // Unhandled operand. Halt "fast" selection and bail. 176 return 0; 177 178 // If the index is smaller or larger than intptr_t, truncate or extend it. 179 MVT PtrVT = TLI.getPointerTy(); 180 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 181 if (IdxVT.bitsLT(PtrVT)) 182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); 183 else if (IdxVT.bitsGT(PtrVT)) 184 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); 185 return IdxN; 186} 187 188/// SelectBinaryOp - Select and emit code for a binary operator instruction, 189/// which has an opcode which directly corresponds to the given ISD opcode. 190/// 191bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) { 192 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 193 if (VT == MVT::Other || !VT.isSimple()) 194 // Unhandled type. Halt "fast" selection and bail. 195 return false; 196 197 // We only handle legal types. For example, on x86-32 the instruction 198 // selector contains all of the 64-bit instructions from x86-64, 199 // under the assumption that i64 won't be used if the target doesn't 200 // support it. 201 if (!TLI.isTypeLegal(VT)) { 202 // MVT::i1 is special. Allow AND, OR, or XOR because they 203 // don't require additional zeroing, which makes them easy. 204 if (VT == MVT::i1 && 205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 206 ISDOpcode == ISD::XOR)) 207 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 208 else 209 return false; 210 } 211 212 unsigned Op0 = getRegForValue(I->getOperand(0)); 213 if (Op0 == 0) 214 // Unhandled operand. Halt "fast" selection and bail. 215 return false; 216 217 // Check if the second operand is a constant and handle it appropriately. 218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), 220 ISDOpcode, Op0, CI->getZExtValue()); 221 if (ResultReg != 0) { 222 // We successfully emitted code for the given LLVM Instruction. 223 UpdateValueMap(I, ResultReg); 224 return true; 225 } 226 } 227 228 // Check if the second operand is a constant float. 229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 231 ISDOpcode, Op0, CF); 232 if (ResultReg != 0) { 233 // We successfully emitted code for the given LLVM Instruction. 234 UpdateValueMap(I, ResultReg); 235 return true; 236 } 237 } 238 239 unsigned Op1 = getRegForValue(I->getOperand(1)); 240 if (Op1 == 0) 241 // Unhandled operand. Halt "fast" selection and bail. 242 return false; 243 244 // Now we have both operands in registers. Emit the instruction. 245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 246 ISDOpcode, Op0, Op1); 247 if (ResultReg == 0) 248 // Target-specific code wasn't able to find a machine opcode for 249 // the given ISD opcode and type. Halt "fast" selection and bail. 250 return false; 251 252 // We successfully emitted code for the given LLVM Instruction. 253 UpdateValueMap(I, ResultReg); 254 return true; 255} 256 257bool FastISel::SelectGetElementPtr(User *I) { 258 unsigned N = getRegForValue(I->getOperand(0)); 259 if (N == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return false; 262 263 const Type *Ty = I->getOperand(0)->getType(); 264 MVT VT = TLI.getPointerTy(); 265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); 266 OI != E; ++OI) { 267 Value *Idx = *OI; 268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 270 if (Field) { 271 // N = N + Offset 272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 273 // FIXME: This can be optimized by combining the add with a 274 // subsequent one. 275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 276 if (N == 0) 277 // Unhandled operand. Halt "fast" selection and bail. 278 return false; 279 } 280 Ty = StTy->getElementType(Field); 281 } else { 282 Ty = cast<SequentialType>(Ty)->getElementType(); 283 284 // If this is a constant subscript, handle it quickly. 285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 286 if (CI->getZExtValue() == 0) continue; 287 uint64_t Offs = 288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); 290 if (N == 0) 291 // Unhandled operand. Halt "fast" selection and bail. 292 return false; 293 continue; 294 } 295 296 // N = N + Idx * ElementSize; 297 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 298 unsigned IdxN = getRegForGEPIndex(Idx); 299 if (IdxN == 0) 300 // Unhandled operand. Halt "fast" selection and bail. 301 return false; 302 303 if (ElementSize != 1) { 304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); 305 if (IdxN == 0) 306 // Unhandled operand. Halt "fast" selection and bail. 307 return false; 308 } 309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); 310 if (N == 0) 311 // Unhandled operand. Halt "fast" selection and bail. 312 return false; 313 } 314 } 315 316 // We successfully emitted code for the given LLVM Instruction. 317 UpdateValueMap(I, N); 318 return true; 319} 320 321bool FastISel::SelectCall(User *I) { 322 Function *F = cast<CallInst>(I)->getCalledFunction(); 323 if (!F) return false; 324 325 unsigned IID = F->getIntrinsicID(); 326 switch (IID) { 327 default: break; 328 case Intrinsic::dbg_declare: { 329 DbgDeclareInst *DI = cast<DbgDeclareInst>(I); 330 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW 331 || !DW->ShouldEmitDwarfDebug()) 332 return true; 333 334 Value *Address = DI->getAddress(); 335 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 336 Address = BCI->getOperand(0); 337 AllocaInst *AI = dyn_cast<AllocaInst>(Address); 338 // Don't handle byval struct arguments or VLAs, for example. 339 if (!AI) break; 340 DenseMap<const AllocaInst*, int>::iterator SI = 341 StaticAllocaMap.find(AI); 342 if (SI == StaticAllocaMap.end()) break; // VLAs. 343 int FI = SI->second; 344 if (MMI) { 345 if (MDNode *Dbg = DI->getMetadata("dbg")) 346 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg); 347 } 348 return true; 349 } 350 case Intrinsic::eh_exception: { 351 EVT VT = TLI.getValueType(I->getType()); 352 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { 353 default: break; 354 case TargetLowering::Expand: { 355 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!"); 356 unsigned Reg = TLI.getExceptionAddressRegister(); 357 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 358 unsigned ResultReg = createResultReg(RC); 359 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 360 Reg, RC, RC); 361 assert(InsertedCopy && "Can't copy address registers!"); 362 InsertedCopy = InsertedCopy; 363 UpdateValueMap(I, ResultReg); 364 return true; 365 } 366 } 367 break; 368 } 369 case Intrinsic::eh_selector: { 370 EVT VT = TLI.getValueType(I->getType()); 371 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { 372 default: break; 373 case TargetLowering::Expand: { 374 if (MMI) { 375 if (MBB->isLandingPad()) 376 AddCatchInfo(*cast<CallInst>(I), MMI, MBB); 377 else { 378#ifndef NDEBUG 379 CatchInfoLost.insert(cast<CallInst>(I)); 380#endif 381 // FIXME: Mark exception selector register as live in. Hack for PR1508. 382 unsigned Reg = TLI.getExceptionSelectorRegister(); 383 if (Reg) MBB->addLiveIn(Reg); 384 } 385 386 unsigned Reg = TLI.getExceptionSelectorRegister(); 387 EVT SrcVT = TLI.getPointerTy(); 388 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 389 unsigned ResultReg = createResultReg(RC); 390 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg, 391 RC, RC); 392 assert(InsertedCopy && "Can't copy address registers!"); 393 InsertedCopy = InsertedCopy; 394 395 // Cast the register to the type of the selector. 396 if (SrcVT.bitsGT(MVT::i32)) 397 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 398 ResultReg); 399 else if (SrcVT.bitsLT(MVT::i32)) 400 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 401 ISD::SIGN_EXTEND, ResultReg); 402 if (ResultReg == 0) 403 // Unhandled operand. Halt "fast" selection and bail. 404 return false; 405 406 UpdateValueMap(I, ResultReg); 407 } else { 408 unsigned ResultReg = 409 getRegForValue(Constant::getNullValue(I->getType())); 410 UpdateValueMap(I, ResultReg); 411 } 412 return true; 413 } 414 } 415 break; 416 } 417 } 418 return false; 419} 420 421bool FastISel::SelectCast(User *I, unsigned Opcode) { 422 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 423 EVT DstVT = TLI.getValueType(I->getType()); 424 425 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 426 DstVT == MVT::Other || !DstVT.isSimple()) 427 // Unhandled type. Halt "fast" selection and bail. 428 return false; 429 430 // Check if the destination type is legal. Or as a special case, 431 // it may be i1 if we're doing a truncate because that's 432 // easy and somewhat common. 433 if (!TLI.isTypeLegal(DstVT)) 434 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) 435 // Unhandled type. Halt "fast" selection and bail. 436 return false; 437 438 // Check if the source operand is legal. Or as a special case, 439 // it may be i1 if we're doing zero-extension because that's 440 // easy and somewhat common. 441 if (!TLI.isTypeLegal(SrcVT)) 442 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) 443 // Unhandled type. Halt "fast" selection and bail. 444 return false; 445 446 unsigned InputReg = getRegForValue(I->getOperand(0)); 447 if (!InputReg) 448 // Unhandled operand. Halt "fast" selection and bail. 449 return false; 450 451 // If the operand is i1, arrange for the high bits in the register to be zero. 452 if (SrcVT == MVT::i1) { 453 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT); 454 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); 455 if (!InputReg) 456 return false; 457 } 458 // If the result is i1, truncate to the target's type for i1 first. 459 if (DstVT == MVT::i1) 460 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT); 461 462 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 463 DstVT.getSimpleVT(), 464 Opcode, 465 InputReg); 466 if (!ResultReg) 467 return false; 468 469 UpdateValueMap(I, ResultReg); 470 return true; 471} 472 473bool FastISel::SelectBitCast(User *I) { 474 // If the bitcast doesn't change the type, just use the operand value. 475 if (I->getType() == I->getOperand(0)->getType()) { 476 unsigned Reg = getRegForValue(I->getOperand(0)); 477 if (Reg == 0) 478 return false; 479 UpdateValueMap(I, Reg); 480 return true; 481 } 482 483 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. 484 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 485 EVT DstVT = TLI.getValueType(I->getType()); 486 487 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 488 DstVT == MVT::Other || !DstVT.isSimple() || 489 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 490 // Unhandled type. Halt "fast" selection and bail. 491 return false; 492 493 unsigned Op0 = getRegForValue(I->getOperand(0)); 494 if (Op0 == 0) 495 // Unhandled operand. Halt "fast" selection and bail. 496 return false; 497 498 // First, try to perform the bitcast by inserting a reg-reg copy. 499 unsigned ResultReg = 0; 500 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 501 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 502 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 503 ResultReg = createResultReg(DstClass); 504 505 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 506 Op0, DstClass, SrcClass); 507 if (!InsertedCopy) 508 ResultReg = 0; 509 } 510 511 // If the reg-reg copy failed, select a BIT_CONVERT opcode. 512 if (!ResultReg) 513 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 514 ISD::BIT_CONVERT, Op0); 515 516 if (!ResultReg) 517 return false; 518 519 UpdateValueMap(I, ResultReg); 520 return true; 521} 522 523bool 524FastISel::SelectInstruction(Instruction *I) { 525 // First, try doing target-independent selection. 526 if (SelectOperator(I, I->getOpcode())) 527 return true; 528 529 // Next, try calling the target to attempt to handle the instruction. 530 if (TargetSelectInstruction(I)) 531 return true; 532 533 return false; 534} 535 536/// FastEmitBranch - Emit an unconditional branch to the given block, 537/// unless it is the immediate (fall-through) successor, and update 538/// the CFG. 539void 540FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { 541 if (MBB->isLayoutSuccessor(MSucc)) { 542 // The unconditional fall-through case, which needs no instructions. 543 } else { 544 // The unconditional branch case. 545 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); 546 } 547 MBB->addSuccessor(MSucc); 548} 549 550/// SelectFNeg - Emit an FNeg operation. 551/// 552bool 553FastISel::SelectFNeg(User *I) { 554 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 555 if (OpReg == 0) return false; 556 557 // If the target has ISD::FNEG, use it. 558 EVT VT = TLI.getValueType(I->getType()); 559 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 560 ISD::FNEG, OpReg); 561 if (ResultReg != 0) { 562 UpdateValueMap(I, ResultReg); 563 return true; 564 } 565 566 // Bitcast the value to integer, twiddle the sign bit with xor, 567 // and then bitcast it back to floating-point. 568 if (VT.getSizeInBits() > 64) return false; 569 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 570 if (!TLI.isTypeLegal(IntVT)) 571 return false; 572 573 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 574 ISD::BIT_CONVERT, OpReg); 575 if (IntReg == 0) 576 return false; 577 578 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg, 579 UINT64_C(1) << (VT.getSizeInBits()-1), 580 IntVT.getSimpleVT()); 581 if (IntResultReg == 0) 582 return false; 583 584 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 585 ISD::BIT_CONVERT, IntResultReg); 586 if (ResultReg == 0) 587 return false; 588 589 UpdateValueMap(I, ResultReg); 590 return true; 591} 592 593bool 594FastISel::SelectOperator(User *I, unsigned Opcode) { 595 switch (Opcode) { 596 case Instruction::Add: 597 return SelectBinaryOp(I, ISD::ADD); 598 case Instruction::FAdd: 599 return SelectBinaryOp(I, ISD::FADD); 600 case Instruction::Sub: 601 return SelectBinaryOp(I, ISD::SUB); 602 case Instruction::FSub: 603 // FNeg is currently represented in LLVM IR as a special case of FSub. 604 if (BinaryOperator::isFNeg(I)) 605 return SelectFNeg(I); 606 return SelectBinaryOp(I, ISD::FSUB); 607 case Instruction::Mul: 608 return SelectBinaryOp(I, ISD::MUL); 609 case Instruction::FMul: 610 return SelectBinaryOp(I, ISD::FMUL); 611 case Instruction::SDiv: 612 return SelectBinaryOp(I, ISD::SDIV); 613 case Instruction::UDiv: 614 return SelectBinaryOp(I, ISD::UDIV); 615 case Instruction::FDiv: 616 return SelectBinaryOp(I, ISD::FDIV); 617 case Instruction::SRem: 618 return SelectBinaryOp(I, ISD::SREM); 619 case Instruction::URem: 620 return SelectBinaryOp(I, ISD::UREM); 621 case Instruction::FRem: 622 return SelectBinaryOp(I, ISD::FREM); 623 case Instruction::Shl: 624 return SelectBinaryOp(I, ISD::SHL); 625 case Instruction::LShr: 626 return SelectBinaryOp(I, ISD::SRL); 627 case Instruction::AShr: 628 return SelectBinaryOp(I, ISD::SRA); 629 case Instruction::And: 630 return SelectBinaryOp(I, ISD::AND); 631 case Instruction::Or: 632 return SelectBinaryOp(I, ISD::OR); 633 case Instruction::Xor: 634 return SelectBinaryOp(I, ISD::XOR); 635 636 case Instruction::GetElementPtr: 637 return SelectGetElementPtr(I); 638 639 case Instruction::Br: { 640 BranchInst *BI = cast<BranchInst>(I); 641 642 if (BI->isUnconditional()) { 643 BasicBlock *LLVMSucc = BI->getSuccessor(0); 644 MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; 645 FastEmitBranch(MSucc); 646 return true; 647 } 648 649 // Conditional branches are not handed yet. 650 // Halt "fast" selection and bail. 651 return false; 652 } 653 654 case Instruction::Unreachable: 655 // Nothing to emit. 656 return true; 657 658 case Instruction::PHI: 659 // PHI nodes are already emitted. 660 return true; 661 662 case Instruction::Alloca: 663 // FunctionLowering has the static-sized case covered. 664 if (StaticAllocaMap.count(cast<AllocaInst>(I))) 665 return true; 666 667 // Dynamic-sized alloca is not handled yet. 668 return false; 669 670 case Instruction::Call: 671 return SelectCall(I); 672 673 case Instruction::BitCast: 674 return SelectBitCast(I); 675 676 case Instruction::FPToSI: 677 return SelectCast(I, ISD::FP_TO_SINT); 678 case Instruction::ZExt: 679 return SelectCast(I, ISD::ZERO_EXTEND); 680 case Instruction::SExt: 681 return SelectCast(I, ISD::SIGN_EXTEND); 682 case Instruction::Trunc: 683 return SelectCast(I, ISD::TRUNCATE); 684 case Instruction::SIToFP: 685 return SelectCast(I, ISD::SINT_TO_FP); 686 687 case Instruction::IntToPtr: // Deliberate fall-through. 688 case Instruction::PtrToInt: { 689 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 690 EVT DstVT = TLI.getValueType(I->getType()); 691 if (DstVT.bitsGT(SrcVT)) 692 return SelectCast(I, ISD::ZERO_EXTEND); 693 if (DstVT.bitsLT(SrcVT)) 694 return SelectCast(I, ISD::TRUNCATE); 695 unsigned Reg = getRegForValue(I->getOperand(0)); 696 if (Reg == 0) return false; 697 UpdateValueMap(I, Reg); 698 return true; 699 } 700 701 default: 702 // Unhandled instruction. Halt "fast" selection and bail. 703 return false; 704 } 705} 706 707FastISel::FastISel(MachineFunction &mf, 708 MachineModuleInfo *mmi, 709 DwarfWriter *dw, 710 DenseMap<const Value *, unsigned> &vm, 711 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 712 DenseMap<const AllocaInst *, int> &am 713#ifndef NDEBUG 714 , SmallSet<Instruction*, 8> &cil 715#endif 716 ) 717 : MBB(0), 718 ValueMap(vm), 719 MBBMap(bm), 720 StaticAllocaMap(am), 721#ifndef NDEBUG 722 CatchInfoLost(cil), 723#endif 724 MF(mf), 725 MMI(mmi), 726 DW(dw), 727 MRI(MF.getRegInfo()), 728 MFI(*MF.getFrameInfo()), 729 MCP(*MF.getConstantPool()), 730 TM(MF.getTarget()), 731 TD(*TM.getTargetData()), 732 TII(*TM.getInstrInfo()), 733 TLI(*TM.getTargetLowering()) { 734} 735 736FastISel::~FastISel() {} 737 738unsigned FastISel::FastEmit_(MVT, MVT, 739 unsigned) { 740 return 0; 741} 742 743unsigned FastISel::FastEmit_r(MVT, MVT, 744 unsigned, unsigned /*Op0*/) { 745 return 0; 746} 747 748unsigned FastISel::FastEmit_rr(MVT, MVT, 749 unsigned, unsigned /*Op0*/, 750 unsigned /*Op0*/) { 751 return 0; 752} 753 754unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 755 return 0; 756} 757 758unsigned FastISel::FastEmit_f(MVT, MVT, 759 unsigned, ConstantFP * /*FPImm*/) { 760 return 0; 761} 762 763unsigned FastISel::FastEmit_ri(MVT, MVT, 764 unsigned, unsigned /*Op0*/, 765 uint64_t /*Imm*/) { 766 return 0; 767} 768 769unsigned FastISel::FastEmit_rf(MVT, MVT, 770 unsigned, unsigned /*Op0*/, 771 ConstantFP * /*FPImm*/) { 772 return 0; 773} 774 775unsigned FastISel::FastEmit_rri(MVT, MVT, 776 unsigned, 777 unsigned /*Op0*/, unsigned /*Op1*/, 778 uint64_t /*Imm*/) { 779 return 0; 780} 781 782/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 783/// to emit an instruction with an immediate operand using FastEmit_ri. 784/// If that fails, it materializes the immediate into a register and try 785/// FastEmit_rr instead. 786unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 787 unsigned Op0, uint64_t Imm, 788 MVT ImmType) { 789 // First check if immediate type is legal. If not, we can't use the ri form. 790 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); 791 if (ResultReg != 0) 792 return ResultReg; 793 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 794 if (MaterialReg == 0) 795 return 0; 796 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 797} 798 799/// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries 800/// to emit an instruction with a floating-point immediate operand using 801/// FastEmit_rf. If that fails, it materializes the immediate into a register 802/// and try FastEmit_rr instead. 803unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode, 804 unsigned Op0, ConstantFP *FPImm, 805 MVT ImmType) { 806 // First check if immediate type is legal. If not, we can't use the rf form. 807 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); 808 if (ResultReg != 0) 809 return ResultReg; 810 811 // Materialize the constant in a register. 812 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); 813 if (MaterialReg == 0) { 814 // If the target doesn't have a way to directly enter a floating-point 815 // value into a register, use an alternate approach. 816 // TODO: The current approach only supports floating-point constants 817 // that can be constructed by conversion from integer values. This should 818 // be replaced by code that creates a load from a constant-pool entry, 819 // which will require some target-specific work. 820 const APFloat &Flt = FPImm->getValueAPF(); 821 EVT IntVT = TLI.getPointerTy(); 822 823 uint64_t x[2]; 824 uint32_t IntBitWidth = IntVT.getSizeInBits(); 825 bool isExact; 826 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 827 APFloat::rmTowardZero, &isExact); 828 if (!isExact) 829 return 0; 830 APInt IntVal(IntBitWidth, 2, x); 831 832 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), 833 ISD::Constant, IntVal.getZExtValue()); 834 if (IntegerReg == 0) 835 return 0; 836 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, 837 ISD::SINT_TO_FP, IntegerReg); 838 if (MaterialReg == 0) 839 return 0; 840 } 841 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); 842} 843 844unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 845 return MRI.createVirtualRegister(RC); 846} 847 848unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 849 const TargetRegisterClass* RC) { 850 unsigned ResultReg = createResultReg(RC); 851 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 852 853 BuildMI(MBB, DL, II, ResultReg); 854 return ResultReg; 855} 856 857unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 858 const TargetRegisterClass *RC, 859 unsigned Op0) { 860 unsigned ResultReg = createResultReg(RC); 861 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 862 863 if (II.getNumDefs() >= 1) 864 BuildMI(MBB, DL, II, ResultReg).addReg(Op0); 865 else { 866 BuildMI(MBB, DL, II).addReg(Op0); 867 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 868 II.ImplicitDefs[0], RC, RC); 869 if (!InsertedCopy) 870 ResultReg = 0; 871 } 872 873 return ResultReg; 874} 875 876unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 877 const TargetRegisterClass *RC, 878 unsigned Op0, unsigned Op1) { 879 unsigned ResultReg = createResultReg(RC); 880 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 881 882 if (II.getNumDefs() >= 1) 883 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1); 884 else { 885 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1); 886 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 887 II.ImplicitDefs[0], RC, RC); 888 if (!InsertedCopy) 889 ResultReg = 0; 890 } 891 return ResultReg; 892} 893 894unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 895 const TargetRegisterClass *RC, 896 unsigned Op0, uint64_t Imm) { 897 unsigned ResultReg = createResultReg(RC); 898 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 899 900 if (II.getNumDefs() >= 1) 901 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm); 902 else { 903 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm); 904 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 905 II.ImplicitDefs[0], RC, RC); 906 if (!InsertedCopy) 907 ResultReg = 0; 908 } 909 return ResultReg; 910} 911 912unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 913 const TargetRegisterClass *RC, 914 unsigned Op0, ConstantFP *FPImm) { 915 unsigned ResultReg = createResultReg(RC); 916 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 917 918 if (II.getNumDefs() >= 1) 919 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm); 920 else { 921 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm); 922 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 923 II.ImplicitDefs[0], RC, RC); 924 if (!InsertedCopy) 925 ResultReg = 0; 926 } 927 return ResultReg; 928} 929 930unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 931 const TargetRegisterClass *RC, 932 unsigned Op0, unsigned Op1, uint64_t Imm) { 933 unsigned ResultReg = createResultReg(RC); 934 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 935 936 if (II.getNumDefs() >= 1) 937 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); 938 else { 939 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm); 940 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 941 II.ImplicitDefs[0], RC, RC); 942 if (!InsertedCopy) 943 ResultReg = 0; 944 } 945 return ResultReg; 946} 947 948unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 949 const TargetRegisterClass *RC, 950 uint64_t Imm) { 951 unsigned ResultReg = createResultReg(RC); 952 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 953 954 if (II.getNumDefs() >= 1) 955 BuildMI(MBB, DL, II, ResultReg).addImm(Imm); 956 else { 957 BuildMI(MBB, DL, II).addImm(Imm); 958 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 959 II.ImplicitDefs[0], RC, RC); 960 if (!InsertedCopy) 961 ResultReg = 0; 962 } 963 return ResultReg; 964} 965 966unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 967 unsigned Op0, uint32_t Idx) { 968 const TargetRegisterClass* RC = MRI.getRegClass(Op0); 969 970 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 971 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); 972 973 if (II.getNumDefs() >= 1) 974 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx); 975 else { 976 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx); 977 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 978 II.ImplicitDefs[0], RC, RC); 979 if (!InsertedCopy) 980 ResultReg = 0; 981 } 982 return ResultReg; 983} 984 985/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 986/// with all but the least significant bit set to zero. 987unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) { 988 return FastEmit_ri(VT, VT, ISD::AND, Op, 1); 989} 990