FastISel.cpp revision 76927d7303046058c627691bd45d6bff608f49f4
1//===-- FastISel.cpp - Implementation of the FastISel class ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the implementation of the FastISel class. 11// 12// "Fast" instruction selection is designed to emit very poor code quickly. 13// Also, it is not designed to be able to do much lowering, so most illegal 14// types (e.g. i64 on 32-bit targets) and operations are not supported. It is 15// also not intended to be able to do much optimization, except in a few cases 16// where doing optimizations reduces overall compile time. For example, folding 17// constants into immediate fields is often done, because it's cheap and it 18// reduces the number of instructions later phases have to examine. 19// 20// "Fast" instruction selection is able to fail gracefully and transfer 21// control to the SelectionDAG selector for operations that it doesn't 22// support. In many cases, this allows us to avoid duplicating a lot of 23// the complicated lowering logic that SelectionDAG currently has. 24// 25// The intended use for "fast" instruction selection is "-O0" mode 26// compilation, where the quality of the generated code is irrelevant when 27// weighed against the speed at which the code can be generated. Also, 28// at -O0, the LLVM optimizers are not running, and this makes the 29// compile time of codegen a much higher portion of the overall compile 30// time. Despite its limitations, "fast" instruction selection is able to 31// handle enough code on its own to provide noticeable overall speedups 32// in -O0 compiles. 33// 34// Basic operations are supported in a target-independent way, by reading 35// the same instruction descriptions that the SelectionDAG selector reads, 36// and identifying simple arithmetic operations that can be directly selected 37// from simple operators. More complicated operations currently require 38// target-specific code. 39// 40//===----------------------------------------------------------------------===// 41 42#include "llvm/Function.h" 43#include "llvm/GlobalVariable.h" 44#include "llvm/Instructions.h" 45#include "llvm/IntrinsicInst.h" 46#include "llvm/Operator.h" 47#include "llvm/CodeGen/Analysis.h" 48#include "llvm/CodeGen/FastISel.h" 49#include "llvm/CodeGen/FunctionLoweringInfo.h" 50#include "llvm/CodeGen/MachineInstrBuilder.h" 51#include "llvm/CodeGen/MachineModuleInfo.h" 52#include "llvm/CodeGen/MachineRegisterInfo.h" 53#include "llvm/Analysis/DebugInfo.h" 54#include "llvm/Analysis/Loads.h" 55#include "llvm/Target/TargetData.h" 56#include "llvm/Target/TargetInstrInfo.h" 57#include "llvm/Target/TargetLowering.h" 58#include "llvm/Target/TargetMachine.h" 59#include "llvm/Support/ErrorHandling.h" 60#include "llvm/Support/Debug.h" 61using namespace llvm; 62 63/// startNewBlock - Set the current block to which generated machine 64/// instructions will be appended, and clear the local CSE map. 65/// 66void FastISel::startNewBlock() { 67 LocalValueMap.clear(); 68 69 // Start out as null, meaining no local-value instructions have 70 // been emitted. 71 LastLocalValue = 0; 72 73 // Advance the last local value past any EH_LABEL instructions. 74 MachineBasicBlock::iterator 75 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end(); 76 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) { 77 LastLocalValue = I; 78 ++I; 79 } 80} 81 82bool FastISel::hasTrivialKill(const Value *V) const { 83 // Don't consider constants or arguments to have trivial kills. 84 const Instruction *I = dyn_cast<Instruction>(V); 85 if (!I) 86 return false; 87 88 // No-op casts are trivially coalesced by fast-isel. 89 if (const CastInst *Cast = dyn_cast<CastInst>(I)) 90 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) && 91 !hasTrivialKill(Cast->getOperand(0))) 92 return false; 93 94 // Only instructions with a single use in the same basic block are considered 95 // to have trivial kills. 96 return I->hasOneUse() && 97 !(I->getOpcode() == Instruction::BitCast || 98 I->getOpcode() == Instruction::PtrToInt || 99 I->getOpcode() == Instruction::IntToPtr) && 100 cast<Instruction>(*I->use_begin())->getParent() == I->getParent(); 101} 102 103unsigned FastISel::getRegForValue(const Value *V) { 104 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); 105 // Don't handle non-simple values in FastISel. 106 if (!RealVT.isSimple()) 107 return 0; 108 109 // Ignore illegal types. We must do this before looking up the value 110 // in ValueMap because Arguments are given virtual registers regardless 111 // of whether FastISel can handle them. 112 MVT VT = RealVT.getSimpleVT(); 113 if (!TLI.isTypeLegal(VT)) { 114 // Handle integer promotions, though, because they're common and easy. 115 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 116 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); 117 else 118 return 0; 119 } 120 121 // Look up the value to see if we already have a register for it. We 122 // cache values defined by Instructions across blocks, and other values 123 // only locally. This is because Instructions already have the SSA 124 // def-dominates-use requirement enforced. 125 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 126 if (I != FuncInfo.ValueMap.end()) 127 return I->second; 128 129 unsigned Reg = LocalValueMap[V]; 130 if (Reg != 0) 131 return Reg; 132 133 // In bottom-up mode, just create the virtual register which will be used 134 // to hold the value. It will be materialized later. 135 if (isa<Instruction>(V) && 136 (!isa<AllocaInst>(V) || 137 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V)))) 138 return FuncInfo.InitializeRegForValue(V); 139 140 SavePoint SaveInsertPt = enterLocalValueArea(); 141 142 // Materialize the value in a register. Emit any instructions in the 143 // local value area. 144 Reg = materializeRegForValue(V, VT); 145 146 leaveLocalValueArea(SaveInsertPt); 147 148 return Reg; 149} 150 151/// materializeRegForValue - Helper for getRegForValue. This function is 152/// called when the value isn't already available in a register and must 153/// be materialized with new instructions. 154unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { 155 unsigned Reg = 0; 156 157 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 158 if (CI->getValue().getActiveBits() <= 64) 159 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 160 } else if (isa<AllocaInst>(V)) { 161 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 162 } else if (isa<ConstantPointerNull>(V)) { 163 // Translate this as an integer zero so that it can be 164 // local-CSE'd with actual integer zeros. 165 Reg = 166 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext()))); 167 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 168 if (CF->isNullValue()) { 169 Reg = TargetMaterializeFloatZero(CF); 170 } else { 171 // Try to emit the constant directly. 172 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); 173 } 174 175 if (!Reg) { 176 // Try to emit the constant by using an integer constant with a cast. 177 const APFloat &Flt = CF->getValueAPF(); 178 EVT IntVT = TLI.getPointerTy(); 179 180 uint64_t x[2]; 181 uint32_t IntBitWidth = IntVT.getSizeInBits(); 182 bool isExact; 183 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, 184 APFloat::rmTowardZero, &isExact); 185 if (isExact) { 186 APInt IntVal(IntBitWidth, 2, x); 187 188 unsigned IntegerReg = 189 getRegForValue(ConstantInt::get(V->getContext(), IntVal)); 190 if (IntegerReg != 0) 191 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, 192 IntegerReg, /*Kill=*/false); 193 } 194 } 195 } else if (const Operator *Op = dyn_cast<Operator>(V)) { 196 if (!SelectOperator(Op, Op->getOpcode())) 197 if (!isa<Instruction>(Op) || 198 !TargetSelectInstruction(cast<Instruction>(Op))) 199 return 0; 200 Reg = lookUpRegForValue(Op); 201 } else if (isa<UndefValue>(V)) { 202 Reg = createResultReg(TLI.getRegClassFor(VT)); 203 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 204 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); 205 } 206 207 // If target-independent code couldn't handle the value, give target-specific 208 // code a try. 209 if (!Reg && isa<Constant>(V)) 210 Reg = TargetMaterializeConstant(cast<Constant>(V)); 211 212 // Don't cache constant materializations in the general ValueMap. 213 // To do so would require tracking what uses they dominate. 214 if (Reg != 0) { 215 LocalValueMap[V] = Reg; 216 LastLocalValue = MRI.getVRegDef(Reg); 217 } 218 return Reg; 219} 220 221unsigned FastISel::lookUpRegForValue(const Value *V) { 222 // Look up the value to see if we already have a register for it. We 223 // cache values defined by Instructions across blocks, and other values 224 // only locally. This is because Instructions already have the SSA 225 // def-dominates-use requirement enforced. 226 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V); 227 if (I != FuncInfo.ValueMap.end()) 228 return I->second; 229 return LocalValueMap[V]; 230} 231 232/// UpdateValueMap - Update the value map to include the new mapping for this 233/// instruction, or insert an extra copy to get the result in a previous 234/// determined register. 235/// NOTE: This is only necessary because we might select a block that uses 236/// a value before we select the block that defines the value. It might be 237/// possible to fix this by selecting blocks in reverse postorder. 238void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { 239 if (!isa<Instruction>(I)) { 240 LocalValueMap[I] = Reg; 241 return; 242 } 243 244 unsigned &AssignedReg = FuncInfo.ValueMap[I]; 245 if (AssignedReg == 0) 246 // Use the new register. 247 AssignedReg = Reg; 248 else if (Reg != AssignedReg) { 249 // Arrange for uses of AssignedReg to be replaced by uses of Reg. 250 for (unsigned i = 0; i < NumRegs; i++) 251 FuncInfo.RegFixups[AssignedReg+i] = Reg+i; 252 253 AssignedReg = Reg; 254 } 255} 256 257std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) { 258 unsigned IdxN = getRegForValue(Idx); 259 if (IdxN == 0) 260 // Unhandled operand. Halt "fast" selection and bail. 261 return std::pair<unsigned, bool>(0, false); 262 263 bool IdxNIsKill = hasTrivialKill(Idx); 264 265 // If the index is smaller or larger than intptr_t, truncate or extend it. 266 MVT PtrVT = TLI.getPointerTy(); 267 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); 268 if (IdxVT.bitsLT(PtrVT)) { 269 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, 270 IdxN, IdxNIsKill); 271 IdxNIsKill = true; 272 } 273 else if (IdxVT.bitsGT(PtrVT)) { 274 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, 275 IdxN, IdxNIsKill); 276 IdxNIsKill = true; 277 } 278 return std::pair<unsigned, bool>(IdxN, IdxNIsKill); 279} 280 281void FastISel::recomputeInsertPt() { 282 if (getLastLocalValue()) { 283 FuncInfo.InsertPt = getLastLocalValue(); 284 FuncInfo.MBB = FuncInfo.InsertPt->getParent(); 285 ++FuncInfo.InsertPt; 286 } else 287 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI(); 288 289 // Now skip past any EH_LABELs, which must remain at the beginning. 290 while (FuncInfo.InsertPt != FuncInfo.MBB->end() && 291 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) 292 ++FuncInfo.InsertPt; 293} 294 295FastISel::SavePoint FastISel::enterLocalValueArea() { 296 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; 297 DebugLoc OldDL = DL; 298 recomputeInsertPt(); 299 DL = DebugLoc(); 300 SavePoint SP = { OldInsertPt, OldDL }; 301 return SP; 302} 303 304void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { 305 if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) 306 LastLocalValue = llvm::prior(FuncInfo.InsertPt); 307 308 // Restore the previous insert position. 309 FuncInfo.InsertPt = OldInsertPt.InsertPt; 310 DL = OldInsertPt.DL; 311} 312 313/// SelectBinaryOp - Select and emit code for a binary operator instruction, 314/// which has an opcode which directly corresponds to the given ISD opcode. 315/// 316bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) { 317 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); 318 if (VT == MVT::Other || !VT.isSimple()) 319 // Unhandled type. Halt "fast" selection and bail. 320 return false; 321 322 // We only handle legal types. For example, on x86-32 the instruction 323 // selector contains all of the 64-bit instructions from x86-64, 324 // under the assumption that i64 won't be used if the target doesn't 325 // support it. 326 if (!TLI.isTypeLegal(VT)) { 327 // MVT::i1 is special. Allow AND, OR, or XOR because they 328 // don't require additional zeroing, which makes them easy. 329 if (VT == MVT::i1 && 330 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || 331 ISDOpcode == ISD::XOR)) 332 VT = TLI.getTypeToTransformTo(I->getContext(), VT); 333 else 334 return false; 335 } 336 337 // Check if the first operand is a constant, and handle it as "ri". At -O0, 338 // we don't have anything that canonicalizes operand order. 339 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0))) 340 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) { 341 unsigned Op1 = getRegForValue(I->getOperand(1)); 342 if (Op1 == 0) return false; 343 344 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 345 346 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, 347 Op1IsKill, CI->getZExtValue(), 348 VT.getSimpleVT()); 349 if (ResultReg == 0) return false; 350 351 // We successfully emitted code for the given LLVM Instruction. 352 UpdateValueMap(I, ResultReg); 353 return true; 354 } 355 356 357 unsigned Op0 = getRegForValue(I->getOperand(0)); 358 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail. 359 return false; 360 361 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 362 363 // Check if the second operand is a constant and handle it appropriately. 364 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 365 uint64_t Imm = CI->getZExtValue(); 366 367 // Transform "sdiv exact X, 8" -> "sra X, 3". 368 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) && 369 cast<BinaryOperator>(I)->isExact() && 370 isPowerOf2_64(Imm)) { 371 Imm = Log2_64(Imm); 372 ISDOpcode = ISD::SRA; 373 } 374 375 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, 376 Op0IsKill, Imm, VT.getSimpleVT()); 377 if (ResultReg == 0) return false; 378 379 // We successfully emitted code for the given LLVM Instruction. 380 UpdateValueMap(I, ResultReg); 381 return true; 382 } 383 384 // Check if the second operand is a constant float. 385 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { 386 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), 387 ISDOpcode, Op0, Op0IsKill, CF); 388 if (ResultReg != 0) { 389 // We successfully emitted code for the given LLVM Instruction. 390 UpdateValueMap(I, ResultReg); 391 return true; 392 } 393 } 394 395 unsigned Op1 = getRegForValue(I->getOperand(1)); 396 if (Op1 == 0) 397 // Unhandled operand. Halt "fast" selection and bail. 398 return false; 399 400 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); 401 402 // Now we have both operands in registers. Emit the instruction. 403 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), 404 ISDOpcode, 405 Op0, Op0IsKill, 406 Op1, Op1IsKill); 407 if (ResultReg == 0) 408 // Target-specific code wasn't able to find a machine opcode for 409 // the given ISD opcode and type. Halt "fast" selection and bail. 410 return false; 411 412 // We successfully emitted code for the given LLVM Instruction. 413 UpdateValueMap(I, ResultReg); 414 return true; 415} 416 417bool FastISel::SelectGetElementPtr(const User *I) { 418 unsigned N = getRegForValue(I->getOperand(0)); 419 if (N == 0) 420 // Unhandled operand. Halt "fast" selection and bail. 421 return false; 422 423 bool NIsKill = hasTrivialKill(I->getOperand(0)); 424 425 const Type *Ty = I->getOperand(0)->getType(); 426 MVT VT = TLI.getPointerTy(); 427 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1, 428 E = I->op_end(); OI != E; ++OI) { 429 const Value *Idx = *OI; 430 if (const StructType *StTy = dyn_cast<StructType>(Ty)) { 431 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 432 if (Field) { 433 // N = N + Offset 434 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); 435 // FIXME: This can be optimized by combining the add with a 436 // subsequent one. 437 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 438 if (N == 0) 439 // Unhandled operand. Halt "fast" selection and bail. 440 return false; 441 NIsKill = true; 442 } 443 Ty = StTy->getElementType(Field); 444 } else { 445 Ty = cast<SequentialType>(Ty)->getElementType(); 446 447 // If this is a constant subscript, handle it quickly. 448 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 449 if (CI->isZero()) continue; 450 uint64_t Offs = 451 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 452 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); 453 if (N == 0) 454 // Unhandled operand. Halt "fast" selection and bail. 455 return false; 456 NIsKill = true; 457 continue; 458 } 459 460 // N = N + Idx * ElementSize; 461 uint64_t ElementSize = TD.getTypeAllocSize(Ty); 462 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx); 463 unsigned IdxN = Pair.first; 464 bool IdxNIsKill = Pair.second; 465 if (IdxN == 0) 466 // Unhandled operand. Halt "fast" selection and bail. 467 return false; 468 469 if (ElementSize != 1) { 470 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT); 471 if (IdxN == 0) 472 // Unhandled operand. Halt "fast" selection and bail. 473 return false; 474 IdxNIsKill = true; 475 } 476 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill); 477 if (N == 0) 478 // Unhandled operand. Halt "fast" selection and bail. 479 return false; 480 } 481 } 482 483 // We successfully emitted code for the given LLVM Instruction. 484 UpdateValueMap(I, N); 485 return true; 486} 487 488bool FastISel::SelectCall(const User *I) { 489 const CallInst *Call = cast<CallInst>(I); 490 491 // Handle simple inline asms. 492 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getArgOperand(0))) { 493 // Don't attempt to handle constraints. 494 if (!IA->getConstraintString().empty()) 495 return false; 496 497 unsigned ExtraInfo = 0; 498 if (IA->hasSideEffects()) 499 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 500 if (IA->isAlignStack()) 501 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 502 503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 504 TII.get(TargetOpcode::INLINEASM)) 505 .addExternalSymbol(IA->getAsmString().c_str()) 506 .addImm(ExtraInfo); 507 return true; 508 } 509 510 const Function *F = Call->getCalledFunction(); 511 if (!F) return false; 512 513 // Handle selected intrinsic function calls. 514 switch (F->getIntrinsicID()) { 515 default: break; 516 case Intrinsic::dbg_declare: { 517 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call); 518 if (!DIVariable(DI->getVariable()).Verify() || 519 !FuncInfo.MF->getMMI().hasDebugInfo()) 520 return true; 521 522 const Value *Address = DI->getAddress(); 523 if (!Address || isa<UndefValue>(Address) || isa<AllocaInst>(Address)) 524 return true; 525 526 unsigned Reg = 0; 527 unsigned Offset = 0; 528 if (const Argument *Arg = dyn_cast<Argument>(Address)) { 529 if (Arg->hasByValAttr()) { 530 // Byval arguments' frame index is recorded during argument lowering. 531 // Use this info directly. 532 Offset = FuncInfo.getByValArgumentFrameIndex(Arg); 533 if (Offset) 534 Reg = TRI.getFrameRegister(*FuncInfo.MF); 535 } 536 } 537 if (!Reg) 538 Reg = getRegForValue(Address); 539 540 if (Reg) 541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 542 TII.get(TargetOpcode::DBG_VALUE)) 543 .addReg(Reg, RegState::Debug).addImm(Offset) 544 .addMetadata(DI->getVariable()); 545 return true; 546 } 547 case Intrinsic::dbg_value: { 548 // This form of DBG_VALUE is target-independent. 549 const DbgValueInst *DI = cast<DbgValueInst>(Call); 550 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 551 const Value *V = DI->getValue(); 552 if (!V) { 553 // Currently the optimizer can produce this; insert an undef to 554 // help debugging. Probably the optimizer should not do this. 555 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 556 .addReg(0U).addImm(DI->getOffset()) 557 .addMetadata(DI->getVariable()); 558 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 559 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 560 .addImm(CI->getZExtValue()).addImm(DI->getOffset()) 561 .addMetadata(DI->getVariable()); 562 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 563 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 564 .addFPImm(CF).addImm(DI->getOffset()) 565 .addMetadata(DI->getVariable()); 566 } else if (unsigned Reg = lookUpRegForValue(V)) { 567 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 568 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 569 .addMetadata(DI->getVariable()); 570 } else { 571 // We can't yet handle anything else here because it would require 572 // generating code, thus altering codegen because of debug info. 573 DEBUG(dbgs() << "Dropping debug info for " << DI); 574 } 575 return true; 576 } 577 case Intrinsic::eh_exception: { 578 EVT VT = TLI.getValueType(Call->getType()); 579 if (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)!=TargetLowering::Expand) 580 break; 581 582 assert(FuncInfo.MBB->isLandingPad() && 583 "Call to eh.exception not in landing pad!"); 584 unsigned Reg = TLI.getExceptionAddressRegister(); 585 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); 586 unsigned ResultReg = createResultReg(RC); 587 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 588 ResultReg).addReg(Reg); 589 UpdateValueMap(Call, ResultReg); 590 return true; 591 } 592 case Intrinsic::eh_selector: { 593 EVT VT = TLI.getValueType(Call->getType()); 594 if (TLI.getOperationAction(ISD::EHSELECTION, VT) != TargetLowering::Expand) 595 break; 596 if (FuncInfo.MBB->isLandingPad()) 597 AddCatchInfo(*Call, &FuncInfo.MF->getMMI(), FuncInfo.MBB); 598 else { 599#ifndef NDEBUG 600 FuncInfo.CatchInfoLost.insert(Call); 601#endif 602 // FIXME: Mark exception selector register as live in. Hack for PR1508. 603 unsigned Reg = TLI.getExceptionSelectorRegister(); 604 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 605 } 606 607 unsigned Reg = TLI.getExceptionSelectorRegister(); 608 EVT SrcVT = TLI.getPointerTy(); 609 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); 610 unsigned ResultReg = createResultReg(RC); 611 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 612 ResultReg).addReg(Reg); 613 614 bool ResultRegIsKill = hasTrivialKill(Call); 615 616 // Cast the register to the type of the selector. 617 if (SrcVT.bitsGT(MVT::i32)) 618 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE, 619 ResultReg, ResultRegIsKill); 620 else if (SrcVT.bitsLT(MVT::i32)) 621 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, 622 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill); 623 if (ResultReg == 0) 624 // Unhandled operand. Halt "fast" selection and bail. 625 return false; 626 627 UpdateValueMap(Call, ResultReg); 628 629 return true; 630 } 631 case Intrinsic::objectsize: { 632 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1)); 633 unsigned long long Res = CI->isZero() ? -1ULL : 0; 634 Constant *ResCI = ConstantInt::get(Call->getType(), Res); 635 unsigned ResultReg = getRegForValue(ResCI); 636 if (ResultReg == 0) 637 return false; 638 UpdateValueMap(Call, ResultReg); 639 return true; 640 } 641 } 642 643 // An arbitrary call. Bail. 644 return false; 645} 646 647bool FastISel::SelectCast(const User *I, unsigned Opcode) { 648 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 649 EVT DstVT = TLI.getValueType(I->getType()); 650 651 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 652 DstVT == MVT::Other || !DstVT.isSimple()) 653 // Unhandled type. Halt "fast" selection and bail. 654 return false; 655 656 // Check if the destination type is legal. 657 if (!TLI.isTypeLegal(DstVT)) 658 return false; 659 660 // Check if the source operand is legal. 661 if (!TLI.isTypeLegal(SrcVT)) 662 return false; 663 664 unsigned InputReg = getRegForValue(I->getOperand(0)); 665 if (!InputReg) 666 // Unhandled operand. Halt "fast" selection and bail. 667 return false; 668 669 bool InputRegIsKill = hasTrivialKill(I->getOperand(0)); 670 671 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), 672 DstVT.getSimpleVT(), 673 Opcode, 674 InputReg, InputRegIsKill); 675 if (!ResultReg) 676 return false; 677 678 UpdateValueMap(I, ResultReg); 679 return true; 680} 681 682bool FastISel::SelectBitCast(const User *I) { 683 // If the bitcast doesn't change the type, just use the operand value. 684 if (I->getType() == I->getOperand(0)->getType()) { 685 unsigned Reg = getRegForValue(I->getOperand(0)); 686 if (Reg == 0) 687 return false; 688 UpdateValueMap(I, Reg); 689 return true; 690 } 691 692 // Bitcasts of other values become reg-reg copies or BITCAST operators. 693 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 694 EVT DstVT = TLI.getValueType(I->getType()); 695 696 if (SrcVT == MVT::Other || !SrcVT.isSimple() || 697 DstVT == MVT::Other || !DstVT.isSimple() || 698 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) 699 // Unhandled type. Halt "fast" selection and bail. 700 return false; 701 702 unsigned Op0 = getRegForValue(I->getOperand(0)); 703 if (Op0 == 0) 704 // Unhandled operand. Halt "fast" selection and bail. 705 return false; 706 707 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); 708 709 // First, try to perform the bitcast by inserting a reg-reg copy. 710 unsigned ResultReg = 0; 711 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { 712 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); 713 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); 714 // Don't attempt a cross-class copy. It will likely fail. 715 if (SrcClass == DstClass) { 716 ResultReg = createResultReg(DstClass); 717 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 718 ResultReg).addReg(Op0); 719 } 720 } 721 722 // If the reg-reg copy failed, select a BITCAST opcode. 723 if (!ResultReg) 724 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), 725 ISD::BITCAST, Op0, Op0IsKill); 726 727 if (!ResultReg) 728 return false; 729 730 UpdateValueMap(I, ResultReg); 731 return true; 732} 733 734bool 735FastISel::SelectInstruction(const Instruction *I) { 736 // Just before the terminator instruction, insert instructions to 737 // feed PHI nodes in successor blocks. 738 if (isa<TerminatorInst>(I)) 739 if (!HandlePHINodesInSuccessorBlocks(I->getParent())) 740 return false; 741 742 DL = I->getDebugLoc(); 743 744 // First, try doing target-independent selection. 745 if (SelectOperator(I, I->getOpcode())) { 746 DL = DebugLoc(); 747 return true; 748 } 749 750 // Next, try calling the target to attempt to handle the instruction. 751 if (TargetSelectInstruction(I)) { 752 DL = DebugLoc(); 753 return true; 754 } 755 756 DL = DebugLoc(); 757 return false; 758} 759 760/// FastEmitBranch - Emit an unconditional branch to the given block, 761/// unless it is the immediate (fall-through) successor, and update 762/// the CFG. 763void 764FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { 765 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) { 766 // The unconditional fall-through case, which needs no instructions. 767 } else { 768 // The unconditional branch case. 769 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL, 770 SmallVector<MachineOperand, 0>(), DL); 771 } 772 FuncInfo.MBB->addSuccessor(MSucc); 773} 774 775/// SelectFNeg - Emit an FNeg operation. 776/// 777bool 778FastISel::SelectFNeg(const User *I) { 779 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); 780 if (OpReg == 0) return false; 781 782 bool OpRegIsKill = hasTrivialKill(I); 783 784 // If the target has ISD::FNEG, use it. 785 EVT VT = TLI.getValueType(I->getType()); 786 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), 787 ISD::FNEG, OpReg, OpRegIsKill); 788 if (ResultReg != 0) { 789 UpdateValueMap(I, ResultReg); 790 return true; 791 } 792 793 // Bitcast the value to integer, twiddle the sign bit with xor, 794 // and then bitcast it back to floating-point. 795 if (VT.getSizeInBits() > 64) return false; 796 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); 797 if (!TLI.isTypeLegal(IntVT)) 798 return false; 799 800 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), 801 ISD::BITCAST, OpReg, OpRegIsKill); 802 if (IntReg == 0) 803 return false; 804 805 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, 806 IntReg, /*Kill=*/true, 807 UINT64_C(1) << (VT.getSizeInBits()-1), 808 IntVT.getSimpleVT()); 809 if (IntResultReg == 0) 810 return false; 811 812 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), 813 ISD::BITCAST, IntResultReg, /*Kill=*/true); 814 if (ResultReg == 0) 815 return false; 816 817 UpdateValueMap(I, ResultReg); 818 return true; 819} 820 821bool 822FastISel::SelectExtractValue(const User *U) { 823 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U); 824 if (!EVI) 825 return false; 826 827 // Make sure we only try to handle extracts with a legal result. But also 828 // allow i1 because it's easy. 829 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true); 830 if (!RealVT.isSimple()) 831 return false; 832 MVT VT = RealVT.getSimpleVT(); 833 if (!TLI.isTypeLegal(VT) && VT != MVT::i1) 834 return false; 835 836 const Value *Op0 = EVI->getOperand(0); 837 const Type *AggTy = Op0->getType(); 838 839 // Get the base result register. 840 unsigned ResultReg; 841 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0); 842 if (I != FuncInfo.ValueMap.end()) 843 ResultReg = I->second; 844 else 845 ResultReg = FuncInfo.InitializeRegForValue(Op0); 846 847 // Get the actual result register, which is an offset from the base register. 848 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->idx_begin(), EVI->idx_end()); 849 850 SmallVector<EVT, 4> AggValueVTs; 851 ComputeValueVTs(TLI, AggTy, AggValueVTs); 852 853 for (unsigned i = 0; i < VTIndex; i++) 854 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]); 855 856 UpdateValueMap(EVI, ResultReg); 857 return true; 858} 859 860bool 861FastISel::SelectOperator(const User *I, unsigned Opcode) { 862 switch (Opcode) { 863 case Instruction::Add: 864 return SelectBinaryOp(I, ISD::ADD); 865 case Instruction::FAdd: 866 return SelectBinaryOp(I, ISD::FADD); 867 case Instruction::Sub: 868 return SelectBinaryOp(I, ISD::SUB); 869 case Instruction::FSub: 870 // FNeg is currently represented in LLVM IR as a special case of FSub. 871 if (BinaryOperator::isFNeg(I)) 872 return SelectFNeg(I); 873 return SelectBinaryOp(I, ISD::FSUB); 874 case Instruction::Mul: 875 return SelectBinaryOp(I, ISD::MUL); 876 case Instruction::FMul: 877 return SelectBinaryOp(I, ISD::FMUL); 878 case Instruction::SDiv: 879 return SelectBinaryOp(I, ISD::SDIV); 880 case Instruction::UDiv: 881 return SelectBinaryOp(I, ISD::UDIV); 882 case Instruction::FDiv: 883 return SelectBinaryOp(I, ISD::FDIV); 884 case Instruction::SRem: 885 return SelectBinaryOp(I, ISD::SREM); 886 case Instruction::URem: 887 return SelectBinaryOp(I, ISD::UREM); 888 case Instruction::FRem: 889 return SelectBinaryOp(I, ISD::FREM); 890 case Instruction::Shl: 891 return SelectBinaryOp(I, ISD::SHL); 892 case Instruction::LShr: 893 return SelectBinaryOp(I, ISD::SRL); 894 case Instruction::AShr: 895 return SelectBinaryOp(I, ISD::SRA); 896 case Instruction::And: 897 return SelectBinaryOp(I, ISD::AND); 898 case Instruction::Or: 899 return SelectBinaryOp(I, ISD::OR); 900 case Instruction::Xor: 901 return SelectBinaryOp(I, ISD::XOR); 902 903 case Instruction::GetElementPtr: 904 return SelectGetElementPtr(I); 905 906 case Instruction::Br: { 907 const BranchInst *BI = cast<BranchInst>(I); 908 909 if (BI->isUnconditional()) { 910 const BasicBlock *LLVMSucc = BI->getSuccessor(0); 911 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc]; 912 FastEmitBranch(MSucc, BI->getDebugLoc()); 913 return true; 914 } 915 916 // Conditional branches are not handed yet. 917 // Halt "fast" selection and bail. 918 return false; 919 } 920 921 case Instruction::Unreachable: 922 // Nothing to emit. 923 return true; 924 925 case Instruction::Alloca: 926 // FunctionLowering has the static-sized case covered. 927 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I))) 928 return true; 929 930 // Dynamic-sized alloca is not handled yet. 931 return false; 932 933 case Instruction::Call: 934 return SelectCall(I); 935 936 case Instruction::BitCast: 937 return SelectBitCast(I); 938 939 case Instruction::FPToSI: 940 return SelectCast(I, ISD::FP_TO_SINT); 941 case Instruction::ZExt: 942 return SelectCast(I, ISD::ZERO_EXTEND); 943 case Instruction::SExt: 944 return SelectCast(I, ISD::SIGN_EXTEND); 945 case Instruction::Trunc: 946 return SelectCast(I, ISD::TRUNCATE); 947 case Instruction::SIToFP: 948 return SelectCast(I, ISD::SINT_TO_FP); 949 950 case Instruction::IntToPtr: // Deliberate fall-through. 951 case Instruction::PtrToInt: { 952 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 953 EVT DstVT = TLI.getValueType(I->getType()); 954 if (DstVT.bitsGT(SrcVT)) 955 return SelectCast(I, ISD::ZERO_EXTEND); 956 if (DstVT.bitsLT(SrcVT)) 957 return SelectCast(I, ISD::TRUNCATE); 958 unsigned Reg = getRegForValue(I->getOperand(0)); 959 if (Reg == 0) return false; 960 UpdateValueMap(I, Reg); 961 return true; 962 } 963 964 case Instruction::ExtractValue: 965 return SelectExtractValue(I); 966 967 case Instruction::PHI: 968 llvm_unreachable("FastISel shouldn't visit PHI nodes!"); 969 970 default: 971 // Unhandled instruction. Halt "fast" selection and bail. 972 return false; 973 } 974} 975 976FastISel::FastISel(FunctionLoweringInfo &funcInfo) 977 : FuncInfo(funcInfo), 978 MRI(FuncInfo.MF->getRegInfo()), 979 MFI(*FuncInfo.MF->getFrameInfo()), 980 MCP(*FuncInfo.MF->getConstantPool()), 981 TM(FuncInfo.MF->getTarget()), 982 TD(*TM.getTargetData()), 983 TII(*TM.getInstrInfo()), 984 TLI(*TM.getTargetLowering()), 985 TRI(*TM.getRegisterInfo()) { 986} 987 988FastISel::~FastISel() {} 989 990unsigned FastISel::FastEmit_(MVT, MVT, 991 unsigned) { 992 return 0; 993} 994 995unsigned FastISel::FastEmit_r(MVT, MVT, 996 unsigned, 997 unsigned /*Op0*/, bool /*Op0IsKill*/) { 998 return 0; 999} 1000 1001unsigned FastISel::FastEmit_rr(MVT, MVT, 1002 unsigned, 1003 unsigned /*Op0*/, bool /*Op0IsKill*/, 1004 unsigned /*Op1*/, bool /*Op1IsKill*/) { 1005 return 0; 1006} 1007 1008unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) { 1009 return 0; 1010} 1011 1012unsigned FastISel::FastEmit_f(MVT, MVT, 1013 unsigned, const ConstantFP * /*FPImm*/) { 1014 return 0; 1015} 1016 1017unsigned FastISel::FastEmit_ri(MVT, MVT, 1018 unsigned, 1019 unsigned /*Op0*/, bool /*Op0IsKill*/, 1020 uint64_t /*Imm*/) { 1021 return 0; 1022} 1023 1024unsigned FastISel::FastEmit_rf(MVT, MVT, 1025 unsigned, 1026 unsigned /*Op0*/, bool /*Op0IsKill*/, 1027 const ConstantFP * /*FPImm*/) { 1028 return 0; 1029} 1030 1031unsigned FastISel::FastEmit_rri(MVT, MVT, 1032 unsigned, 1033 unsigned /*Op0*/, bool /*Op0IsKill*/, 1034 unsigned /*Op1*/, bool /*Op1IsKill*/, 1035 uint64_t /*Imm*/) { 1036 return 0; 1037} 1038 1039/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries 1040/// to emit an instruction with an immediate operand using FastEmit_ri. 1041/// If that fails, it materializes the immediate into a register and try 1042/// FastEmit_rr instead. 1043unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode, 1044 unsigned Op0, bool Op0IsKill, 1045 uint64_t Imm, MVT ImmType) { 1046 // If this is a multiply by a power of two, emit this as a shift left. 1047 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) { 1048 Opcode = ISD::SHL; 1049 Imm = Log2_64(Imm); 1050 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { 1051 // div x, 8 -> srl x, 3 1052 Opcode = ISD::SRL; 1053 Imm = Log2_64(Imm); 1054 } 1055 1056 // Horrible hack (to be removed), check to make sure shift amounts are 1057 // in-range. 1058 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) && 1059 Imm >= VT.getSizeInBits()) 1060 return 0; 1061 1062 // First check if immediate type is legal. If not, we can't use the ri form. 1063 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm); 1064 if (ResultReg != 0) 1065 return ResultReg; 1066 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); 1067 if (MaterialReg == 0) { 1068 // This is a bit ugly/slow, but failing here means falling out of 1069 // fast-isel, which would be very slow. 1070 const IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(), 1071 VT.getSizeInBits()); 1072 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm)); 1073 } 1074 return FastEmit_rr(VT, VT, Opcode, 1075 Op0, Op0IsKill, 1076 MaterialReg, /*Kill=*/true); 1077} 1078 1079unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { 1080 return MRI.createVirtualRegister(RC); 1081} 1082 1083unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, 1084 const TargetRegisterClass* RC) { 1085 unsigned ResultReg = createResultReg(RC); 1086 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1087 1088 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); 1089 return ResultReg; 1090} 1091 1092unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, 1093 const TargetRegisterClass *RC, 1094 unsigned Op0, bool Op0IsKill) { 1095 unsigned ResultReg = createResultReg(RC); 1096 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1097 1098 if (II.getNumDefs() >= 1) 1099 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1100 .addReg(Op0, Op0IsKill * RegState::Kill); 1101 else { 1102 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1103 .addReg(Op0, Op0IsKill * RegState::Kill); 1104 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1105 ResultReg).addReg(II.ImplicitDefs[0]); 1106 } 1107 1108 return ResultReg; 1109} 1110 1111unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 1112 const TargetRegisterClass *RC, 1113 unsigned Op0, bool Op0IsKill, 1114 unsigned Op1, bool Op1IsKill) { 1115 unsigned ResultReg = createResultReg(RC); 1116 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1117 1118 if (II.getNumDefs() >= 1) 1119 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1120 .addReg(Op0, Op0IsKill * RegState::Kill) 1121 .addReg(Op1, Op1IsKill * RegState::Kill); 1122 else { 1123 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1124 .addReg(Op0, Op0IsKill * RegState::Kill) 1125 .addReg(Op1, Op1IsKill * RegState::Kill); 1126 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1127 ResultReg).addReg(II.ImplicitDefs[0]); 1128 } 1129 return ResultReg; 1130} 1131 1132unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, 1133 const TargetRegisterClass *RC, 1134 unsigned Op0, bool Op0IsKill, 1135 unsigned Op1, bool Op1IsKill, 1136 unsigned Op2, bool Op2IsKill) { 1137 unsigned ResultReg = createResultReg(RC); 1138 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1139 1140 if (II.getNumDefs() >= 1) 1141 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1142 .addReg(Op0, Op0IsKill * RegState::Kill) 1143 .addReg(Op1, Op1IsKill * RegState::Kill) 1144 .addReg(Op2, Op2IsKill * RegState::Kill); 1145 else { 1146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1147 .addReg(Op0, Op0IsKill * RegState::Kill) 1148 .addReg(Op1, Op1IsKill * RegState::Kill) 1149 .addReg(Op2, Op2IsKill * RegState::Kill); 1150 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1151 ResultReg).addReg(II.ImplicitDefs[0]); 1152 } 1153 return ResultReg; 1154} 1155 1156unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 1157 const TargetRegisterClass *RC, 1158 unsigned Op0, bool Op0IsKill, 1159 uint64_t Imm) { 1160 unsigned ResultReg = createResultReg(RC); 1161 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1162 1163 if (II.getNumDefs() >= 1) 1164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1165 .addReg(Op0, Op0IsKill * RegState::Kill) 1166 .addImm(Imm); 1167 else { 1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1169 .addReg(Op0, Op0IsKill * RegState::Kill) 1170 .addImm(Imm); 1171 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1172 ResultReg).addReg(II.ImplicitDefs[0]); 1173 } 1174 return ResultReg; 1175} 1176 1177unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode, 1178 const TargetRegisterClass *RC, 1179 unsigned Op0, bool Op0IsKill, 1180 uint64_t Imm1, uint64_t Imm2) { 1181 unsigned ResultReg = createResultReg(RC); 1182 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1183 1184 if (II.getNumDefs() >= 1) 1185 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1186 .addReg(Op0, Op0IsKill * RegState::Kill) 1187 .addImm(Imm1) 1188 .addImm(Imm2); 1189 else { 1190 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1191 .addReg(Op0, Op0IsKill * RegState::Kill) 1192 .addImm(Imm1) 1193 .addImm(Imm2); 1194 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1195 ResultReg).addReg(II.ImplicitDefs[0]); 1196 } 1197 return ResultReg; 1198} 1199 1200unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 1201 const TargetRegisterClass *RC, 1202 unsigned Op0, bool Op0IsKill, 1203 const ConstantFP *FPImm) { 1204 unsigned ResultReg = createResultReg(RC); 1205 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1206 1207 if (II.getNumDefs() >= 1) 1208 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1209 .addReg(Op0, Op0IsKill * RegState::Kill) 1210 .addFPImm(FPImm); 1211 else { 1212 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1213 .addReg(Op0, Op0IsKill * RegState::Kill) 1214 .addFPImm(FPImm); 1215 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1216 ResultReg).addReg(II.ImplicitDefs[0]); 1217 } 1218 return ResultReg; 1219} 1220 1221unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 1222 const TargetRegisterClass *RC, 1223 unsigned Op0, bool Op0IsKill, 1224 unsigned Op1, bool Op1IsKill, 1225 uint64_t Imm) { 1226 unsigned ResultReg = createResultReg(RC); 1227 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1228 1229 if (II.getNumDefs() >= 1) 1230 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1231 .addReg(Op0, Op0IsKill * RegState::Kill) 1232 .addReg(Op1, Op1IsKill * RegState::Kill) 1233 .addImm(Imm); 1234 else { 1235 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 1236 .addReg(Op0, Op0IsKill * RegState::Kill) 1237 .addReg(Op1, Op1IsKill * RegState::Kill) 1238 .addImm(Imm); 1239 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1240 ResultReg).addReg(II.ImplicitDefs[0]); 1241 } 1242 return ResultReg; 1243} 1244 1245unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, 1246 const TargetRegisterClass *RC, 1247 uint64_t Imm) { 1248 unsigned ResultReg = createResultReg(RC); 1249 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1250 1251 if (II.getNumDefs() >= 1) 1252 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); 1253 else { 1254 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm); 1255 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1256 ResultReg).addReg(II.ImplicitDefs[0]); 1257 } 1258 return ResultReg; 1259} 1260 1261unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode, 1262 const TargetRegisterClass *RC, 1263 uint64_t Imm1, uint64_t Imm2) { 1264 unsigned ResultReg = createResultReg(RC); 1265 const TargetInstrDesc &II = TII.get(MachineInstOpcode); 1266 1267 if (II.getNumDefs() >= 1) 1268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 1269 .addImm(Imm1).addImm(Imm2); 1270 else { 1271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2); 1272 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 1273 ResultReg).addReg(II.ImplicitDefs[0]); 1274 } 1275 return ResultReg; 1276} 1277 1278unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, 1279 unsigned Op0, bool Op0IsKill, 1280 uint32_t Idx) { 1281 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 1282 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 1283 "Cannot yet extract from physregs"); 1284 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 1285 DL, TII.get(TargetOpcode::COPY), ResultReg) 1286 .addReg(Op0, getKillRegState(Op0IsKill), Idx); 1287 return ResultReg; 1288} 1289 1290/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op 1291/// with all but the least significant bit set to zero. 1292unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) { 1293 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1); 1294} 1295 1296/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. 1297/// Emit code to ensure constants are copied into registers when needed. 1298/// Remember the virtual registers that need to be added to the Machine PHI 1299/// nodes as input. We cannot just directly add them, because expansion 1300/// might result in multiple MBB's for one BB. As such, the start of the 1301/// BB might correspond to a different MBB than the end. 1302bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 1303 const TerminatorInst *TI = LLVMBB->getTerminator(); 1304 1305 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 1306 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size(); 1307 1308 // Check successor nodes' PHI nodes that expect a constant to be available 1309 // from this block. 1310 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 1311 const BasicBlock *SuccBB = TI->getSuccessor(succ); 1312 if (!isa<PHINode>(SuccBB->begin())) continue; 1313 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 1314 1315 // If this terminator has multiple identical successors (common for 1316 // switches), only handle each succ once. 1317 if (!SuccsHandled.insert(SuccMBB)) continue; 1318 1319 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 1320 1321 // At this point we know that there is a 1-1 correspondence between LLVM PHI 1322 // nodes and Machine PHI nodes, but the incoming operands have not been 1323 // emitted yet. 1324 for (BasicBlock::const_iterator I = SuccBB->begin(); 1325 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 1326 1327 // Ignore dead phi's. 1328 if (PN->use_empty()) continue; 1329 1330 // Only handle legal types. Two interesting things to note here. First, 1331 // by bailing out early, we may leave behind some dead instructions, 1332 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its 1333 // own moves. Second, this check is necessary because FastISel doesn't 1334 // use CreateRegs to create registers, so it always creates 1335 // exactly one register for each non-void instruction. 1336 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); 1337 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { 1338 // Promote MVT::i1. 1339 if (VT == MVT::i1) 1340 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT); 1341 else { 1342 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1343 return false; 1344 } 1345 } 1346 1347 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 1348 1349 // Set the DebugLoc for the copy. Prefer the location of the operand 1350 // if there is one; use the location of the PHI otherwise. 1351 DL = PN->getDebugLoc(); 1352 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp)) 1353 DL = Inst->getDebugLoc(); 1354 1355 unsigned Reg = getRegForValue(PHIOp); 1356 if (Reg == 0) { 1357 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); 1358 return false; 1359 } 1360 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg)); 1361 DL = DebugLoc(); 1362 } 1363 } 1364 1365 return true; 1366} 1367